1977001aaSXing Zheng/* 2977001aaSXing Zheng * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3977001aaSXing Zheng * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5977001aaSXing Zheng */ 6977001aaSXing Zheng 7977001aaSXing Zheng#include <m0_param.h> 8977001aaSXing Zheng 9977001aaSXing ZhengOUTPUT_FORMAT("elf32-littlearm") 10977001aaSXing Zheng 11977001aaSXing ZhengSECTIONS { 12977001aaSXing Zheng .m0_bin 0 : { 13977001aaSXing Zheng KEEP(*(.isr_vector)) 14977001aaSXing Zheng ASSERT(. == 0xc0, "ISR vector has the wrong size."); 15977001aaSXing Zheng ASSERT(. == PARAM_ADDR, "M0 params should go right behind ISR table."); 16977001aaSXing Zheng . += PARAM_M0_SIZE; 17977001aaSXing Zheng *(.text*) 18977001aaSXing Zheng *(.rodata*) 19977001aaSXing Zheng *(.data*) 20977001aaSXing Zheng *(.bss*) 21977001aaSXing Zheng . = ALIGN(8); 22977001aaSXing Zheng *(.co_stack*) 23977001aaSXing Zheng } 24977001aaSXing Zheng 25977001aaSXing Zheng /DISCARD/ : { *(.comment) *(.note*) } 26977001aaSXing Zheng} 27