1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <dram_regs.h> 32 #include <m0_param.h> 33 #include <pmu_bits.h> 34 #include <pmu_regs.h> 35 #include "misc_regs.h" 36 #include "rk3399_mcu.h" 37 38 static uint32_t gatedis_con0; 39 40 static void idle_port(void) 41 { 42 gatedis_con0 = mmio_read_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0); 43 mmio_write_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0, 0x3fffffff); 44 45 mmio_setbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, 46 (1 << PMU_IDLE_REQ_MSCH0) | (1 << PMU_IDLE_REQ_MSCH1)); 47 while ((mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & 48 ((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0))) != 49 ((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0))) 50 continue; 51 } 52 53 static void deidle_port(void) 54 { 55 mmio_clrbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, 56 (1 << PMU_IDLE_REQ_MSCH0) | (1 << PMU_IDLE_REQ_MSCH1)); 57 while (mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & 58 ((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0))) 59 continue; 60 61 /* document is wrong, PMU_CRU_GATEDIS_CON0 do not need set MASK BIT */ 62 mmio_write_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0, gatedis_con0); 63 } 64 65 static void ddr_set_pll(void) 66 { 67 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_SLOW_MODE)); 68 69 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(1)); 70 mmio_write_32(CRU_BASE + CRU_DPLL_CON0, 71 mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON0)); 72 mmio_write_32(CRU_BASE + CRU_DPLL_CON1, 73 mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON1)); 74 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(0)); 75 76 while ((mmio_read_32(CRU_BASE + CRU_DPLL_CON2) & (1u << 31)) == 0) 77 continue; 78 79 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_NORMAL_MODE)); 80 } 81 82 void handle_dram(void) 83 { 84 mmio_setbits_32(PHY_REG(0, 927), (1 << 22)); 85 mmio_setbits_32(PHY_REG(1, 927), (1 << 22)); 86 idle_port(); 87 88 mmio_write_32(CIC_BASE + CIC_CTRL0, 89 (((0x3 << 4) | (1 << 2) | 1) << 16) | 90 (1 << 2) | 1 | 91 mmio_read_32(PARAM_ADDR + PARAM_FREQ_SELECT)); 92 while ((mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 2)) == 0) 93 continue; 94 95 ddr_set_pll(); 96 mmio_write_32(CIC_BASE + CIC_CTRL0, 0x20002); 97 while ((mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 0)) == 0) 98 continue; 99 100 deidle_port(); 101 mmio_clrbits_32(PHY_REG(0, 927), (1 << 22)); 102 mmio_clrbits_32(PHY_REG(1, 927), (1 << 22)); 103 } 104