1977001aaSXing Zheng /* 2977001aaSXing Zheng * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3977001aaSXing Zheng * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5977001aaSXing Zheng */ 6977001aaSXing Zheng 71830f790SXing Zheng #include <dram_regs.h> 8977001aaSXing Zheng #include <m0_param.h> 91830f790SXing Zheng #include <pmu_bits.h> 101830f790SXing Zheng #include <pmu_regs.h> 111830f790SXing Zheng #include "misc_regs.h" 12977001aaSXing Zheng #include "rk3399_mcu.h" 13977001aaSXing Zheng 141830f790SXing Zheng static uint32_t gatedis_con0; 15ef0a6bfcSLin Huang 16977001aaSXing Zheng static void idle_port(void) 17977001aaSXing Zheng { 181830f790SXing Zheng gatedis_con0 = mmio_read_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0); 191830f790SXing Zheng mmio_write_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0, 0x3fffffff); 201830f790SXing Zheng 21977001aaSXing Zheng mmio_setbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, 221830f790SXing Zheng (1 << PMU_IDLE_REQ_MSCH0) | (1 << PMU_IDLE_REQ_MSCH1)); 23977001aaSXing Zheng while ((mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & 241830f790SXing Zheng ((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0))) != 251830f790SXing Zheng ((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0))) 26977001aaSXing Zheng continue; 27977001aaSXing Zheng } 28977001aaSXing Zheng 29977001aaSXing Zheng static void deidle_port(void) 30977001aaSXing Zheng { 31977001aaSXing Zheng mmio_clrbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, 321830f790SXing Zheng (1 << PMU_IDLE_REQ_MSCH0) | (1 << PMU_IDLE_REQ_MSCH1)); 33977001aaSXing Zheng while (mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & 341830f790SXing Zheng ((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0))) 35977001aaSXing Zheng continue; 36ef0a6bfcSLin Huang 37ef0a6bfcSLin Huang /* document is wrong, PMU_CRU_GATEDIS_CON0 do not need set MASK BIT */ 381830f790SXing Zheng mmio_write_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0, gatedis_con0); 39977001aaSXing Zheng } 40977001aaSXing Zheng 41977001aaSXing Zheng static void ddr_set_pll(void) 42977001aaSXing Zheng { 431830f790SXing Zheng mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_SLOW_MODE)); 44977001aaSXing Zheng 451830f790SXing Zheng mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(1)); 461830f790SXing Zheng mmio_write_32(CRU_BASE + CRU_DPLL_CON0, 47977001aaSXing Zheng mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON0)); 481830f790SXing Zheng mmio_write_32(CRU_BASE + CRU_DPLL_CON1, 49977001aaSXing Zheng mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON1)); 501830f790SXing Zheng mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(0)); 51977001aaSXing Zheng 521830f790SXing Zheng while ((mmio_read_32(CRU_BASE + CRU_DPLL_CON2) & (1u << 31)) == 0) 53977001aaSXing Zheng continue; 54977001aaSXing Zheng 551830f790SXing Zheng mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_NORMAL_MODE)); 56977001aaSXing Zheng } 57977001aaSXing Zheng 58977001aaSXing Zheng void handle_dram(void) 59977001aaSXing Zheng { 6050bde47fSDerek Basehore mmio_setbits_32(PHY_REG(0, 927), (1 << 22)); 6150bde47fSDerek Basehore mmio_setbits_32(PHY_REG(1, 927), (1 << 22)); 62977001aaSXing Zheng idle_port(); 63977001aaSXing Zheng 641830f790SXing Zheng mmio_write_32(CIC_BASE + CIC_CTRL0, 65977001aaSXing Zheng (((0x3 << 4) | (1 << 2) | 1) << 16) | 66977001aaSXing Zheng (1 << 2) | 1 | 67977001aaSXing Zheng mmio_read_32(PARAM_ADDR + PARAM_FREQ_SELECT)); 681830f790SXing Zheng while ((mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 2)) == 0) 69977001aaSXing Zheng continue; 70977001aaSXing Zheng 71977001aaSXing Zheng ddr_set_pll(); 721830f790SXing Zheng mmio_write_32(CIC_BASE + CIC_CTRL0, 0x20002); 731830f790SXing Zheng while ((mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 0)) == 0) 74977001aaSXing Zheng continue; 75977001aaSXing Zheng 76977001aaSXing Zheng deidle_port(); 7750bde47fSDerek Basehore mmio_clrbits_32(PHY_REG(0, 927), (1 << 22)); 7850bde47fSDerek Basehore mmio_clrbits_32(PHY_REG(1, 927), (1 << 22)); 79977001aaSXing Zheng } 80