12831bc3aSCaesar Wang /* 22831bc3aSCaesar Wang * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 32831bc3aSCaesar Wang * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 52831bc3aSCaesar Wang */ 62831bc3aSCaesar Wang 72831bc3aSCaesar Wang #ifndef __SOC_ROCKCHIP_RK3399_SUSPEND_H__ 82831bc3aSCaesar Wang #define __SOC_ROCKCHIP_RK3399_SUSPEND_H__ 92831bc3aSCaesar Wang #include <dram.h> 102831bc3aSCaesar Wang 112831bc3aSCaesar Wang #define KHz (1000) 122831bc3aSCaesar Wang #define MHz (1000 * KHz) 132831bc3aSCaesar Wang #define GHz (1000 * MHz) 142831bc3aSCaesar Wang 152831bc3aSCaesar Wang #define PI_CA_TRAINING (1 << 0) 162831bc3aSCaesar Wang #define PI_WRITE_LEVELING (1 << 1) 172831bc3aSCaesar Wang #define PI_READ_GATE_TRAINING (1 << 2) 182831bc3aSCaesar Wang #define PI_READ_LEVELING (1 << 3) 192831bc3aSCaesar Wang #define PI_WDQ_LEVELING (1 << 4) 202831bc3aSCaesar Wang #define PI_FULL_TRAINING (0xff) 212831bc3aSCaesar Wang 222831bc3aSCaesar Wang void dmc_save(void); 232831bc3aSCaesar Wang __sramfunc void dmc_restore(void); 242831bc3aSCaesar Wang __sramfunc void sram_regcpy(uintptr_t dst, uintptr_t src, uint32_t num); 252831bc3aSCaesar Wang 262831bc3aSCaesar Wang #endif /* __DRAM_H__ */ 27