1*2831bc3aSCaesar Wang /* 2*2831bc3aSCaesar Wang * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3*2831bc3aSCaesar Wang * 4*2831bc3aSCaesar Wang * Redistribution and use in source and binary forms, with or without 5*2831bc3aSCaesar Wang * modification, are permitted provided that the following conditions are met: 6*2831bc3aSCaesar Wang * 7*2831bc3aSCaesar Wang * Redistributions of source code must retain the above copyright notice, this 8*2831bc3aSCaesar Wang * list of conditions and the following disclaimer. 9*2831bc3aSCaesar Wang * 10*2831bc3aSCaesar Wang * Redistributions in binary form must reproduce the above copyright notice, 11*2831bc3aSCaesar Wang * this list of conditions and the following disclaimer in the documentation 12*2831bc3aSCaesar Wang * and/or other materials provided with the distribution. 13*2831bc3aSCaesar Wang * 14*2831bc3aSCaesar Wang * Neither the name of ARM nor the names of its contributors may be used 15*2831bc3aSCaesar Wang * to endorse or promote products derived from this software without specific 16*2831bc3aSCaesar Wang * prior written permission. 17*2831bc3aSCaesar Wang * 18*2831bc3aSCaesar Wang * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*2831bc3aSCaesar Wang * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*2831bc3aSCaesar Wang * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*2831bc3aSCaesar Wang * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*2831bc3aSCaesar Wang * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*2831bc3aSCaesar Wang * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*2831bc3aSCaesar Wang * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*2831bc3aSCaesar Wang * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*2831bc3aSCaesar Wang * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*2831bc3aSCaesar Wang * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*2831bc3aSCaesar Wang * POSSIBILITY OF SUCH DAMAGE. 29*2831bc3aSCaesar Wang */ 30*2831bc3aSCaesar Wang 31*2831bc3aSCaesar Wang #ifndef __SOC_ROCKCHIP_RK3399_SUSPEND_H__ 32*2831bc3aSCaesar Wang #define __SOC_ROCKCHIP_RK3399_SUSPEND_H__ 33*2831bc3aSCaesar Wang #include <dram.h> 34*2831bc3aSCaesar Wang 35*2831bc3aSCaesar Wang #define KHz (1000) 36*2831bc3aSCaesar Wang #define MHz (1000 * KHz) 37*2831bc3aSCaesar Wang #define GHz (1000 * MHz) 38*2831bc3aSCaesar Wang 39*2831bc3aSCaesar Wang #define PI_CA_TRAINING (1 << 0) 40*2831bc3aSCaesar Wang #define PI_WRITE_LEVELING (1 << 1) 41*2831bc3aSCaesar Wang #define PI_READ_GATE_TRAINING (1 << 2) 42*2831bc3aSCaesar Wang #define PI_READ_LEVELING (1 << 3) 43*2831bc3aSCaesar Wang #define PI_WDQ_LEVELING (1 << 4) 44*2831bc3aSCaesar Wang #define PI_FULL_TRAINING (0xff) 45*2831bc3aSCaesar Wang 46*2831bc3aSCaesar Wang void dmc_save(void); 47*2831bc3aSCaesar Wang __sramfunc void dmc_restore(void); 48*2831bc3aSCaesar Wang __sramfunc void sram_regcpy(uintptr_t dst, uintptr_t src, uint32_t num); 49*2831bc3aSCaesar Wang 50*2831bc3aSCaesar Wang #endif /* __DRAM_H__ */ 51