1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef _DRAM_SPEC_TIMING_HEAD_ 32 #define _DRAM_SPEC_TIMING_HEAD_ 33 #include <stdint.h> 34 35 enum { 36 DDR3 = 3, 37 LPDDR2 = 5, 38 LPDDR3 = 6, 39 LPDDR4 = 7, 40 UNUSED = 0xFF 41 }; 42 43 enum ddr3_speed_rate { 44 /* 5-5-5 */ 45 DDR3_800D = 0, 46 /* 6-6-6 */ 47 DDR3_800E = 1, 48 /* 6-6-6 */ 49 DDR3_1066E = 2, 50 /* 7-7-7 */ 51 DDR3_1066F = 3, 52 /* 8-8-8 */ 53 DDR3_1066G = 4, 54 /* 7-7-7 */ 55 DDR3_1333F = 5, 56 /* 8-8-8 */ 57 DDR3_1333G = 6, 58 /* 9-9-9 */ 59 DDR3_1333H = 7, 60 /* 10-10-10 */ 61 DDR3_1333J = 8, 62 /* 8-8-8 */ 63 DDR3_1600G = 9, 64 /* 9-9-9 */ 65 DDR3_1600H = 10, 66 /* 10-10-10 */ 67 DDR3_1600J = 11, 68 /* 11-11-11 */ 69 DDR3_1600K = 12, 70 /* 10-10-10 */ 71 DDR3_1866J = 13, 72 /* 11-11-11 */ 73 DDR3_1866K = 14, 74 /* 12-12-12 */ 75 DDR3_1866L = 15, 76 /* 13-13-13 */ 77 DDR3_1866M = 16, 78 /* 11-11-11 */ 79 DDR3_2133K = 17, 80 /* 12-12-12 */ 81 DDR3_2133L = 18, 82 /* 13-13-13 */ 83 DDR3_2133M = 19, 84 /* 14-14-14 */ 85 DDR3_2133N = 20, 86 DDR3_DEFAULT = 21, 87 }; 88 89 #define max(a, b) (((a) > (b)) ? (a) : (b)) 90 #define range(mi, val, ma) (((ma) > (val)) ? (max(mi, val)) : (ma)) 91 92 struct dram_timing_t { 93 /* unit MHz */ 94 uint32_t mhz; 95 /* some timing unit is us */ 96 uint32_t tinit1; 97 uint32_t tinit2; 98 uint32_t tinit3; 99 uint32_t tinit4; 100 uint32_t tinit5; 101 /* reset low, DDR3:200us */ 102 uint32_t trstl; 103 /* reset high to CKE high, DDR3:500us */ 104 uint32_t trsth; 105 uint32_t trefi; 106 /* base */ 107 uint32_t trcd; 108 /* trp per bank */ 109 uint32_t trppb; 110 /* trp all bank */ 111 uint32_t trp; 112 uint32_t twr; 113 uint32_t tdal; 114 uint32_t trtp; 115 uint32_t trc; 116 uint32_t trrd; 117 uint32_t tccd; 118 uint32_t twtr; 119 uint32_t trtw; 120 uint32_t tras_max; 121 uint32_t tras_min; 122 uint32_t tfaw; 123 uint32_t trfc; 124 uint32_t tdqsck; 125 uint32_t tdqsck_max; 126 /* pd or sr */ 127 uint32_t txsr; 128 uint32_t txsnr; 129 uint32_t txp; 130 uint32_t txpdll; 131 uint32_t tdllk; 132 uint32_t tcke; 133 uint32_t tckesr; 134 uint32_t tcksre; 135 uint32_t tcksrx; 136 uint32_t tdpd; 137 /* mode regiter timing */ 138 uint32_t tmod; 139 uint32_t tmrd; 140 uint32_t tmrr; 141 uint32_t tmrri; 142 /* ODT */ 143 uint32_t todton; 144 /* ZQ */ 145 uint32_t tzqinit; 146 uint32_t tzqcs; 147 uint32_t tzqoper; 148 uint32_t tzqreset; 149 /* Write Leveling */ 150 uint32_t twlmrd; 151 uint32_t twlo; 152 uint32_t twldqsen; 153 /* CA Training */ 154 uint32_t tcackel; 155 uint32_t tcaent; 156 uint32_t tcamrd; 157 uint32_t tcackeh; 158 uint32_t tcaext; 159 uint32_t tadr; 160 uint32_t tmrz; 161 uint32_t tcacd; 162 /* mode register */ 163 uint32_t mr[4]; 164 uint32_t mr11; 165 /* lpddr4 spec */ 166 uint32_t mr12; 167 uint32_t mr13; 168 uint32_t mr14; 169 uint32_t mr16; 170 uint32_t mr17; 171 uint32_t mr20; 172 uint32_t mr22; 173 uint32_t tccdmw; 174 uint32_t tppd; 175 uint32_t tescke; 176 uint32_t tsr; 177 uint32_t tcmdcke; 178 uint32_t tcscke; 179 uint32_t tckelcs; 180 uint32_t tcsckeh; 181 uint32_t tckehcs; 182 uint32_t tmrwckel; 183 uint32_t tzqcal; 184 uint32_t tzqlat; 185 uint32_t tzqcke; 186 uint32_t tvref_long; 187 uint32_t tvref_short; 188 uint32_t tvrcg_enable; 189 uint32_t tvrcg_disable; 190 uint32_t tfc_long; 191 uint32_t tckfspe; 192 uint32_t tckfspx; 193 uint32_t tckehcmd; 194 uint32_t tckelcmd; 195 uint32_t tckelpd; 196 uint32_t tckckel; 197 /* other */ 198 uint32_t al; 199 uint32_t cl; 200 uint32_t cwl; 201 uint32_t bl; 202 }; 203 204 struct dram_info_t { 205 /* speed_rate only used when DDR3 */ 206 enum ddr3_speed_rate speed_rate; 207 /* 1: use CS0, 2: use CS0 and CS1 */ 208 uint32_t cs_cnt; 209 /* give the max per-die capability on each rank/cs */ 210 uint32_t per_die_capability[2]; 211 }; 212 213 struct timing_related_config { 214 struct dram_info_t dram_info[2]; 215 uint32_t dram_type; 216 /* MHz */ 217 uint32_t freq; 218 uint32_t ch_cnt; 219 uint32_t bl; 220 /* 1:auto precharge, 0:never auto precharge */ 221 uint32_t ap; 222 /* 223 * 1:dll bypass, 0:dll normal 224 * dram and controller dll bypass at the same time 225 */ 226 uint32_t dllbp; 227 /* 1:odt enable, 0:odt disable */ 228 uint32_t odt; 229 /* 1:enable, 0:disabe */ 230 uint32_t rdbi; 231 uint32_t wdbi; 232 /* dram driver strength */ 233 uint32_t dramds; 234 /* dram ODT, if odt=0, this parameter invalid */ 235 uint32_t dramodt; 236 /* 237 * ca ODT, if odt=0, this parameter invalid 238 * it only used by LPDDR4 239 */ 240 uint32_t caodt; 241 }; 242 243 /* mr0 for ddr3 */ 244 #define DDR3_BL8 (0) 245 #define DDR3_BC4_8 (1) 246 #define DDR3_BC4 (2) 247 #define DDR3_CL(n) (((((n) - 4) & 0x7) << 4)\ 248 | ((((n) - 4) & 0x8) >> 1)) 249 #define DDR3_WR(n) (((n) & 0x7) << 9) 250 #define DDR3_DLL_RESET (1 << 8) 251 #define DDR3_DLL_DERESET (0 << 8) 252 253 /* mr1 for ddr3 */ 254 #define DDR3_DLL_ENABLE (0) 255 #define DDR3_DLL_DISABLE (1) 256 #define DDR3_MR1_AL(n) (((n) & 0x3) << 3) 257 258 #define DDR3_DS_40 (0) 259 #define DDR3_DS_34 (1 << 1) 260 #define DDR3_RTT_NOM_DIS (0) 261 #define DDR3_RTT_NOM_60 (1 << 2) 262 #define DDR3_RTT_NOM_120 (1 << 6) 263 #define DDR3_RTT_NOM_40 ((1 << 2) | (1 << 6)) 264 #define DDR3_TDQS (1 << 11) 265 266 /* mr2 for ddr3 */ 267 #define DDR3_MR2_CWL(n) ((((n) - 5) & 0x7) << 3) 268 #define DDR3_RTT_WR_DIS (0) 269 #define DDR3_RTT_WR_60 (1 << 9) 270 #define DDR3_RTT_WR_120 (2 << 9) 271 272 /* 273 * MR0 (Device Information) 274 * 0:DAI complete, 1:DAI still in progress 275 */ 276 #define LPDDR2_DAI (0x1) 277 /* 0:S2 or S4 SDRAM, 1:NVM */ 278 #define LPDDR2_DI (0x1 << 1) 279 /* 0:DNV not supported, 1:DNV supported */ 280 #define LPDDR2_DNVI (0x1 << 2) 281 #define LPDDR2_RZQI (0x3 << 3) 282 283 /* 284 * 00:RZQ self test not supported, 285 * 01:ZQ-pin may connect to VDDCA or float 286 * 10:ZQ-pin may short to GND. 287 * 11:ZQ-pin self test completed, no error condition detected. 288 */ 289 290 /* MR1 (Device Feature) */ 291 #define LPDDR2_BL4 (0x2) 292 #define LPDDR2_BL8 (0x3) 293 #define LPDDR2_BL16 (0x4) 294 #define LPDDR2_N_WR(n) (((n) - 2) << 5) 295 296 /* MR2 (Device Feature 2) */ 297 #define LPDDR2_RL3_WL1 (0x1) 298 #define LPDDR2_RL4_WL2 (0x2) 299 #define LPDDR2_RL5_WL2 (0x3) 300 #define LPDDR2_RL6_WL3 (0x4) 301 #define LPDDR2_RL7_WL4 (0x5) 302 #define LPDDR2_RL8_WL4 (0x6) 303 304 /* MR3 (IO Configuration 1) */ 305 #define LPDDR2_DS_34 (0x1) 306 #define LPDDR2_DS_40 (0x2) 307 #define LPDDR2_DS_48 (0x3) 308 #define LPDDR2_DS_60 (0x4) 309 #define LPDDR2_DS_80 (0x6) 310 /* optional */ 311 #define LPDDR2_DS_120 (0x7) 312 313 /* MR4 (Device Temperature) */ 314 #define LPDDR2_TREF_MASK (0x7) 315 #define LPDDR2_4_TREF (0x1) 316 #define LPDDR2_2_TREF (0x2) 317 #define LPDDR2_1_TREF (0x3) 318 #define LPDDR2_025_TREF (0x5) 319 #define LPDDR2_025_TREF_DERATE (0x6) 320 321 #define LPDDR2_TUF (0x1 << 7) 322 323 /* MR8 (Basic configuration 4) */ 324 #define LPDDR2_S4 (0x0) 325 #define LPDDR2_S2 (0x1) 326 #define LPDDR2_N (0x2) 327 /* Unit:MB */ 328 #define LPDDR2_DENSITY(mr8) (8 << (((mr8) >> 2) & 0xf)) 329 #define LPDDR2_IO_WIDTH(mr8) (32 >> (((mr8) >> 6) & 0x3)) 330 331 /* MR10 (Calibration) */ 332 #define LPDDR2_ZQINIT (0xff) 333 #define LPDDR2_ZQCL (0xab) 334 #define LPDDR2_ZQCS (0x56) 335 #define LPDDR2_ZQRESET (0xc3) 336 337 /* MR16 (PASR Bank Mask), S2 SDRAM Only */ 338 #define LPDDR2_PASR_FULL (0x0) 339 #define LPDDR2_PASR_1_2 (0x1) 340 #define LPDDR2_PASR_1_4 (0x2) 341 #define LPDDR2_PASR_1_8 (0x3) 342 343 /* 344 * MR0 (Device Information) 345 * 0:DAI complete, 346 * 1:DAI still in progress 347 */ 348 #define LPDDR3_DAI (0x1) 349 /* 350 * 00:RZQ self test not supported, 351 * 01:ZQ-pin may connect to VDDCA or float 352 * 10:ZQ-pin may short to GND. 353 * 11:ZQ-pin self test completed, no error condition detected. 354 */ 355 #define LPDDR3_RZQI (0x3 << 3) 356 /* 357 * 0:DRAM does not support WL(Set B), 358 * 1:DRAM support WL(Set B) 359 */ 360 #define LPDDR3_WL_SUPOT (1 << 6) 361 /* 362 * 0:DRAM does not support RL=3,nWR=3,WL=1; 363 * 1:DRAM supports RL=3,nWR=3,WL=1 for frequencies <=166 364 */ 365 #define LPDDR3_RL3_SUPOT (1 << 7) 366 367 /* MR1 (Device Feature) */ 368 #define LPDDR3_BL8 (0x3) 369 #define LPDDR3_N_WR(n) ((n) << 5) 370 371 /* MR2 (Device Feature 2), WL Set A,default */ 372 /* <=166MHz,optional*/ 373 #define LPDDR3_RL3_WL1 (0x1) 374 /* <=400MHz*/ 375 #define LPDDR3_RL6_WL3 (0x4) 376 /* <=533MHz*/ 377 #define LPDDR3_RL8_WL4 (0x6) 378 /* <=600MHz*/ 379 #define LPDDR3_RL9_WL5 (0x7) 380 /* <=667MHz,default*/ 381 #define LPDDR3_RL10_WL6 (0x8) 382 /* <=733MHz*/ 383 #define LPDDR3_RL11_WL6 (0x9) 384 /* <=800MHz*/ 385 #define LPDDR3_RL12_WL6 (0xa) 386 /* <=933MHz*/ 387 #define LPDDR3_RL14_WL8 (0xc) 388 /* <=1066MHz*/ 389 #define LPDDR3_RL16_WL8 (0xe) 390 391 /* WL Set B, optional */ 392 /* <=667MHz,default*/ 393 #define LPDDR3_RL10_WL8 (0x8) 394 /* <=733MHz*/ 395 #define LPDDR3_RL11_WL9 (0x9) 396 /* <=800MHz*/ 397 #define LPDDR3_RL12_WL9 (0xa) 398 /* <=933MHz*/ 399 #define LPDDR3_RL14_WL11 (0xc) 400 /* <=1066MHz*/ 401 #define LPDDR3_RL16_WL13 (0xe) 402 403 /* 1:enable nWR programming > 9(default)*/ 404 #define LPDDR3_N_WRE (1 << 4) 405 /* 1:Select WL Set B*/ 406 #define LPDDR3_WL_S (1 << 6) 407 /* 1:enable*/ 408 #define LPDDR3_WR_LEVEL (1 << 7) 409 410 /* MR3 (IO Configuration 1) */ 411 #define LPDDR3_DS_34 (0x1) 412 #define LPDDR3_DS_40 (0x2) 413 #define LPDDR3_DS_48 (0x3) 414 #define LPDDR3_DS_60 (0x4) 415 #define LPDDR3_DS_80 (0x6) 416 #define LPDDR3_DS_34D_40U (0x9) 417 #define LPDDR3_DS_40D_48U (0xa) 418 #define LPDDR3_DS_34D_48U (0xb) 419 420 /* MR4 (Device Temperature) */ 421 #define LPDDR3_TREF_MASK (0x7) 422 /* SDRAM Low temperature operating limit exceeded */ 423 #define LPDDR3_LT_EXED (0x0) 424 #define LPDDR3_4_TREF (0x1) 425 #define LPDDR3_2_TREF (0x2) 426 #define LPDDR3_1_TREF (0x3) 427 #define LPDDR3_05_TREF (0x4) 428 #define LPDDR3_025_TREF (0x5) 429 #define LPDDR3_025_TREF_DERATE (0x6) 430 /* SDRAM High temperature operating limit exceeded */ 431 #define LPDDR3_HT_EXED (0x7) 432 433 /* 1:value has changed since last read of MR4 */ 434 #define LPDDR3_TUF (0x1 << 7) 435 436 /* MR8 (Basic configuration 4) */ 437 #define LPDDR3_S8 (0x3) 438 #define LPDDR3_DENSITY(mr8) (8 << (((mr8) >> 2) & 0xf)) 439 #define LPDDR3_IO_WIDTH(mr8) (32 >> (((mr8) >> 6) & 0x3)) 440 441 /* MR10 (Calibration) */ 442 #define LPDDR3_ZQINIT (0xff) 443 #define LPDDR3_ZQCL (0xab) 444 #define LPDDR3_ZQCS (0x56) 445 #define LPDDR3_ZQRESET (0xc3) 446 447 /* MR11 (ODT Control) */ 448 #define LPDDR3_ODT_60 (1) 449 #define LPDDR3_ODT_120 (2) 450 #define LPDDR3_ODT_240 (3) 451 #define LPDDR3_ODT_DIS (0) 452 453 /* MR2 (Device Feature 2) */ 454 /* RL & nRTP for DBI-RD Disabled */ 455 #define LPDDR4_RL6_NRTP8 (0x0) 456 #define LPDDR4_RL10_NRTP8 (0x1) 457 #define LPDDR4_RL14_NRTP8 (0x2) 458 #define LPDDR4_RL20_NRTP8 (0x3) 459 #define LPDDR4_RL24_NRTP10 (0x4) 460 #define LPDDR4_RL28_NRTP12 (0x5) 461 #define LPDDR4_RL32_NRTP14 (0x6) 462 #define LPDDR4_RL36_NRTP16 (0x7) 463 /* RL & nRTP for DBI-RD Disabled */ 464 #define LPDDR4_RL12_NRTP8 (0x1) 465 #define LPDDR4_RL16_NRTP8 (0x2) 466 #define LPDDR4_RL22_NRTP8 (0x3) 467 #define LPDDR4_RL28_NRTP10 (0x4) 468 #define LPDDR4_RL32_NRTP12 (0x5) 469 #define LPDDR4_RL36_NRTP14 (0x6) 470 #define LPDDR4_RL40_NRTP16 (0x7) 471 /* WL Set A,default */ 472 #define LPDDR4_A_WL4 (0x0) 473 #define LPDDR4_A_WL6 (0x1) 474 #define LPDDR4_A_WL8 (0x2) 475 #define LPDDR4_A_WL10 (0x3) 476 #define LPDDR4_A_WL12 (0x4) 477 #define LPDDR4_A_WL14 (0x5) 478 #define LPDDR4_A_WL16 (0x6) 479 #define LPDDR4_A_WL18 (0x7) 480 /* WL Set B, optional */ 481 #define LPDDR4_B_WL4 (0x0 << 3) 482 #define LPDDR4_B_WL8 (0x1 << 3) 483 #define LPDDR4_B_WL12 (0x2 << 3) 484 #define LPDDR4_B_WL18 (0x3 << 3) 485 #define LPDDR4_B_WL22 (0x4 << 3) 486 #define LPDDR4_B_WL26 (0x5 << 3) 487 #define LPDDR4_B_WL30 (0x6 << 3) 488 #define LPDDR4_B_WL34 (0x7 << 3) 489 /* 1:Select WL Set B*/ 490 #define LPDDR4_WL_B (1 << 6) 491 /* 1:enable*/ 492 #define LPDDR4_WR_LEVEL (1 << 7) 493 494 /* MR3 */ 495 #define LPDDR4_VDDQ_2_5 (0) 496 #define LPDDR4_VDDQ_3 (1) 497 #define LPDDR4_WRPST_0_5_TCK (0 << 1) 498 #define LPDDR4_WRPST_1_5_TCK (1 << 1) 499 #define LPDDR4_PPR_EN (1 << 2) 500 /* PDDS */ 501 #define LPDDR4_PDDS_240 (0x1 << 3) 502 #define LPDDR4_PDDS_120 (0x2 << 3) 503 #define LPDDR4_PDDS_80 (0x3 << 3) 504 #define LPDDR4_PDDS_60 (0x4 << 3) 505 #define LPDDR4_PDDS_48 (0x5 << 3) 506 #define LPDDR4_PDDS_40 (0x6 << 3) 507 #define LPDDR4_DBI_RD_EN (1 << 6) 508 #define LPDDR4_DBI_WR_EN (1 << 7) 509 510 /* MR11 (ODT Control) */ 511 #define LPDDR4_DQODT_240 (1) 512 #define LPDDR4_DQODT_120 (2) 513 #define LPDDR4_DQODT_80 (3) 514 #define LPDDR4_DQODT_60 (4) 515 #define LPDDR4_DQODT_48 (5) 516 #define LPDDR4_DQODT_40 (6) 517 #define LPDDR4_DQODT_DIS (0) 518 #define LPDDR4_CAODT_240 (1 << 4) 519 #define LPDDR4_CAODT_120 (2 << 4) 520 #define LPDDR4_CAODT_80 (3 << 4) 521 #define LPDDR4_CAODT_60 (4 << 4) 522 #define LPDDR4_CAODT_48 (5 << 4) 523 #define LPDDR4_CAODT_40 (6 << 4) 524 #define LPDDR4_CAODT_DIS (0 << 4) 525 526 /* 527 * Description: depend on input parameter "timing_config", 528 * and calculate correspond "dram_type" 529 * spec timing to "pdram_timing" 530 * parameters: 531 * input: timing_config 532 * output: pdram_timing 533 * NOTE: MR ODT is set, need to disable by controller 534 */ 535 void dram_get_parameter(struct timing_related_config *timing_config, 536 struct dram_timing_t *pdram_timing); 537 538 #endif /* _DRAM_SPEC_TIMING_HEAD_ */ 539