1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef _DRAM_SPEC_TIMING_HEAD_ 32 #define _DRAM_SPEC_TIMING_HEAD_ 33 #include <stdint.h> 34 35 enum ddr3_speed_rate { 36 /* 5-5-5 */ 37 DDR3_800D = 0, 38 /* 6-6-6 */ 39 DDR3_800E = 1, 40 /* 6-6-6 */ 41 DDR3_1066E = 2, 42 /* 7-7-7 */ 43 DDR3_1066F = 3, 44 /* 8-8-8 */ 45 DDR3_1066G = 4, 46 /* 7-7-7 */ 47 DDR3_1333F = 5, 48 /* 8-8-8 */ 49 DDR3_1333G = 6, 50 /* 9-9-9 */ 51 DDR3_1333H = 7, 52 /* 10-10-10 */ 53 DDR3_1333J = 8, 54 /* 8-8-8 */ 55 DDR3_1600G = 9, 56 /* 9-9-9 */ 57 DDR3_1600H = 10, 58 /* 10-10-10 */ 59 DDR3_1600J = 11, 60 /* 11-11-11 */ 61 DDR3_1600K = 12, 62 /* 10-10-10 */ 63 DDR3_1866J = 13, 64 /* 11-11-11 */ 65 DDR3_1866K = 14, 66 /* 12-12-12 */ 67 DDR3_1866L = 15, 68 /* 13-13-13 */ 69 DDR3_1866M = 16, 70 /* 11-11-11 */ 71 DDR3_2133K = 17, 72 /* 12-12-12 */ 73 DDR3_2133L = 18, 74 /* 13-13-13 */ 75 DDR3_2133M = 19, 76 /* 14-14-14 */ 77 DDR3_2133N = 20, 78 DDR3_DEFAULT = 21, 79 }; 80 81 #define max(a, b) (((a) > (b)) ? (a) : (b)) 82 #define range(mi, val, ma) (((ma) > (val)) ? (max(mi, val)) : (ma)) 83 84 struct dram_timing_t { 85 /* unit MHz */ 86 uint32_t mhz; 87 /* some timing unit is us */ 88 uint32_t tinit1; 89 uint32_t tinit2; 90 uint32_t tinit3; 91 uint32_t tinit4; 92 uint32_t tinit5; 93 /* reset low, DDR3:200us */ 94 uint32_t trstl; 95 /* reset high to CKE high, DDR3:500us */ 96 uint32_t trsth; 97 uint32_t trefi; 98 /* base */ 99 uint32_t trcd; 100 /* trp per bank */ 101 uint32_t trppb; 102 /* trp all bank */ 103 uint32_t trp; 104 uint32_t twr; 105 uint32_t tdal; 106 uint32_t trtp; 107 uint32_t trc; 108 uint32_t trrd; 109 uint32_t tccd; 110 uint32_t twtr; 111 uint32_t trtw; 112 uint32_t tras_max; 113 uint32_t tras_min; 114 uint32_t tfaw; 115 uint32_t trfc; 116 uint32_t tdqsck; 117 uint32_t tdqsck_max; 118 /* pd or sr */ 119 uint32_t txsr; 120 uint32_t txsnr; 121 uint32_t txp; 122 uint32_t txpdll; 123 uint32_t tdllk; 124 uint32_t tcke; 125 uint32_t tckesr; 126 uint32_t tcksre; 127 uint32_t tcksrx; 128 uint32_t tdpd; 129 /* mode regiter timing */ 130 uint32_t tmod; 131 uint32_t tmrd; 132 uint32_t tmrr; 133 uint32_t tmrri; 134 /* ODT */ 135 uint32_t todton; 136 /* ZQ */ 137 uint32_t tzqinit; 138 uint32_t tzqcs; 139 uint32_t tzqoper; 140 uint32_t tzqreset; 141 /* Write Leveling */ 142 uint32_t twlmrd; 143 uint32_t twlo; 144 uint32_t twldqsen; 145 /* CA Training */ 146 uint32_t tcackel; 147 uint32_t tcaent; 148 uint32_t tcamrd; 149 uint32_t tcackeh; 150 uint32_t tcaext; 151 uint32_t tadr; 152 uint32_t tmrz; 153 uint32_t tcacd; 154 /* mode register */ 155 uint32_t mr[4]; 156 uint32_t mr11; 157 /* lpddr4 spec */ 158 uint32_t mr12; 159 uint32_t mr13; 160 uint32_t mr14; 161 uint32_t mr16; 162 uint32_t mr17; 163 uint32_t mr20; 164 uint32_t mr22; 165 uint32_t tccdmw; 166 uint32_t tppd; 167 uint32_t tescke; 168 uint32_t tsr; 169 uint32_t tcmdcke; 170 uint32_t tcscke; 171 uint32_t tckelcs; 172 uint32_t tcsckeh; 173 uint32_t tckehcs; 174 uint32_t tmrwckel; 175 uint32_t tzqcal; 176 uint32_t tzqlat; 177 uint32_t tzqcke; 178 uint32_t tvref_long; 179 uint32_t tvref_short; 180 uint32_t tvrcg_enable; 181 uint32_t tvrcg_disable; 182 uint32_t tfc_long; 183 uint32_t tckfspe; 184 uint32_t tckfspx; 185 uint32_t tckehcmd; 186 uint32_t tckelcmd; 187 uint32_t tckelpd; 188 uint32_t tckckel; 189 /* other */ 190 uint32_t al; 191 uint32_t cl; 192 uint32_t cwl; 193 uint32_t bl; 194 }; 195 196 struct dram_info_t { 197 /* speed_rate only used when DDR3 */ 198 enum ddr3_speed_rate speed_rate; 199 /* 1: use CS0, 2: use CS0 and CS1 */ 200 uint32_t cs_cnt; 201 /* give the max per-die capability on each rank/cs */ 202 uint32_t per_die_capability[2]; 203 }; 204 205 struct timing_related_config { 206 struct dram_info_t dram_info[2]; 207 uint32_t dram_type; 208 /* MHz */ 209 uint32_t freq; 210 uint32_t ch_cnt; 211 uint32_t bl; 212 /* 1:auto precharge, 0:never auto precharge */ 213 uint32_t ap; 214 /* 215 * 1:dll bypass, 0:dll normal 216 * dram and controller dll bypass at the same time 217 */ 218 uint32_t dllbp; 219 /* 1:odt enable, 0:odt disable */ 220 uint32_t odt; 221 /* 1:enable, 0:disabe */ 222 uint32_t rdbi; 223 uint32_t wdbi; 224 /* dram driver strength */ 225 uint32_t dramds; 226 /* dram ODT, if odt=0, this parameter invalid */ 227 uint32_t dramodt; 228 /* 229 * ca ODT, if odt=0, this parameter invalid 230 * it only used by LPDDR4 231 */ 232 uint32_t caodt; 233 }; 234 235 /* mr0 for ddr3 */ 236 #define DDR3_BL8 (0) 237 #define DDR3_BC4_8 (1) 238 #define DDR3_BC4 (2) 239 #define DDR3_CL(n) (((((n) - 4) & 0x7) << 4)\ 240 | ((((n) - 4) & 0x8) >> 1)) 241 #define DDR3_WR(n) (((n) & 0x7) << 9) 242 #define DDR3_DLL_RESET (1 << 8) 243 #define DDR3_DLL_DERESET (0 << 8) 244 245 /* mr1 for ddr3 */ 246 #define DDR3_DLL_ENABLE (0) 247 #define DDR3_DLL_DISABLE (1) 248 #define DDR3_MR1_AL(n) (((n) & 0x3) << 3) 249 250 #define DDR3_DS_40 (0) 251 #define DDR3_DS_34 (1 << 1) 252 #define DDR3_RTT_NOM_DIS (0) 253 #define DDR3_RTT_NOM_60 (1 << 2) 254 #define DDR3_RTT_NOM_120 (1 << 6) 255 #define DDR3_RTT_NOM_40 ((1 << 2) | (1 << 6)) 256 #define DDR3_TDQS (1 << 11) 257 258 /* mr2 for ddr3 */ 259 #define DDR3_MR2_CWL(n) ((((n) - 5) & 0x7) << 3) 260 #define DDR3_RTT_WR_DIS (0) 261 #define DDR3_RTT_WR_60 (1 << 9) 262 #define DDR3_RTT_WR_120 (2 << 9) 263 264 /* 265 * MR0 (Device Information) 266 * 0:DAI complete, 1:DAI still in progress 267 */ 268 #define LPDDR2_DAI (0x1) 269 /* 0:S2 or S4 SDRAM, 1:NVM */ 270 #define LPDDR2_DI (0x1 << 1) 271 /* 0:DNV not supported, 1:DNV supported */ 272 #define LPDDR2_DNVI (0x1 << 2) 273 #define LPDDR2_RZQI (0x3 << 3) 274 275 /* 276 * 00:RZQ self test not supported, 277 * 01:ZQ-pin may connect to VDDCA or float 278 * 10:ZQ-pin may short to GND. 279 * 11:ZQ-pin self test completed, no error condition detected. 280 */ 281 282 /* MR1 (Device Feature) */ 283 #define LPDDR2_BL4 (0x2) 284 #define LPDDR2_BL8 (0x3) 285 #define LPDDR2_BL16 (0x4) 286 #define LPDDR2_N_WR(n) (((n) - 2) << 5) 287 288 /* MR2 (Device Feature 2) */ 289 #define LPDDR2_RL3_WL1 (0x1) 290 #define LPDDR2_RL4_WL2 (0x2) 291 #define LPDDR2_RL5_WL2 (0x3) 292 #define LPDDR2_RL6_WL3 (0x4) 293 #define LPDDR2_RL7_WL4 (0x5) 294 #define LPDDR2_RL8_WL4 (0x6) 295 296 /* MR3 (IO Configuration 1) */ 297 #define LPDDR2_DS_34 (0x1) 298 #define LPDDR2_DS_40 (0x2) 299 #define LPDDR2_DS_48 (0x3) 300 #define LPDDR2_DS_60 (0x4) 301 #define LPDDR2_DS_80 (0x6) 302 /* optional */ 303 #define LPDDR2_DS_120 (0x7) 304 305 /* MR4 (Device Temperature) */ 306 #define LPDDR2_TREF_MASK (0x7) 307 #define LPDDR2_4_TREF (0x1) 308 #define LPDDR2_2_TREF (0x2) 309 #define LPDDR2_1_TREF (0x3) 310 #define LPDDR2_025_TREF (0x5) 311 #define LPDDR2_025_TREF_DERATE (0x6) 312 313 #define LPDDR2_TUF (0x1 << 7) 314 315 /* MR8 (Basic configuration 4) */ 316 #define LPDDR2_S4 (0x0) 317 #define LPDDR2_S2 (0x1) 318 #define LPDDR2_N (0x2) 319 /* Unit:MB */ 320 #define LPDDR2_DENSITY(mr8) (8 << (((mr8) >> 2) & 0xf)) 321 #define LPDDR2_IO_WIDTH(mr8) (32 >> (((mr8) >> 6) & 0x3)) 322 323 /* MR10 (Calibration) */ 324 #define LPDDR2_ZQINIT (0xff) 325 #define LPDDR2_ZQCL (0xab) 326 #define LPDDR2_ZQCS (0x56) 327 #define LPDDR2_ZQRESET (0xc3) 328 329 /* MR16 (PASR Bank Mask), S2 SDRAM Only */ 330 #define LPDDR2_PASR_FULL (0x0) 331 #define LPDDR2_PASR_1_2 (0x1) 332 #define LPDDR2_PASR_1_4 (0x2) 333 #define LPDDR2_PASR_1_8 (0x3) 334 335 /* 336 * MR0 (Device Information) 337 * 0:DAI complete, 338 * 1:DAI still in progress 339 */ 340 #define LPDDR3_DAI (0x1) 341 /* 342 * 00:RZQ self test not supported, 343 * 01:ZQ-pin may connect to VDDCA or float 344 * 10:ZQ-pin may short to GND. 345 * 11:ZQ-pin self test completed, no error condition detected. 346 */ 347 #define LPDDR3_RZQI (0x3 << 3) 348 /* 349 * 0:DRAM does not support WL(Set B), 350 * 1:DRAM support WL(Set B) 351 */ 352 #define LPDDR3_WL_SUPOT (1 << 6) 353 /* 354 * 0:DRAM does not support RL=3,nWR=3,WL=1; 355 * 1:DRAM supports RL=3,nWR=3,WL=1 for frequencies <=166 356 */ 357 #define LPDDR3_RL3_SUPOT (1 << 7) 358 359 /* MR1 (Device Feature) */ 360 #define LPDDR3_BL8 (0x3) 361 #define LPDDR3_N_WR(n) ((n) << 5) 362 363 /* MR2 (Device Feature 2), WL Set A,default */ 364 /* <=166MHz,optional*/ 365 #define LPDDR3_RL3_WL1 (0x1) 366 /* <=400MHz*/ 367 #define LPDDR3_RL6_WL3 (0x4) 368 /* <=533MHz*/ 369 #define LPDDR3_RL8_WL4 (0x6) 370 /* <=600MHz*/ 371 #define LPDDR3_RL9_WL5 (0x7) 372 /* <=667MHz,default*/ 373 #define LPDDR3_RL10_WL6 (0x8) 374 /* <=733MHz*/ 375 #define LPDDR3_RL11_WL6 (0x9) 376 /* <=800MHz*/ 377 #define LPDDR3_RL12_WL6 (0xa) 378 /* <=933MHz*/ 379 #define LPDDR3_RL14_WL8 (0xc) 380 /* <=1066MHz*/ 381 #define LPDDR3_RL16_WL8 (0xe) 382 383 /* WL Set B, optional */ 384 /* <=667MHz,default*/ 385 #define LPDDR3_RL10_WL8 (0x8) 386 /* <=733MHz*/ 387 #define LPDDR3_RL11_WL9 (0x9) 388 /* <=800MHz*/ 389 #define LPDDR3_RL12_WL9 (0xa) 390 /* <=933MHz*/ 391 #define LPDDR3_RL14_WL11 (0xc) 392 /* <=1066MHz*/ 393 #define LPDDR3_RL16_WL13 (0xe) 394 395 /* 1:enable nWR programming > 9(default)*/ 396 #define LPDDR3_N_WRE (1 << 4) 397 /* 1:Select WL Set B*/ 398 #define LPDDR3_WL_S (1 << 6) 399 /* 1:enable*/ 400 #define LPDDR3_WR_LEVEL (1 << 7) 401 402 /* MR3 (IO Configuration 1) */ 403 #define LPDDR3_DS_34 (0x1) 404 #define LPDDR3_DS_40 (0x2) 405 #define LPDDR3_DS_48 (0x3) 406 #define LPDDR3_DS_60 (0x4) 407 #define LPDDR3_DS_80 (0x6) 408 #define LPDDR3_DS_34D_40U (0x9) 409 #define LPDDR3_DS_40D_48U (0xa) 410 #define LPDDR3_DS_34D_48U (0xb) 411 412 /* MR4 (Device Temperature) */ 413 #define LPDDR3_TREF_MASK (0x7) 414 /* SDRAM Low temperature operating limit exceeded */ 415 #define LPDDR3_LT_EXED (0x0) 416 #define LPDDR3_4_TREF (0x1) 417 #define LPDDR3_2_TREF (0x2) 418 #define LPDDR3_1_TREF (0x3) 419 #define LPDDR3_05_TREF (0x4) 420 #define LPDDR3_025_TREF (0x5) 421 #define LPDDR3_025_TREF_DERATE (0x6) 422 /* SDRAM High temperature operating limit exceeded */ 423 #define LPDDR3_HT_EXED (0x7) 424 425 /* 1:value has changed since last read of MR4 */ 426 #define LPDDR3_TUF (0x1 << 7) 427 428 /* MR8 (Basic configuration 4) */ 429 #define LPDDR3_S8 (0x3) 430 #define LPDDR3_DENSITY(mr8) (8 << (((mr8) >> 2) & 0xf)) 431 #define LPDDR3_IO_WIDTH(mr8) (32 >> (((mr8) >> 6) & 0x3)) 432 433 /* MR10 (Calibration) */ 434 #define LPDDR3_ZQINIT (0xff) 435 #define LPDDR3_ZQCL (0xab) 436 #define LPDDR3_ZQCS (0x56) 437 #define LPDDR3_ZQRESET (0xc3) 438 439 /* MR11 (ODT Control) */ 440 #define LPDDR3_ODT_60 (1) 441 #define LPDDR3_ODT_120 (2) 442 #define LPDDR3_ODT_240 (3) 443 #define LPDDR3_ODT_DIS (0) 444 445 /* MR2 (Device Feature 2) */ 446 /* RL & nRTP for DBI-RD Disabled */ 447 #define LPDDR4_RL6_NRTP8 (0x0) 448 #define LPDDR4_RL10_NRTP8 (0x1) 449 #define LPDDR4_RL14_NRTP8 (0x2) 450 #define LPDDR4_RL20_NRTP8 (0x3) 451 #define LPDDR4_RL24_NRTP10 (0x4) 452 #define LPDDR4_RL28_NRTP12 (0x5) 453 #define LPDDR4_RL32_NRTP14 (0x6) 454 #define LPDDR4_RL36_NRTP16 (0x7) 455 /* RL & nRTP for DBI-RD Disabled */ 456 #define LPDDR4_RL12_NRTP8 (0x1) 457 #define LPDDR4_RL16_NRTP8 (0x2) 458 #define LPDDR4_RL22_NRTP8 (0x3) 459 #define LPDDR4_RL28_NRTP10 (0x4) 460 #define LPDDR4_RL32_NRTP12 (0x5) 461 #define LPDDR4_RL36_NRTP14 (0x6) 462 #define LPDDR4_RL40_NRTP16 (0x7) 463 /* WL Set A,default */ 464 #define LPDDR4_A_WL4 (0x0) 465 #define LPDDR4_A_WL6 (0x1) 466 #define LPDDR4_A_WL8 (0x2) 467 #define LPDDR4_A_WL10 (0x3) 468 #define LPDDR4_A_WL12 (0x4) 469 #define LPDDR4_A_WL14 (0x5) 470 #define LPDDR4_A_WL16 (0x6) 471 #define LPDDR4_A_WL18 (0x7) 472 /* WL Set B, optional */ 473 #define LPDDR4_B_WL4 (0x0 << 3) 474 #define LPDDR4_B_WL8 (0x1 << 3) 475 #define LPDDR4_B_WL12 (0x2 << 3) 476 #define LPDDR4_B_WL18 (0x3 << 3) 477 #define LPDDR4_B_WL22 (0x4 << 3) 478 #define LPDDR4_B_WL26 (0x5 << 3) 479 #define LPDDR4_B_WL30 (0x6 << 3) 480 #define LPDDR4_B_WL34 (0x7 << 3) 481 /* 1:Select WL Set B*/ 482 #define LPDDR4_WL_B (1 << 6) 483 /* 1:enable*/ 484 #define LPDDR4_WR_LEVEL (1 << 7) 485 486 /* MR3 */ 487 #define LPDDR4_VDDQ_2_5 (0) 488 #define LPDDR4_VDDQ_3 (1) 489 #define LPDDR4_WRPST_0_5_TCK (0 << 1) 490 #define LPDDR4_WRPST_1_5_TCK (1 << 1) 491 #define LPDDR4_PPR_EN (1 << 2) 492 /* PDDS */ 493 #define LPDDR4_PDDS_240 (0x1 << 3) 494 #define LPDDR4_PDDS_120 (0x2 << 3) 495 #define LPDDR4_PDDS_80 (0x3 << 3) 496 #define LPDDR4_PDDS_60 (0x4 << 3) 497 #define LPDDR4_PDDS_48 (0x5 << 3) 498 #define LPDDR4_PDDS_40 (0x6 << 3) 499 #define LPDDR4_DBI_RD_EN (1 << 6) 500 #define LPDDR4_DBI_WR_EN (1 << 7) 501 502 /* MR11 (ODT Control) */ 503 #define LPDDR4_DQODT_240 (1) 504 #define LPDDR4_DQODT_120 (2) 505 #define LPDDR4_DQODT_80 (3) 506 #define LPDDR4_DQODT_60 (4) 507 #define LPDDR4_DQODT_48 (5) 508 #define LPDDR4_DQODT_40 (6) 509 #define LPDDR4_DQODT_DIS (0) 510 #define LPDDR4_CAODT_240 (1 << 4) 511 #define LPDDR4_CAODT_120 (2 << 4) 512 #define LPDDR4_CAODT_80 (3 << 4) 513 #define LPDDR4_CAODT_60 (4 << 4) 514 #define LPDDR4_CAODT_48 (5 << 4) 515 #define LPDDR4_CAODT_40 (6 << 4) 516 #define LPDDR4_CAODT_DIS (0 << 4) 517 518 /* 519 * Description: depend on input parameter "timing_config", 520 * and calculate correspond "dram_type" 521 * spec timing to "pdram_timing" 522 * parameters: 523 * input: timing_config 524 * output: pdram_timing 525 * NOTE: MR ODT is set, need to disable by controller 526 */ 527 void dram_get_parameter(struct timing_related_config *timing_config, 528 struct dram_timing_t *pdram_timing); 529 530 #endif /* _DRAM_SPEC_TIMING_HEAD_ */ 531