1 /* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <string.h> 32 #include <stdint.h> 33 #include <dram.h> 34 #include <utils.h> 35 #include "dram_spec_timing.h" 36 37 static const uint8_t ddr3_cl_cwl[][7] = { 38 /* 39 * speed 0~330 331 ~ 400 401 ~ 533 534~666 667~800 801~933 934~1066 40 * tCK>3 2.5~3 1.875~2.5 1.5~1.875 1.25~1.5 1.07~1.25 0.938~1.07 41 * cl<<4, cwl cl<<4, cwl cl<<4, cwl 42 */ 43 /* DDR3_800D (5-5-5) */ 44 {((5 << 4) | 5), ((5 << 4) | 5), 0, 0, 0, 0, 0}, 45 /* DDR3_800E (6-6-6) */ 46 {((5 << 4) | 5), ((6 << 4) | 5), 0, 0, 0, 0, 0}, 47 /* DDR3_1066E (6-6-6) */ 48 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), 0, 0, 0, 0}, 49 /* DDR3_1066F (7-7-7) */ 50 {((5 << 4) | 5), ((6 << 4) | 5), ((7 << 4) | 6), 0, 0, 0, 0}, 51 /* DDR3_1066G (8-8-8) */ 52 {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), 0, 0, 0, 0}, 53 /* DDR3_1333F (7-7-7) */ 54 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((7 << 4) | 7), 55 0, 0, 0}, 56 /* DDR3_1333G (8-8-8) */ 57 {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((8 << 4) | 7), 58 0, 0, 0}, 59 /* DDR3_1333H (9-9-9) */ 60 {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((9 << 4) | 7), 61 0, 0, 0}, 62 /* DDR3_1333J (10-10-10) */ 63 {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7), 64 0, 0, 0}, 65 /* DDR3_1600G (8-8-8) */ 66 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((7 << 4) | 7), 67 ((8 << 4) | 8), 0, 0}, 68 /* DDR3_1600H (9-9-9) */ 69 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((8 << 4) | 7), 70 ((9 << 4) | 8), 0, 0}, 71 /* DDR3_1600J (10-10-10) */ 72 {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7), 73 ((10 << 4) | 8), 0, 0}, 74 /* DDR3_1600K (11-11-11) */ 75 {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7), 76 ((11 << 4) | 8), 0, 0}, 77 /* DDR3_1866J (10-10-10) */ 78 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((8 << 4) | 7), 79 ((9 << 4) | 8), ((11 << 4) | 9), 0}, 80 /* DDR3_1866K (11-11-11) */ 81 {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((8 << 4) | 7), 82 ((10 << 4) | 8), ((11 << 4) | 9), 0}, 83 /* DDR3_1866L (12-12-12) */ 84 {((6 << 4) | 5), ((6 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7), 85 ((11 << 4) | 8), ((12 << 4) | 9), 0}, 86 /* DDR3_1866M (13-13-13) */ 87 {((6 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7), 88 ((11 << 4) | 8), ((13 << 4) | 9), 0}, 89 /* DDR3_2133K (11-11-11) */ 90 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((7 << 4) | 7), 91 ((9 << 4) | 8), ((10 << 4) | 9), ((11 << 4) | 10)}, 92 /* DDR3_2133L (12-12-12) */ 93 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((8 << 4) | 7), 94 ((9 << 4) | 8), ((11 << 4) | 9), ((12 << 4) | 10)}, 95 /* DDR3_2133M (13-13-13) */ 96 {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7), 97 ((10 << 4) | 8), ((12 << 4) | 9), ((13 << 4) | 10)}, 98 /* DDR3_2133N (14-14-14) */ 99 {((6 << 4) | 5), ((6 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7), 100 ((11 << 4) | 8), ((13 << 4) | 9), ((14 << 4) | 10)}, 101 /* DDR3_DEFAULT */ 102 {((6 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7), 103 ((11 << 4) | 8), ((13 << 4) | 9), ((14 << 4) | 10)} 104 }; 105 106 static const uint16_t ddr3_trc_tfaw[] = { 107 /* tRC tFAW */ 108 ((50 << 8) | 50), /* DDR3_800D (5-5-5) */ 109 ((53 << 8) | 50), /* DDR3_800E (6-6-6) */ 110 111 ((49 << 8) | 50), /* DDR3_1066E (6-6-6) */ 112 ((51 << 8) | 50), /* DDR3_1066F (7-7-7) */ 113 ((53 << 8) | 50), /* DDR3_1066G (8-8-8) */ 114 115 ((47 << 8) | 45), /* DDR3_1333F (7-7-7) */ 116 ((48 << 8) | 45), /* DDR3_1333G (8-8-8) */ 117 ((50 << 8) | 45), /* DDR3_1333H (9-9-9) */ 118 ((51 << 8) | 45), /* DDR3_1333J (10-10-10) */ 119 120 ((45 << 8) | 40), /* DDR3_1600G (8-8-8) */ 121 ((47 << 8) | 40), /* DDR3_1600H (9-9-9)*/ 122 ((48 << 8) | 40), /* DDR3_1600J (10-10-10) */ 123 ((49 << 8) | 40), /* DDR3_1600K (11-11-11) */ 124 125 ((45 << 8) | 35), /* DDR3_1866J (10-10-10) */ 126 ((46 << 8) | 35), /* DDR3_1866K (11-11-11) */ 127 ((47 << 8) | 35), /* DDR3_1866L (12-12-12) */ 128 ((48 << 8) | 35), /* DDR3_1866M (13-13-13) */ 129 130 ((44 << 8) | 35), /* DDR3_2133K (11-11-11) */ 131 ((45 << 8) | 35), /* DDR3_2133L (12-12-12) */ 132 ((46 << 8) | 35), /* DDR3_2133M (13-13-13) */ 133 ((47 << 8) | 35), /* DDR3_2133N (14-14-14) */ 134 135 ((53 << 8) | 50) /* DDR3_DEFAULT */ 136 }; 137 138 static uint32_t get_max_speed_rate(struct timing_related_config *timing_config) 139 { 140 if (timing_config->ch_cnt > 1) 141 return max(timing_config->dram_info[0].speed_rate, 142 timing_config->dram_info[1].speed_rate); 143 else 144 return timing_config->dram_info[0].speed_rate; 145 } 146 147 static uint32_t 148 get_max_die_capability(struct timing_related_config *timing_config) 149 { 150 uint32_t die_cap = 0; 151 uint32_t cs, ch; 152 153 for (ch = 0; ch < timing_config->ch_cnt; ch++) { 154 for (cs = 0; cs < timing_config->dram_info[ch].cs_cnt; cs++) { 155 die_cap = max(die_cap, 156 timing_config-> 157 dram_info[ch].per_die_capability[cs]); 158 } 159 } 160 return die_cap; 161 } 162 163 /* tRSTL, 100ns */ 164 #define DDR3_TRSTL (100) 165 /* trsth, 500us */ 166 #define DDR3_TRSTH (500000) 167 /* trefi, 7.8us */ 168 #define DDR3_TREFI_7_8_US (7800) 169 /* tWR, 15ns */ 170 #define DDR3_TWR (15) 171 /* tRTP, max(4 tCK,7.5ns) */ 172 #define DDR3_TRTP (7) 173 /* tRRD = max(4nCK, 10ns) */ 174 #define DDR3_TRRD (10) 175 /* tCK */ 176 #define DDR3_TCCD (4) 177 /*tWTR, max(4 tCK,7.5ns)*/ 178 #define DDR3_TWTR (7) 179 /* tCK */ 180 #define DDR3_TRTW (0) 181 /* tRAS, 37.5ns(400MHz) 37.5ns(533MHz) */ 182 #define DDR3_TRAS (37) 183 /* ns */ 184 #define DDR3_TRFC_512MBIT (90) 185 /* ns */ 186 #define DDR3_TRFC_1GBIT (110) 187 /* ns */ 188 #define DDR3_TRFC_2GBIT (160) 189 /* ns */ 190 #define DDR3_TRFC_4GBIT (300) 191 /* ns */ 192 #define DDR3_TRFC_8GBIT (350) 193 194 /*pd and sr*/ 195 #define DDR3_TXP (7) /* tXP, max(3 tCK, 7.5ns)( < 933MHz) */ 196 #define DDR3_TXPDLL (24) /* tXPDLL, max(10 tCK, 24ns) */ 197 #define DDR3_TDLLK (512) /* tXSR, tDLLK=512 tCK */ 198 #define DDR3_TCKE_400MHZ (7) /* tCKE, max(3 tCK,7.5ns)(400MHz) */ 199 #define DDR3_TCKE_533MHZ (6) /* tCKE, max(3 tCK,5.625ns)(533MHz) */ 200 #define DDR3_TCKSRE (10) /* tCKSRX, max(5 tCK, 10ns) */ 201 202 /*mode register timing*/ 203 #define DDR3_TMOD (15) /* tMOD, max(12 tCK,15ns) */ 204 #define DDR3_TMRD (4) /* tMRD, 4 tCK */ 205 206 /* ZQ */ 207 #define DDR3_TZQINIT (640) /* tZQinit, max(512 tCK, 640ns) */ 208 #define DDR3_TZQCS (80) /* tZQCS, max(64 tCK, 80ns) */ 209 #define DDR3_TZQOPER (320) /* tZQoper, max(256 tCK, 320ns) */ 210 211 /* Write leveling */ 212 #define DDR3_TWLMRD (40) /* tCK */ 213 #define DDR3_TWLO (9) /* max 7.5ns */ 214 #define DDR3_TWLDQSEN (25) /* tCK */ 215 216 /* 217 * Description: depend on input parameter "timing_config", 218 * and calculate all ddr3 219 * spec timing to "pdram_timing" 220 * parameters: 221 * input: timing_config 222 * output: pdram_timing 223 */ 224 static void ddr3_get_parameter(struct timing_related_config *timing_config, 225 struct dram_timing_t *pdram_timing) 226 { 227 uint32_t nmhz = timing_config->freq; 228 uint32_t ddr_speed_bin = get_max_speed_rate(timing_config); 229 uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); 230 uint32_t tmp; 231 232 zeromem((void *)pdram_timing, sizeof(struct dram_timing_t)); 233 pdram_timing->mhz = nmhz; 234 pdram_timing->al = 0; 235 pdram_timing->bl = timing_config->bl; 236 if (nmhz <= 330) 237 tmp = 0; 238 else if (nmhz <= 400) 239 tmp = 1; 240 else if (nmhz <= 533) 241 tmp = 2; 242 else if (nmhz <= 666) 243 tmp = 3; 244 else if (nmhz <= 800) 245 tmp = 4; 246 else if (nmhz <= 933) 247 tmp = 5; 248 else 249 tmp = 6; 250 251 /* when dll bypss cl = cwl = 6 */ 252 if (nmhz < 300) { 253 pdram_timing->cl = 6; 254 pdram_timing->cwl = 6; 255 } else { 256 pdram_timing->cl = (ddr3_cl_cwl[ddr_speed_bin][tmp] >> 4) & 0xf; 257 pdram_timing->cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0xf; 258 } 259 260 switch (timing_config->dramds) { 261 case 40: 262 tmp = DDR3_DS_40; 263 break; 264 case 34: 265 default: 266 tmp = DDR3_DS_34; 267 break; 268 } 269 270 if (timing_config->odt) 271 switch (timing_config->dramodt) { 272 case 60: 273 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_60; 274 break; 275 case 40: 276 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_40; 277 break; 278 case 120: 279 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_120; 280 break; 281 case 0: 282 default: 283 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_DIS; 284 break; 285 } 286 else 287 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_DIS; 288 289 pdram_timing->mr[2] = DDR3_MR2_CWL(pdram_timing->cwl); 290 pdram_timing->mr[3] = 0; 291 292 pdram_timing->trstl = ((DDR3_TRSTL * nmhz + 999) / 1000); 293 pdram_timing->trsth = ((DDR3_TRSTH * nmhz + 999) / 1000); 294 /* tREFI, average periodic refresh interval, 7.8us */ 295 pdram_timing->trefi = ((DDR3_TREFI_7_8_US * nmhz + 999) / 1000); 296 /* base timing */ 297 pdram_timing->trcd = pdram_timing->cl; 298 pdram_timing->trp = pdram_timing->cl; 299 pdram_timing->trppb = pdram_timing->cl; 300 tmp = ((DDR3_TWR * nmhz + 999) / 1000); 301 pdram_timing->twr = tmp; 302 pdram_timing->tdal = tmp + pdram_timing->trp; 303 if (tmp < 9) { 304 tmp = tmp - 4; 305 } else { 306 tmp += (tmp & 0x1) ? 1 : 0; 307 tmp = tmp >> 1; 308 } 309 if (pdram_timing->bl == 4) 310 pdram_timing->mr[0] = DDR3_BC4 311 | DDR3_CL(pdram_timing->cl) 312 | DDR3_WR(tmp); 313 else 314 pdram_timing->mr[0] = DDR3_BL8 315 | DDR3_CL(pdram_timing->cl) 316 | DDR3_WR(tmp); 317 tmp = ((DDR3_TRTP * nmhz + (nmhz >> 1) + 999) / 1000); 318 pdram_timing->trtp = max(4, tmp); 319 pdram_timing->trc = 320 (((ddr3_trc_tfaw[ddr_speed_bin] >> 8) * nmhz + 999) / 1000); 321 tmp = ((DDR3_TRRD * nmhz + 999) / 1000); 322 pdram_timing->trrd = max(4, tmp); 323 pdram_timing->tccd = DDR3_TCCD; 324 tmp = ((DDR3_TWTR * nmhz + (nmhz >> 1) + 999) / 1000); 325 pdram_timing->twtr = max(4, tmp); 326 pdram_timing->trtw = DDR3_TRTW; 327 pdram_timing->tras_max = 9 * pdram_timing->trefi; 328 pdram_timing->tras_min = ((DDR3_TRAS * nmhz + (nmhz >> 1) + 999) 329 / 1000); 330 pdram_timing->tfaw = 331 (((ddr3_trc_tfaw[ddr_speed_bin] & 0x0ff) * nmhz + 999) 332 / 1000); 333 /* tRFC, 90ns(512Mb),110ns(1Gb),160ns(2Gb),300ns(4Gb),350ns(8Gb) */ 334 if (ddr_capability_per_die <= 0x4000000) 335 tmp = DDR3_TRFC_512MBIT; 336 else if (ddr_capability_per_die <= 0x8000000) 337 tmp = DDR3_TRFC_1GBIT; 338 else if (ddr_capability_per_die <= 0x10000000) 339 tmp = DDR3_TRFC_2GBIT; 340 else if (ddr_capability_per_die <= 0x20000000) 341 tmp = DDR3_TRFC_4GBIT; 342 else 343 tmp = DDR3_TRFC_8GBIT; 344 pdram_timing->trfc = (tmp * nmhz + 999) / 1000; 345 pdram_timing->txsnr = max(5, (((tmp + 10) * nmhz + 999) / 1000)); 346 pdram_timing->tdqsck_max = 0; 347 /*pd and sr*/ 348 pdram_timing->txsr = DDR3_TDLLK; 349 tmp = ((DDR3_TXP * nmhz + (nmhz >> 1) + 999) / 1000); 350 pdram_timing->txp = max(3, tmp); 351 tmp = ((DDR3_TXPDLL * nmhz + 999) / 1000); 352 pdram_timing->txpdll = max(10, tmp); 353 pdram_timing->tdllk = DDR3_TDLLK; 354 if (nmhz >= 533) 355 tmp = ((DDR3_TCKE_533MHZ * nmhz + 999) / 1000); 356 else 357 tmp = ((DDR3_TCKE_400MHZ * nmhz + (nmhz >> 1) + 999) / 1000); 358 pdram_timing->tcke = max(3, tmp); 359 pdram_timing->tckesr = (pdram_timing->tcke + 1); 360 tmp = ((DDR3_TCKSRE * nmhz + 999) / 1000); 361 pdram_timing->tcksre = max(5, tmp); 362 pdram_timing->tcksrx = max(5, tmp); 363 /*mode register timing*/ 364 tmp = ((DDR3_TMOD * nmhz + 999) / 1000); 365 pdram_timing->tmod = max(12, tmp); 366 pdram_timing->tmrd = DDR3_TMRD; 367 pdram_timing->tmrr = 0; 368 /*ODT*/ 369 pdram_timing->todton = pdram_timing->cwl - 2; 370 /*ZQ*/ 371 tmp = ((DDR3_TZQINIT * nmhz + 999) / 1000); 372 pdram_timing->tzqinit = max(512, tmp); 373 tmp = ((DDR3_TZQCS * nmhz + 999) / 1000); 374 pdram_timing->tzqcs = max(64, tmp); 375 tmp = ((DDR3_TZQOPER * nmhz + 999) / 1000); 376 pdram_timing->tzqoper = max(256, tmp); 377 /* write leveling */ 378 pdram_timing->twlmrd = DDR3_TWLMRD; 379 pdram_timing->twldqsen = DDR3_TWLDQSEN; 380 pdram_timing->twlo = ((DDR3_TWLO * nmhz + (nmhz >> 1) + 999) / 1000); 381 } 382 383 #define LPDDR2_TINIT1 (100) /* ns */ 384 #define LPDDR2_TINIT2 (5) /* tCK */ 385 #define LPDDR2_TINIT3 (200000) /* 200us */ 386 #define LPDDR2_TINIT4 (1000) /* 1us */ 387 #define LPDDR2_TINIT5 (10000) /* 10us */ 388 #define LPDDR2_TRSTL (0) /* tCK */ 389 #define LPDDR2_TRSTH (500000) /* 500us */ 390 #define LPDDR2_TREFI_3_9_US (3900) /* 3.9us */ 391 #define LPDDR2_TREFI_7_8_US (7800) /* 7.8us */ 392 393 /* base timing */ 394 #define LPDDR2_TRCD (24) /* tRCD,15ns(Fast)18ns(Typ)24ns(Slow) */ 395 #define LPDDR2_TRP_PB (18) /* tRPpb,15ns(Fast)18ns(Typ)24ns(Slow) */ 396 #define LPDDR2_TRP_AB_8_BANK (21) /* tRPab,18ns(Fast)21ns(Typ)27ns(Slow) */ 397 #define LPDDR2_TWR (15) /* tWR, max(3tCK,15ns) */ 398 #define LPDDR2_TRTP (7) /* tRTP, max(2tCK, 7.5ns) */ 399 #define LPDDR2_TRRD (10) /* tRRD, max(2tCK,10ns) */ 400 #define LPDDR2_TCCD (2) /* tCK */ 401 #define LPDDR2_TWTR_GREAT_200MHZ (7) /* ns */ 402 #define LPDDR2_TWTR_LITTLE_200MHZ (10) /* ns */ 403 #define LPDDR2_TRTW (0) /* tCK */ 404 #define LPDDR2_TRAS_MAX (70000) /* 70us */ 405 #define LPDDR2_TRAS (42) /* tRAS, max(3tCK,42ns) */ 406 #define LPDDR2_TFAW_GREAT_200MHZ (50) /* max(8tCK,50ns) */ 407 #define LPDDR2_TFAW_LITTLE_200MHZ (60) /* max(8tCK,60ns) */ 408 #define LPDDR2_TRFC_8GBIT (210) /* ns */ 409 #define LPDDR2_TRFC_4GBIT (130) /* ns */ 410 #define LPDDR2_TDQSCK_MIN (2) /* tDQSCKmin, 2.5ns */ 411 #define LPDDR2_TDQSCK_MAX (5) /* tDQSCKmax, 5.5ns */ 412 413 /*pd and sr*/ 414 #define LPDDR2_TXP (7) /* tXP, max(2tCK,7.5ns) */ 415 #define LPDDR2_TXPDLL (0) 416 #define LPDDR2_TDLLK (0) /* tCK */ 417 #define LPDDR2_TCKE (3) /* tCK */ 418 #define LPDDR2_TCKESR (15) /* tCKESR, max(3tCK,15ns) */ 419 #define LPDDR2_TCKSRE (1) /* tCK */ 420 #define LPDDR2_TCKSRX (2) /* tCK */ 421 422 /*mode register timing*/ 423 #define LPDDR2_TMOD (0) 424 #define LPDDR2_TMRD (5) /* tMRD, (=tMRW), 5 tCK */ 425 #define LPDDR2_TMRR (2) /* tCK */ 426 427 /*ZQ*/ 428 #define LPDDR2_TZQINIT (1000) /* ns */ 429 #define LPDDR2_TZQCS (90) /* tZQCS, max(6tCK,90ns) */ 430 #define LPDDR2_TZQCL (360) /* tZQCL, max(6tCK,360ns) */ 431 #define LPDDR2_TZQRESET (50) /* ZQreset, max(3tCK,50ns) */ 432 433 /* 434 * Description: depend on input parameter "timing_config", 435 * and calculate all lpddr2 436 * spec timing to "pdram_timing" 437 * parameters: 438 * input: timing_config 439 * output: pdram_timing 440 */ 441 static void lpddr2_get_parameter(struct timing_related_config *timing_config, 442 struct dram_timing_t *pdram_timing) 443 { 444 uint32_t nmhz = timing_config->freq; 445 uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); 446 uint32_t tmp, trp_tmp, trppb_tmp, tras_tmp, twr_tmp, bl_tmp; 447 448 zeromem((void *)pdram_timing, sizeof(struct dram_timing_t)); 449 pdram_timing->mhz = nmhz; 450 pdram_timing->al = 0; 451 pdram_timing->bl = timing_config->bl; 452 453 /* 1066 933 800 667 533 400 333 454 * RL, 8 7 6 5 4 3 3 455 * WL, 4 4 3 2 2 1 1 456 */ 457 if (nmhz <= 266) { 458 pdram_timing->cl = 4; 459 pdram_timing->cwl = 2; 460 pdram_timing->mr[2] = LPDDR2_RL4_WL2; 461 } else if (nmhz <= 333) { 462 pdram_timing->cl = 5; 463 pdram_timing->cwl = 2; 464 pdram_timing->mr[2] = LPDDR2_RL5_WL2; 465 } else if (nmhz <= 400) { 466 pdram_timing->cl = 6; 467 pdram_timing->cwl = 3; 468 pdram_timing->mr[2] = LPDDR2_RL6_WL3; 469 } else if (nmhz <= 466) { 470 pdram_timing->cl = 7; 471 pdram_timing->cwl = 4; 472 pdram_timing->mr[2] = LPDDR2_RL7_WL4; 473 } else { 474 pdram_timing->cl = 8; 475 pdram_timing->cwl = 4; 476 pdram_timing->mr[2] = LPDDR2_RL8_WL4; 477 } 478 switch (timing_config->dramds) { 479 case 120: 480 pdram_timing->mr[3] = LPDDR2_DS_120; 481 break; 482 case 80: 483 pdram_timing->mr[3] = LPDDR2_DS_80; 484 break; 485 case 60: 486 pdram_timing->mr[3] = LPDDR2_DS_60; 487 break; 488 case 48: 489 pdram_timing->mr[3] = LPDDR2_DS_48; 490 break; 491 case 40: 492 pdram_timing->mr[3] = LPDDR2_DS_40; 493 break; 494 case 34: 495 default: 496 pdram_timing->mr[3] = LPDDR2_DS_34; 497 break; 498 } 499 pdram_timing->mr[0] = 0; 500 501 pdram_timing->tinit1 = (LPDDR2_TINIT1 * nmhz + 999) / 1000; 502 pdram_timing->tinit2 = LPDDR2_TINIT2; 503 pdram_timing->tinit3 = (LPDDR2_TINIT3 * nmhz + 999) / 1000; 504 pdram_timing->tinit4 = (LPDDR2_TINIT4 * nmhz + 999) / 1000; 505 pdram_timing->tinit5 = (LPDDR2_TINIT5 * nmhz + 999) / 1000; 506 pdram_timing->trstl = LPDDR2_TRSTL; 507 pdram_timing->trsth = (LPDDR2_TRSTH * nmhz + 999) / 1000; 508 /* 509 * tREFI, average periodic refresh interval, 510 * 15.6us(<256Mb) 7.8us(256Mb-1Gb) 3.9us(2Gb-8Gb) 511 */ 512 if (ddr_capability_per_die >= 0x10000000) 513 pdram_timing->trefi = (LPDDR2_TREFI_3_9_US * nmhz + 999) 514 / 1000; 515 else 516 pdram_timing->trefi = (LPDDR2_TREFI_7_8_US * nmhz + 999) 517 / 1000; 518 /* base timing */ 519 tmp = ((LPDDR2_TRCD * nmhz + 999) / 1000); 520 pdram_timing->trcd = max(3, tmp); 521 /* 522 * tRPpb, max(3tCK, 15ns(Fast) 18ns(Typ) 24ns(Slow), 523 */ 524 trppb_tmp = ((LPDDR2_TRP_PB * nmhz + 999) / 1000); 525 trppb_tmp = max(3, trppb_tmp); 526 pdram_timing->trppb = trppb_tmp; 527 /* 528 * tRPab, max(3tCK, 4-bank:15ns(Fast) 18ns(Typ) 24ns(Slow), 529 * 8-bank:18ns(Fast) 21ns(Typ) 27ns(Slow)) 530 */ 531 trp_tmp = ((LPDDR2_TRP_AB_8_BANK * nmhz + 999) / 1000); 532 trp_tmp = max(3, trp_tmp); 533 pdram_timing->trp = trp_tmp; 534 twr_tmp = ((LPDDR2_TWR * nmhz + 999) / 1000); 535 twr_tmp = max(3, twr_tmp); 536 pdram_timing->twr = twr_tmp; 537 bl_tmp = (pdram_timing->bl == 16) ? LPDDR2_BL16 : 538 ((pdram_timing->bl == 8) ? LPDDR2_BL8 : LPDDR2_BL4); 539 pdram_timing->mr[1] = bl_tmp | LPDDR2_N_WR(twr_tmp); 540 tmp = ((LPDDR2_TRTP * nmhz + (nmhz >> 1) + 999) / 1000); 541 pdram_timing->trtp = max(2, tmp); 542 tras_tmp = ((LPDDR2_TRAS * nmhz + 999) / 1000); 543 tras_tmp = max(3, tras_tmp); 544 pdram_timing->tras_min = tras_tmp; 545 pdram_timing->tras_max = ((LPDDR2_TRAS_MAX * nmhz + 999) / 1000); 546 pdram_timing->trc = (tras_tmp + trp_tmp); 547 tmp = ((LPDDR2_TRRD * nmhz + 999) / 1000); 548 pdram_timing->trrd = max(2, tmp); 549 pdram_timing->tccd = LPDDR2_TCCD; 550 /* tWTR, max(2tCK, 7.5ns(533-266MHz) 10ns(200-166MHz)) */ 551 if (nmhz > 200) 552 tmp = ((LPDDR2_TWTR_GREAT_200MHZ * nmhz + (nmhz >> 1) + 553 999) / 1000); 554 else 555 tmp = ((LPDDR2_TWTR_LITTLE_200MHZ * nmhz + 999) / 1000); 556 pdram_timing->twtr = max(2, tmp); 557 pdram_timing->trtw = LPDDR2_TRTW; 558 if (nmhz <= 200) 559 pdram_timing->tfaw = (LPDDR2_TFAW_LITTLE_200MHZ * nmhz + 999) 560 / 1000; 561 else 562 pdram_timing->tfaw = (LPDDR2_TFAW_GREAT_200MHZ * nmhz + 999) 563 / 1000; 564 /* tRFC, 90ns(<=512Mb) 130ns(1Gb-4Gb) 210ns(8Gb) */ 565 if (ddr_capability_per_die >= 0x40000000) { 566 pdram_timing->trfc = 567 (LPDDR2_TRFC_8GBIT * nmhz + 999) / 1000; 568 tmp = (((LPDDR2_TRFC_8GBIT + 10) * nmhz + 999) / 1000); 569 } else { 570 pdram_timing->trfc = 571 (LPDDR2_TRFC_4GBIT * nmhz + 999) / 1000; 572 tmp = (((LPDDR2_TRFC_4GBIT + 10) * nmhz + 999) / 1000); 573 } 574 if (tmp < 2) 575 tmp = 2; 576 pdram_timing->txsr = tmp; 577 pdram_timing->txsnr = tmp; 578 /* tdqsck use rounded down */ 579 pdram_timing->tdqsck = ((LPDDR2_TDQSCK_MIN * nmhz + (nmhz >> 1)) 580 / 1000); 581 pdram_timing->tdqsck_max = 582 ((LPDDR2_TDQSCK_MAX * nmhz + (nmhz >> 1) + 999) 583 / 1000); 584 /* pd and sr */ 585 tmp = ((LPDDR2_TXP * nmhz + (nmhz >> 1) + 999) / 1000); 586 pdram_timing->txp = max(2, tmp); 587 pdram_timing->txpdll = LPDDR2_TXPDLL; 588 pdram_timing->tdllk = LPDDR2_TDLLK; 589 pdram_timing->tcke = LPDDR2_TCKE; 590 tmp = ((LPDDR2_TCKESR * nmhz + 999) / 1000); 591 pdram_timing->tckesr = max(3, tmp); 592 pdram_timing->tcksre = LPDDR2_TCKSRE; 593 pdram_timing->tcksrx = LPDDR2_TCKSRX; 594 /* mode register timing */ 595 pdram_timing->tmod = LPDDR2_TMOD; 596 pdram_timing->tmrd = LPDDR2_TMRD; 597 pdram_timing->tmrr = LPDDR2_TMRR; 598 /* ZQ */ 599 pdram_timing->tzqinit = (LPDDR2_TZQINIT * nmhz + 999) / 1000; 600 tmp = ((LPDDR2_TZQCS * nmhz + 999) / 1000); 601 pdram_timing->tzqcs = max(6, tmp); 602 tmp = ((LPDDR2_TZQCL * nmhz + 999) / 1000); 603 pdram_timing->tzqoper = max(6, tmp); 604 tmp = ((LPDDR2_TZQRESET * nmhz + 999) / 1000); 605 pdram_timing->tzqreset = max(3, tmp); 606 } 607 608 #define LPDDR3_TINIT1 (100) /* ns */ 609 #define LPDDR3_TINIT2 (5) /* tCK */ 610 #define LPDDR3_TINIT3 (200000) /* 200us */ 611 #define LPDDR3_TINIT4 (1000) /* 1us */ 612 #define LPDDR3_TINIT5 (10000) /* 10us */ 613 #define LPDDR3_TRSTL (0) 614 #define LPDDR3_TRSTH (0) /* 500us */ 615 #define LPDDR3_TREFI_3_9_US (3900) /* 3.9us */ 616 617 /* base timging */ 618 #define LPDDR3_TRCD (18) /* tRCD,15ns(Fast)18ns(Typ)24ns(Slow) */ 619 #define LPDDR3_TRP_PB (18) /* tRPpb, 15ns(Fast) 18ns(Typ) 24ns(Slow) */ 620 #define LPDDR3_TRP_AB (21) /* tRPab, 18ns(Fast) 21ns(Typ) 27ns(Slow) */ 621 #define LPDDR3_TWR (15) /* tWR, max(4tCK,15ns) */ 622 #define LPDDR3_TRTP (7) /* tRTP, max(4tCK, 7.5ns) */ 623 #define LPDDR3_TRRD (10) /* tRRD, max(2tCK,10ns) */ 624 #define LPDDR3_TCCD (4) /* tCK */ 625 #define LPDDR3_TWTR (7) /* tWTR, max(4tCK, 7.5ns) */ 626 #define LPDDR3_TRTW (0) /* tCK register min valid value */ 627 #define LPDDR3_TRAS_MAX (70000) /* 70us */ 628 #define LPDDR3_TRAS (42) /* tRAS, max(3tCK,42ns) */ 629 #define LPDDR3_TFAW (50) /* tFAW,max(8tCK, 50ns) */ 630 #define LPDDR3_TRFC_8GBIT (210) /* tRFC, 130ns(4Gb) 210ns(>4Gb) */ 631 #define LPDDR3_TRFC_4GBIT (130) /* ns */ 632 #define LPDDR3_TDQSCK_MIN (2) /* tDQSCKmin,2.5ns */ 633 #define LPDDR3_TDQSCK_MAX (5) /* tDQSCKmax,5.5ns */ 634 635 /* pd and sr */ 636 #define LPDDR3_TXP (7) /* tXP, max(3tCK,7.5ns) */ 637 #define LPDDR3_TXPDLL (0) 638 #define LPDDR3_TCKE (7) /* tCKE, (max 7.5ns,3 tCK) */ 639 #define LPDDR3_TCKESR (15) /* tCKESR, max(3tCK,15ns) */ 640 #define LPDDR3_TCKSRE (2) /* tCKSRE=tCPDED, 2 tCK */ 641 #define LPDDR3_TCKSRX (2) /* tCKSRX, 2 tCK */ 642 643 /* mode register timing */ 644 #define LPDDR3_TMOD (0) 645 #define LPDDR3_TMRD (14) /* tMRD, (=tMRW), max(14ns, 10 tCK) */ 646 #define LPDDR3_TMRR (4) /* tMRR, 4 tCK */ 647 #define LPDDR3_TMRRI LPDDR3_TRCD 648 649 /* ODT */ 650 #define LPDDR3_TODTON (3) /* 3.5ns */ 651 652 /* ZQ */ 653 #define LPDDR3_TZQINIT (1000) /* 1us */ 654 #define LPDDR3_TZQCS (90) /* tZQCS, 90ns */ 655 #define LPDDR3_TZQCL (360) /* 360ns */ 656 #define LPDDR3_TZQRESET (50) /* ZQreset, max(3tCK,50ns) */ 657 /* write leveling */ 658 #define LPDDR3_TWLMRD (40) /* ns */ 659 #define LPDDR3_TWLO (20) /* ns */ 660 #define LPDDR3_TWLDQSEN (25) /* ns */ 661 /* CA training */ 662 #define LPDDR3_TCACKEL (10) /* tCK */ 663 #define LPDDR3_TCAENT (10) /* tCK */ 664 #define LPDDR3_TCAMRD (20) /* tCK */ 665 #define LPDDR3_TCACKEH (10) /* tCK */ 666 #define LPDDR3_TCAEXT (10) /* tCK */ 667 #define LPDDR3_TADR (20) /* ns */ 668 #define LPDDR3_TMRZ (3) /* ns */ 669 670 /* FSP */ 671 #define LPDDR3_TFC_LONG (250) /* ns */ 672 673 /* 674 * Description: depend on input parameter "timing_config", 675 * and calculate all lpddr3 676 * spec timing to "pdram_timing" 677 * parameters: 678 * input: timing_config 679 * output: pdram_timing 680 */ 681 static void lpddr3_get_parameter(struct timing_related_config *timing_config, 682 struct dram_timing_t *pdram_timing) 683 { 684 uint32_t nmhz = timing_config->freq; 685 uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); 686 uint32_t tmp, trp_tmp, trppb_tmp, tras_tmp, twr_tmp, bl_tmp; 687 688 zeromem((void *)pdram_timing, sizeof(struct dram_timing_t)); 689 pdram_timing->mhz = nmhz; 690 pdram_timing->al = 0; 691 pdram_timing->bl = timing_config->bl; 692 693 /* 694 * Only support Write Latency Set A here 695 * 1066 933 800 733 667 600 533 400 166 696 * RL, 16 14 12 11 10 9 8 6 3 697 * WL, 8 8 6 6 6 5 4 3 1 698 */ 699 if (nmhz <= 400) { 700 pdram_timing->cl = 6; 701 pdram_timing->cwl = 3; 702 pdram_timing->mr[2] = LPDDR3_RL6_WL3; 703 } else if (nmhz <= 533) { 704 pdram_timing->cl = 8; 705 pdram_timing->cwl = 4; 706 pdram_timing->mr[2] = LPDDR3_RL8_WL4; 707 } else if (nmhz <= 600) { 708 pdram_timing->cl = 9; 709 pdram_timing->cwl = 5; 710 pdram_timing->mr[2] = LPDDR3_RL9_WL5; 711 } else if (nmhz <= 667) { 712 pdram_timing->cl = 10; 713 pdram_timing->cwl = 6; 714 pdram_timing->mr[2] = LPDDR3_RL10_WL6; 715 } else if (nmhz <= 733) { 716 pdram_timing->cl = 11; 717 pdram_timing->cwl = 6; 718 pdram_timing->mr[2] = LPDDR3_RL11_WL6; 719 } else if (nmhz <= 800) { 720 pdram_timing->cl = 12; 721 pdram_timing->cwl = 6; 722 pdram_timing->mr[2] = LPDDR3_RL12_WL6; 723 } else if (nmhz <= 933) { 724 pdram_timing->cl = 14; 725 pdram_timing->cwl = 8; 726 pdram_timing->mr[2] = LPDDR3_RL14_WL8; 727 } else { 728 pdram_timing->cl = 16; 729 pdram_timing->cwl = 8; 730 pdram_timing->mr[2] = LPDDR3_RL16_WL8; 731 } 732 switch (timing_config->dramds) { 733 case 80: 734 pdram_timing->mr[3] = LPDDR3_DS_80; 735 break; 736 case 60: 737 pdram_timing->mr[3] = LPDDR3_DS_60; 738 break; 739 case 48: 740 pdram_timing->mr[3] = LPDDR3_DS_48; 741 break; 742 case 40: 743 pdram_timing->mr[3] = LPDDR3_DS_40; 744 break; 745 case 3440: 746 pdram_timing->mr[3] = LPDDR3_DS_34D_40U; 747 break; 748 case 4048: 749 pdram_timing->mr[3] = LPDDR3_DS_40D_48U; 750 break; 751 case 3448: 752 pdram_timing->mr[3] = LPDDR3_DS_34D_48U; 753 break; 754 case 34: 755 default: 756 pdram_timing->mr[3] = LPDDR3_DS_34; 757 break; 758 } 759 pdram_timing->mr[0] = 0; 760 if (timing_config->odt) 761 switch (timing_config->dramodt) { 762 case 60: 763 pdram_timing->mr11 = LPDDR3_ODT_60; 764 break; 765 case 120: 766 pdram_timing->mr11 = LPDDR3_ODT_120; 767 break; 768 case 240: 769 default: 770 pdram_timing->mr11 = LPDDR3_ODT_240; 771 break; 772 } 773 else 774 pdram_timing->mr11 = LPDDR3_ODT_DIS; 775 776 pdram_timing->tinit1 = (LPDDR3_TINIT1 * nmhz + 999) / 1000; 777 pdram_timing->tinit2 = LPDDR3_TINIT2; 778 pdram_timing->tinit3 = (LPDDR3_TINIT3 * nmhz + 999) / 1000; 779 pdram_timing->tinit4 = (LPDDR3_TINIT4 * nmhz + 999) / 1000; 780 pdram_timing->tinit5 = (LPDDR3_TINIT5 * nmhz + 999) / 1000; 781 pdram_timing->trstl = LPDDR3_TRSTL; 782 pdram_timing->trsth = (LPDDR3_TRSTH * nmhz + 999) / 1000; 783 /* tREFI, average periodic refresh interval, 3.9us(4Gb-16Gb) */ 784 pdram_timing->trefi = (LPDDR3_TREFI_3_9_US * nmhz + 999) / 1000; 785 /* base timing */ 786 tmp = ((LPDDR3_TRCD * nmhz + 999) / 1000); 787 pdram_timing->trcd = max(3, tmp); 788 trppb_tmp = ((LPDDR3_TRP_PB * nmhz + 999) / 1000); 789 trppb_tmp = max(3, trppb_tmp); 790 pdram_timing->trppb = trppb_tmp; 791 trp_tmp = ((LPDDR3_TRP_AB * nmhz + 999) / 1000); 792 trp_tmp = max(3, trp_tmp); 793 pdram_timing->trp = trp_tmp; 794 twr_tmp = ((LPDDR3_TWR * nmhz + 999) / 1000); 795 twr_tmp = max(4, twr_tmp); 796 pdram_timing->twr = twr_tmp; 797 if (twr_tmp <= 6) 798 twr_tmp = 6; 799 else if (twr_tmp <= 8) 800 twr_tmp = 8; 801 else if (twr_tmp <= 12) 802 twr_tmp = twr_tmp; 803 else if (twr_tmp <= 14) 804 twr_tmp = 14; 805 else 806 twr_tmp = 16; 807 if (twr_tmp > 9) 808 pdram_timing->mr[2] |= (1 << 4); /*enable nWR > 9*/ 809 twr_tmp = (twr_tmp > 9) ? (twr_tmp - 10) : (twr_tmp - 2); 810 bl_tmp = LPDDR3_BL8; 811 pdram_timing->mr[1] = bl_tmp | LPDDR3_N_WR(twr_tmp); 812 tmp = ((LPDDR3_TRTP * nmhz + (nmhz >> 1) + 999) / 1000); 813 pdram_timing->trtp = max(4, tmp); 814 tras_tmp = ((LPDDR3_TRAS * nmhz + 999) / 1000); 815 tras_tmp = max(3, tras_tmp); 816 pdram_timing->tras_min = tras_tmp; 817 pdram_timing->trc = (tras_tmp + trp_tmp); 818 tmp = ((LPDDR3_TRRD * nmhz + 999) / 1000); 819 pdram_timing->trrd = max(2, tmp); 820 pdram_timing->tccd = LPDDR3_TCCD; 821 tmp = ((LPDDR3_TWTR * nmhz + (nmhz >> 1) + 999) / 1000); 822 pdram_timing->twtr = max(4, tmp); 823 pdram_timing->trtw = ((LPDDR3_TRTW * nmhz + 999) / 1000); 824 pdram_timing->tras_max = ((LPDDR3_TRAS_MAX * nmhz + 999) / 1000); 825 tmp = (LPDDR3_TFAW * nmhz + 999) / 1000; 826 pdram_timing->tfaw = max(8, tmp); 827 if (ddr_capability_per_die > 0x20000000) { 828 pdram_timing->trfc = 829 (LPDDR3_TRFC_8GBIT * nmhz + 999) / 1000; 830 tmp = (((LPDDR3_TRFC_8GBIT + 10) * nmhz + 999) / 1000); 831 } else { 832 pdram_timing->trfc = 833 (LPDDR3_TRFC_4GBIT * nmhz + 999) / 1000; 834 tmp = (((LPDDR3_TRFC_4GBIT + 10) * nmhz + 999) / 1000); 835 } 836 pdram_timing->txsr = max(2, tmp); 837 pdram_timing->txsnr = max(2, tmp); 838 /* tdqsck use rounded down */ 839 pdram_timing->tdqsck = 840 ((LPDDR3_TDQSCK_MIN * nmhz + (nmhz >> 1)) 841 / 1000); 842 pdram_timing->tdqsck_max = 843 ((LPDDR3_TDQSCK_MAX * nmhz + (nmhz >> 1) + 999) 844 / 1000); 845 /*pd and sr*/ 846 tmp = ((LPDDR3_TXP * nmhz + (nmhz >> 1) + 999) / 1000); 847 pdram_timing->txp = max(3, tmp); 848 pdram_timing->txpdll = LPDDR3_TXPDLL; 849 tmp = ((LPDDR3_TCKE * nmhz + (nmhz >> 1) + 999) / 1000); 850 pdram_timing->tcke = max(3, tmp); 851 tmp = ((LPDDR3_TCKESR * nmhz + 999) / 1000); 852 pdram_timing->tckesr = max(3, tmp); 853 pdram_timing->tcksre = LPDDR3_TCKSRE; 854 pdram_timing->tcksrx = LPDDR3_TCKSRX; 855 /*mode register timing*/ 856 pdram_timing->tmod = LPDDR3_TMOD; 857 tmp = ((LPDDR3_TMRD * nmhz + 999) / 1000); 858 pdram_timing->tmrd = max(10, tmp); 859 pdram_timing->tmrr = LPDDR3_TMRR; 860 tmp = ((LPDDR3_TRCD * nmhz + 999) / 1000); 861 pdram_timing->tmrri = max(3, tmp); 862 /* ODT */ 863 pdram_timing->todton = (LPDDR3_TODTON * nmhz + (nmhz >> 1) + 999) 864 / 1000; 865 /* ZQ */ 866 pdram_timing->tzqinit = (LPDDR3_TZQINIT * nmhz + 999) / 1000; 867 pdram_timing->tzqcs = 868 ((LPDDR3_TZQCS * nmhz + 999) / 1000); 869 pdram_timing->tzqoper = 870 ((LPDDR3_TZQCL * nmhz + 999) / 1000); 871 tmp = ((LPDDR3_TZQRESET * nmhz + 999) / 1000); 872 pdram_timing->tzqreset = max(3, tmp); 873 /* write leveling */ 874 pdram_timing->twlmrd = (LPDDR3_TWLMRD * nmhz + 999) / 1000; 875 pdram_timing->twlo = (LPDDR3_TWLO * nmhz + 999) / 1000; 876 pdram_timing->twldqsen = (LPDDR3_TWLDQSEN * nmhz + 999) / 1000; 877 /* CA training */ 878 pdram_timing->tcackel = LPDDR3_TCACKEL; 879 pdram_timing->tcaent = LPDDR3_TCAENT; 880 pdram_timing->tcamrd = LPDDR3_TCAMRD; 881 pdram_timing->tcackeh = LPDDR3_TCACKEH; 882 pdram_timing->tcaext = LPDDR3_TCAEXT; 883 pdram_timing->tadr = (LPDDR3_TADR * nmhz + 999) / 1000; 884 pdram_timing->tmrz = (LPDDR3_TMRZ * nmhz + 999) / 1000; 885 pdram_timing->tcacd = pdram_timing->tadr + 2; 886 887 /* FSP */ 888 pdram_timing->tfc_long = (LPDDR3_TFC_LONG * nmhz + 999) / 1000; 889 } 890 891 #define LPDDR4_TINIT1 (200000) /* 200us */ 892 #define LPDDR4_TINIT2 (10) /* 10ns */ 893 #define LPDDR4_TINIT3 (2000000) /* 2ms */ 894 #define LPDDR4_TINIT4 (5) /* tCK */ 895 #define LPDDR4_TINIT5 (2000) /* 2us */ 896 #define LPDDR4_TRSTL LPDDR4_TINIT1 897 #define LPDDR4_TRSTH LPDDR4_TINIT3 898 #define LPDDR4_TREFI_3_9_US (3900) /* 3.9us */ 899 900 /* base timging */ 901 #define LPDDR4_TRCD (18) /* tRCD, max(18ns,4tCK) */ 902 #define LPDDR4_TRP_PB (18) /* tRPpb, max(18ns, 4tCK) */ 903 #define LPDDR4_TRP_AB (21) /* tRPab, max(21ns, 4tCK) */ 904 #define LPDDR4_TRRD (10) /* tRRD, max(4tCK,10ns) */ 905 #define LPDDR4_TCCD_BL16 (8) /* tCK */ 906 #define LPDDR4_TCCD_BL32 (16) /* tCK */ 907 #define LPDDR4_TWTR (10) /* tWTR, max(8tCK, 10ns) */ 908 #define LPDDR4_TRTW (0) /* tCK register min valid value */ 909 #define LPDDR4_TRAS_MAX (70000) /* 70us */ 910 #define LPDDR4_TRAS (42) /* tRAS, max(3tCK,42ns) */ 911 #define LPDDR4_TFAW (40) /* tFAW,min 40ns) */ 912 #define LPDDR4_TRFC_12GBIT (280) /* tRFC, 280ns(>=12Gb) */ 913 #define LPDDR4_TRFC_6GBIT (180) /* 6Gb/8Gb 180ns */ 914 #define LPDDR4_TRFC_4GBIT (130) /* 4Gb 130ns */ 915 #define LPDDR4_TDQSCK_MIN (1) /* tDQSCKmin,1.5ns */ 916 #define LPDDR4_TDQSCK_MAX (3) /* tDQSCKmax,3.5ns */ 917 #define LPDDR4_TPPD (4) /* tCK */ 918 919 /* pd and sr */ 920 #define LPDDR4_TXP (7) /* tXP, max(5tCK,7.5ns) */ 921 #define LPDDR4_TCKE (7) /* tCKE, max(7.5ns,4 tCK) */ 922 #define LPDDR4_TESCKE (1) /* tESCKE, max(1.75ns, 3tCK) */ 923 #define LPDDR4_TSR (15) /* tSR, max(15ns, 3tCK) */ 924 #define LPDDR4_TCMDCKE (1) /* max(1.75ns, 3tCK) */ 925 #define LPDDR4_TCSCKE (1) /* 1.75ns */ 926 #define LPDDR4_TCKELCS (5) /* max(5ns, 5tCK) */ 927 #define LPDDR4_TCSCKEH (1) /* 1.75ns */ 928 #define LPDDR4_TCKEHCS (7) /* max(7.5ns, 5tCK) */ 929 #define LPDDR4_TMRWCKEL (14) /* max(14ns, 10tCK) */ 930 #define LPDDR4_TCKELCMD (7) /* max(7.5ns, 3tCK) */ 931 #define LPDDR4_TCKEHCMD (7) /* max(7.5ns, 3tCK) */ 932 #define LPDDR4_TCKELPD (7) /* max(7.5ns, 3tCK) */ 933 #define LPDDR4_TCKCKEL (7) /* max(7.5ns, 3tCK) */ 934 935 /* mode register timing */ 936 #define LPDDR4_TMRD (14) /* tMRD, (=tMRW), max(14ns, 10 tCK) */ 937 #define LPDDR4_TMRR (8) /* tMRR, 8 tCK */ 938 939 /* ODT */ 940 #define LPDDR4_TODTON (3) /* 3.5ns */ 941 942 /* ZQ */ 943 #define LPDDR4_TZQCAL (1000) /* 1us */ 944 #define LPDDR4_TZQLAT (30) /* tZQLAT, max(30ns,8tCK) */ 945 #define LPDDR4_TZQRESET (50) /* ZQreset, max(3tCK,50ns) */ 946 #define LPDDR4_TZQCKE (1) /* tZQCKE, max(1.75ns, 3tCK) */ 947 948 /* write leveling */ 949 #define LPDDR4_TWLMRD (40) /* tCK */ 950 #define LPDDR4_TWLO (20) /* ns */ 951 #define LPDDR4_TWLDQSEN (20) /* tCK */ 952 953 /* CA training */ 954 #define LPDDR4_TCAENT (250) /* ns */ 955 #define LPDDR4_TADR (20) /* ns */ 956 #define LPDDR4_TMRZ (1) /* 1.5ns */ 957 #define LPDDR4_TVREF_LONG (250) /* ns */ 958 #define LPDDR4_TVREF_SHORT (100) /* ns */ 959 960 /* VRCG */ 961 #define LPDDR4_TVRCG_ENABLE (200) /* ns */ 962 #define LPDDR4_TVRCG_DISABLE (100) /* ns */ 963 964 /* FSP */ 965 #define LPDDR4_TFC_LONG (250) /* ns */ 966 #define LPDDR4_TCKFSPE (7) /* max(7.5ns, 4tCK) */ 967 #define LPDDR4_TCKFSPX (7) /* max(7.5ns, 4tCK) */ 968 969 /* 970 * Description: depend on input parameter "timing_config", 971 * and calculate all lpddr4 972 * spec timing to "pdram_timing" 973 * parameters: 974 * input: timing_config 975 * output: pdram_timing 976 */ 977 static void lpddr4_get_parameter(struct timing_related_config *timing_config, 978 struct dram_timing_t *pdram_timing) 979 { 980 uint32_t nmhz = timing_config->freq; 981 uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); 982 uint32_t tmp, trp_tmp, trppb_tmp, tras_tmp; 983 984 zeromem((void *)pdram_timing, sizeof(struct dram_timing_t)); 985 pdram_timing->mhz = nmhz; 986 pdram_timing->al = 0; 987 pdram_timing->bl = timing_config->bl; 988 989 /* 990 * Only support Write Latency Set A here 991 * 2133 1866 1600 1333 1066 800 533 266 992 * RL, 36 32 28 24 20 14 10 6 993 * WL, 18 16 14 12 10 8 6 4 994 * nWR, 40 34 30 24 20 16 10 6 995 * nRTP,16 14 12 10 8 8 8 8 996 */ 997 tmp = (timing_config->bl == 32) ? 1 : 0; 998 999 /* 1000 * we always use WR preamble = 2tCK 1001 * RD preamble = Static 1002 */ 1003 tmp |= (1 << 2); 1004 if (nmhz <= 266) { 1005 pdram_timing->cl = 6; 1006 pdram_timing->cwl = 4; 1007 pdram_timing->twr = 6; 1008 pdram_timing->trtp = 8; 1009 pdram_timing->mr[2] = LPDDR4_RL6_NRTP8 | LPDDR4_A_WL4; 1010 } else if (nmhz <= 533) { 1011 if (timing_config->rdbi) { 1012 pdram_timing->cl = 12; 1013 pdram_timing->mr[2] = LPDDR4_RL12_NRTP8 | LPDDR4_A_WL6; 1014 } else { 1015 pdram_timing->cl = 10; 1016 pdram_timing->mr[2] = LPDDR4_RL10_NRTP8 | LPDDR4_A_WL6; 1017 } 1018 pdram_timing->cwl = 6; 1019 pdram_timing->twr = 10; 1020 pdram_timing->trtp = 8; 1021 tmp |= (1 << 4); 1022 } else if (nmhz <= 800) { 1023 if (timing_config->rdbi) { 1024 pdram_timing->cl = 16; 1025 pdram_timing->mr[2] = LPDDR4_RL16_NRTP8 | LPDDR4_A_WL8; 1026 } else { 1027 pdram_timing->cl = 14; 1028 pdram_timing->mr[2] = LPDDR4_RL14_NRTP8 | LPDDR4_A_WL8; 1029 } 1030 pdram_timing->cwl = 8; 1031 pdram_timing->twr = 16; 1032 pdram_timing->trtp = 8; 1033 tmp |= (2 << 4); 1034 } else if (nmhz <= 1066) { 1035 if (timing_config->rdbi) { 1036 pdram_timing->cl = 22; 1037 pdram_timing->mr[2] = LPDDR4_RL22_NRTP8 | LPDDR4_A_WL10; 1038 } else { 1039 pdram_timing->cl = 20; 1040 pdram_timing->mr[2] = LPDDR4_RL20_NRTP8 | LPDDR4_A_WL10; 1041 } 1042 pdram_timing->cwl = 10; 1043 pdram_timing->twr = 20; 1044 pdram_timing->trtp = 8; 1045 tmp |= (3 << 4); 1046 } else if (nmhz <= 1333) { 1047 if (timing_config->rdbi) { 1048 pdram_timing->cl = 28; 1049 pdram_timing->mr[2] = LPDDR4_RL28_NRTP10 | 1050 LPDDR4_A_WL12; 1051 } else { 1052 pdram_timing->cl = 24; 1053 pdram_timing->mr[2] = LPDDR4_RL24_NRTP10 | 1054 LPDDR4_A_WL12; 1055 } 1056 pdram_timing->cwl = 12; 1057 pdram_timing->twr = 24; 1058 pdram_timing->trtp = 10; 1059 tmp |= (4 << 4); 1060 } else if (nmhz <= 1600) { 1061 if (timing_config->rdbi) { 1062 pdram_timing->cl = 32; 1063 pdram_timing->mr[2] = LPDDR4_RL32_NRTP12 | 1064 LPDDR4_A_WL14; 1065 } else { 1066 pdram_timing->cl = 28; 1067 pdram_timing->mr[2] = LPDDR4_RL28_NRTP12 | 1068 LPDDR4_A_WL14; 1069 } 1070 pdram_timing->cwl = 14; 1071 pdram_timing->twr = 30; 1072 pdram_timing->trtp = 12; 1073 tmp |= (5 << 4); 1074 } else if (nmhz <= 1866) { 1075 if (timing_config->rdbi) { 1076 pdram_timing->cl = 36; 1077 pdram_timing->mr[2] = LPDDR4_RL36_NRTP14 | 1078 LPDDR4_A_WL16; 1079 } else { 1080 pdram_timing->cl = 32; 1081 pdram_timing->mr[2] = LPDDR4_RL32_NRTP14 | 1082 LPDDR4_A_WL16; 1083 } 1084 pdram_timing->cwl = 16; 1085 pdram_timing->twr = 34; 1086 pdram_timing->trtp = 14; 1087 tmp |= (6 << 4); 1088 } else { 1089 if (timing_config->rdbi) { 1090 pdram_timing->cl = 40; 1091 pdram_timing->mr[2] = LPDDR4_RL40_NRTP16 | 1092 LPDDR4_A_WL18; 1093 } else { 1094 pdram_timing->cl = 36; 1095 pdram_timing->mr[2] = LPDDR4_RL36_NRTP16 | 1096 LPDDR4_A_WL18; 1097 } 1098 pdram_timing->cwl = 18; 1099 pdram_timing->twr = 40; 1100 pdram_timing->trtp = 16; 1101 tmp |= (7 << 4); 1102 } 1103 pdram_timing->mr[1] = tmp; 1104 tmp = (timing_config->rdbi ? LPDDR4_DBI_RD_EN : 0) | 1105 (timing_config->wdbi ? LPDDR4_DBI_WR_EN : 0); 1106 switch (timing_config->dramds) { 1107 case 240: 1108 pdram_timing->mr[3] = LPDDR4_PDDS_240 | tmp; 1109 break; 1110 case 120: 1111 pdram_timing->mr[3] = LPDDR4_PDDS_120 | tmp; 1112 break; 1113 case 80: 1114 pdram_timing->mr[3] = LPDDR4_PDDS_80 | tmp; 1115 break; 1116 case 60: 1117 pdram_timing->mr[3] = LPDDR4_PDDS_60 | tmp; 1118 break; 1119 case 48: 1120 pdram_timing->mr[3] = LPDDR4_PDDS_48 | tmp; 1121 break; 1122 case 40: 1123 default: 1124 pdram_timing->mr[3] = LPDDR4_PDDS_40 | tmp; 1125 break; 1126 } 1127 pdram_timing->mr[0] = 0; 1128 if (timing_config->odt) { 1129 switch (timing_config->dramodt) { 1130 case 240: 1131 tmp = LPDDR4_DQODT_240; 1132 break; 1133 case 120: 1134 tmp = LPDDR4_DQODT_120; 1135 break; 1136 case 80: 1137 tmp = LPDDR4_DQODT_80; 1138 break; 1139 case 60: 1140 tmp = LPDDR4_DQODT_60; 1141 break; 1142 case 48: 1143 tmp = LPDDR4_DQODT_48; 1144 break; 1145 case 40: 1146 default: 1147 tmp = LPDDR4_DQODT_40; 1148 break; 1149 } 1150 1151 switch (timing_config->caodt) { 1152 case 240: 1153 pdram_timing->mr11 = LPDDR4_CAODT_240 | tmp; 1154 break; 1155 case 120: 1156 pdram_timing->mr11 = LPDDR4_CAODT_120 | tmp; 1157 break; 1158 case 80: 1159 pdram_timing->mr11 = LPDDR4_CAODT_80 | tmp; 1160 break; 1161 case 60: 1162 pdram_timing->mr11 = LPDDR4_CAODT_60 | tmp; 1163 break; 1164 case 48: 1165 pdram_timing->mr11 = LPDDR4_CAODT_48 | tmp; 1166 break; 1167 case 40: 1168 default: 1169 pdram_timing->mr11 = LPDDR4_CAODT_40 | tmp; 1170 break; 1171 } 1172 } else { 1173 pdram_timing->mr11 = LPDDR4_CAODT_DIS | tmp; 1174 } 1175 1176 pdram_timing->tinit1 = (LPDDR4_TINIT1 * nmhz + 999) / 1000; 1177 pdram_timing->tinit2 = (LPDDR4_TINIT2 * nmhz + 999) / 1000; 1178 pdram_timing->tinit3 = (LPDDR4_TINIT3 * nmhz + 999) / 1000; 1179 pdram_timing->tinit4 = (LPDDR4_TINIT4 * nmhz + 999) / 1000; 1180 pdram_timing->tinit5 = (LPDDR4_TINIT5 * nmhz + 999) / 1000; 1181 pdram_timing->trstl = (LPDDR4_TRSTL * nmhz + 999) / 1000; 1182 pdram_timing->trsth = (LPDDR4_TRSTH * nmhz + 999) / 1000; 1183 /* tREFI, average periodic refresh interval, 3.9us(4Gb-16Gb) */ 1184 pdram_timing->trefi = (LPDDR4_TREFI_3_9_US * nmhz + 999) / 1000; 1185 /* base timing */ 1186 tmp = ((LPDDR4_TRCD * nmhz + 999) / 1000); 1187 pdram_timing->trcd = max(4, tmp); 1188 trppb_tmp = ((LPDDR4_TRP_PB * nmhz + 999) / 1000); 1189 trppb_tmp = max(4, trppb_tmp); 1190 pdram_timing->trppb = trppb_tmp; 1191 trp_tmp = ((LPDDR4_TRP_AB * nmhz + 999) / 1000); 1192 trp_tmp = max(4, trp_tmp); 1193 pdram_timing->trp = trp_tmp; 1194 tras_tmp = ((LPDDR4_TRAS * nmhz + 999) / 1000); 1195 tras_tmp = max(3, tras_tmp); 1196 pdram_timing->tras_min = tras_tmp; 1197 pdram_timing->trc = (tras_tmp + trp_tmp); 1198 tmp = ((LPDDR4_TRRD * nmhz + 999) / 1000); 1199 pdram_timing->trrd = max(4, tmp); 1200 if (timing_config->bl == 32) 1201 pdram_timing->tccd = LPDDR4_TCCD_BL16; 1202 else 1203 pdram_timing->tccd = LPDDR4_TCCD_BL32; 1204 pdram_timing->tccdmw = 4 * pdram_timing->tccd; 1205 tmp = ((LPDDR4_TWTR * nmhz + 999) / 1000); 1206 pdram_timing->twtr = max(8, tmp); 1207 pdram_timing->trtw = ((LPDDR4_TRTW * nmhz + 999) / 1000); 1208 pdram_timing->tras_max = ((LPDDR4_TRAS_MAX * nmhz + 999) / 1000); 1209 pdram_timing->tfaw = (LPDDR4_TFAW * nmhz + 999) / 1000; 1210 if (ddr_capability_per_die > 0x60000000) { 1211 /* >= 12Gb */ 1212 pdram_timing->trfc = 1213 (LPDDR4_TRFC_12GBIT * nmhz + 999) / 1000; 1214 tmp = (((LPDDR4_TRFC_12GBIT + 7) * nmhz + (nmhz >> 1) + 1215 999) / 1000); 1216 } else if (ddr_capability_per_die > 0x30000000) { 1217 pdram_timing->trfc = 1218 (LPDDR4_TRFC_6GBIT * nmhz + 999) / 1000; 1219 tmp = (((LPDDR4_TRFC_6GBIT + 7) * nmhz + (nmhz >> 1) + 1220 999) / 1000); 1221 } else { 1222 pdram_timing->trfc = 1223 (LPDDR4_TRFC_4GBIT * nmhz + 999) / 1000; 1224 tmp = (((LPDDR4_TRFC_4GBIT + 7) * nmhz + (nmhz >> 1) + 1225 999) / 1000); 1226 } 1227 pdram_timing->txsr = max(2, tmp); 1228 pdram_timing->txsnr = max(2, tmp); 1229 /* tdqsck use rounded down */ 1230 pdram_timing->tdqsck = ((LPDDR4_TDQSCK_MIN * nmhz + 1231 (nmhz >> 1)) / 1000); 1232 pdram_timing->tdqsck_max = ((LPDDR4_TDQSCK_MAX * nmhz + 1233 (nmhz >> 1) + 999) / 1000); 1234 pdram_timing->tppd = LPDDR4_TPPD; 1235 /* pd and sr */ 1236 tmp = ((LPDDR4_TXP * nmhz + (nmhz >> 1) + 999) / 1000); 1237 pdram_timing->txp = max(5, tmp); 1238 tmp = ((LPDDR4_TCKE * nmhz + (nmhz >> 1) + 999) / 1000); 1239 pdram_timing->tcke = max(4, tmp); 1240 tmp = ((LPDDR4_TESCKE * nmhz + 1241 ((nmhz * 3) / 4) + 1242 999) / 1000); 1243 pdram_timing->tescke = max(3, tmp); 1244 tmp = ((LPDDR4_TSR * nmhz + 999) / 1000); 1245 pdram_timing->tsr = max(3, tmp); 1246 tmp = ((LPDDR4_TCMDCKE * nmhz + 1247 ((nmhz * 3) / 4) + 1248 999) / 1000); 1249 pdram_timing->tcmdcke = max(3, tmp); 1250 pdram_timing->tcscke = ((LPDDR4_TCSCKE * nmhz + 1251 ((nmhz * 3) / 4) + 1252 999) / 1000); 1253 tmp = ((LPDDR4_TCKELCS * nmhz + 999) / 1000); 1254 pdram_timing->tckelcs = max(5, tmp); 1255 pdram_timing->tcsckeh = ((LPDDR4_TCSCKEH * nmhz + 1256 ((nmhz * 3) / 4) + 1257 999) / 1000); 1258 tmp = ((LPDDR4_TCKEHCS * nmhz + 1259 (nmhz >> 1) + 999) / 1000); 1260 pdram_timing->tckehcs = max(5, tmp); 1261 tmp = ((LPDDR4_TMRWCKEL * nmhz + 999) / 1000); 1262 pdram_timing->tmrwckel = max(10, tmp); 1263 tmp = ((LPDDR4_TCKELCMD * nmhz + (nmhz >> 1) + 1264 999) / 1000); 1265 pdram_timing->tckelcmd = max(3, tmp); 1266 tmp = ((LPDDR4_TCKEHCMD * nmhz + (nmhz >> 1) + 1267 999) / 1000); 1268 pdram_timing->tckehcmd = max(3, tmp); 1269 tmp = ((LPDDR4_TCKELPD * nmhz + (nmhz >> 1) + 1270 999) / 1000); 1271 pdram_timing->tckelpd = max(3, tmp); 1272 tmp = ((LPDDR4_TCKCKEL * nmhz + (nmhz >> 1) + 1273 999) / 1000); 1274 pdram_timing->tckckel = max(3, tmp); 1275 /* mode register timing */ 1276 tmp = ((LPDDR4_TMRD * nmhz + 999) / 1000); 1277 pdram_timing->tmrd = max(10, tmp); 1278 pdram_timing->tmrr = LPDDR4_TMRR; 1279 pdram_timing->tmrri = pdram_timing->trcd + 3; 1280 /* ODT */ 1281 pdram_timing->todton = (LPDDR4_TODTON * nmhz + (nmhz >> 1) + 999) 1282 / 1000; 1283 /* ZQ */ 1284 pdram_timing->tzqcal = (LPDDR4_TZQCAL * nmhz + 999) / 1000; 1285 tmp = ((LPDDR4_TZQLAT * nmhz + 999) / 1000); 1286 pdram_timing->tzqlat = max(8, tmp); 1287 tmp = ((LPDDR4_TZQRESET * nmhz + 999) / 1000); 1288 pdram_timing->tzqreset = max(3, tmp); 1289 tmp = ((LPDDR4_TZQCKE * nmhz + 1290 ((nmhz * 3) / 4) + 1291 999) / 1000); 1292 pdram_timing->tzqcke = max(3, tmp); 1293 /* write leveling */ 1294 pdram_timing->twlmrd = LPDDR4_TWLMRD; 1295 pdram_timing->twlo = (LPDDR4_TWLO * nmhz + 999) / 1000; 1296 pdram_timing->twldqsen = LPDDR4_TWLDQSEN; 1297 /* CA training */ 1298 pdram_timing->tcaent = (LPDDR4_TCAENT * nmhz + 999) / 1000; 1299 pdram_timing->tadr = (LPDDR4_TADR * nmhz + 999) / 1000; 1300 pdram_timing->tmrz = (LPDDR4_TMRZ * nmhz + (nmhz >> 1) + 999) / 1000; 1301 pdram_timing->tvref_long = (LPDDR4_TVREF_LONG * nmhz + 999) / 1000; 1302 pdram_timing->tvref_short = (LPDDR4_TVREF_SHORT * nmhz + 999) / 1000; 1303 /* VRCG */ 1304 pdram_timing->tvrcg_enable = (LPDDR4_TVRCG_ENABLE * nmhz + 1305 999) / 1000; 1306 pdram_timing->tvrcg_disable = (LPDDR4_TVRCG_DISABLE * nmhz + 1307 999) / 1000; 1308 /* FSP */ 1309 pdram_timing->tfc_long = (LPDDR4_TFC_LONG * nmhz + 999) / 1000; 1310 tmp = (LPDDR4_TCKFSPE * nmhz + (nmhz >> 1) + 999) / 1000; 1311 pdram_timing->tckfspe = max(4, tmp); 1312 tmp = (LPDDR4_TCKFSPX * nmhz + (nmhz >> 1) + 999) / 1000; 1313 pdram_timing->tckfspx = max(4, tmp); 1314 } 1315 1316 /* 1317 * Description: depend on input parameter "timing_config", 1318 * and calculate correspond "dram_type" 1319 * spec timing to "pdram_timing" 1320 * parameters: 1321 * input: timing_config 1322 * output: pdram_timing 1323 * NOTE: MR ODT is set, need to disable by controller 1324 */ 1325 void dram_get_parameter(struct timing_related_config *timing_config, 1326 struct dram_timing_t *pdram_timing) 1327 { 1328 switch (timing_config->dram_type) { 1329 case DDR3: 1330 ddr3_get_parameter(timing_config, pdram_timing); 1331 break; 1332 case LPDDR2: 1333 lpddr2_get_parameter(timing_config, pdram_timing); 1334 break; 1335 case LPDDR3: 1336 lpddr3_get_parameter(timing_config, pdram_timing); 1337 break; 1338 case LPDDR4: 1339 lpddr4_get_parameter(timing_config, pdram_timing); 1340 break; 1341 } 1342 } 1343