1 /* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <string.h> 32 #include <stdint.h> 33 #include <dram.h> 34 #include <utils.h> 35 #include "dram_spec_timing.h" 36 37 static const uint8_t ddr3_cl_cwl[][7] = { 38 /* 39 * speed 0~330 331 ~ 400 401 ~ 533 534~666 667~800 801~933 934~1066 40 * tCK>3 2.5~3 1.875~2.5 1.5~1.875 1.25~1.5 1.07~1.25 0.938~1.07 41 * cl<<4, cwl cl<<4, cwl cl<<4, cwl 42 */ 43 /* DDR3_800D (5-5-5) */ 44 {((5 << 4) | 5), ((5 << 4) | 5), 0, 0, 0, 0, 0}, 45 /* DDR3_800E (6-6-6) */ 46 {((5 << 4) | 5), ((6 << 4) | 5), 0, 0, 0, 0, 0}, 47 /* DDR3_1066E (6-6-6) */ 48 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), 0, 0, 0, 0}, 49 /* DDR3_1066F (7-7-7) */ 50 {((5 << 4) | 5), ((6 << 4) | 5), ((7 << 4) | 6), 0, 0, 0, 0}, 51 /* DDR3_1066G (8-8-8) */ 52 {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), 0, 0, 0, 0}, 53 /* DDR3_1333F (7-7-7) */ 54 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((7 << 4) | 7), 55 0, 0, 0}, 56 /* DDR3_1333G (8-8-8) */ 57 {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((8 << 4) | 7), 58 0, 0, 0}, 59 /* DDR3_1333H (9-9-9) */ 60 {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((9 << 4) | 7), 61 0, 0, 0}, 62 /* DDR3_1333J (10-10-10) */ 63 {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7), 64 0, 0, 0}, 65 /* DDR3_1600G (8-8-8) */ 66 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((7 << 4) | 7), 67 ((8 << 4) | 8), 0, 0}, 68 /* DDR3_1600H (9-9-9) */ 69 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((8 << 4) | 7), 70 ((9 << 4) | 8), 0, 0}, 71 /* DDR3_1600J (10-10-10) */ 72 {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7), 73 ((10 << 4) | 8), 0, 0}, 74 /* DDR3_1600K (11-11-11) */ 75 {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7), 76 ((11 << 4) | 8), 0, 0}, 77 /* DDR3_1866J (10-10-10) */ 78 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((8 << 4) | 7), 79 ((9 << 4) | 8), ((11 << 4) | 9), 0}, 80 /* DDR3_1866K (11-11-11) */ 81 {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((8 << 4) | 7), 82 ((10 << 4) | 8), ((11 << 4) | 9), 0}, 83 /* DDR3_1866L (12-12-12) */ 84 {((6 << 4) | 5), ((6 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7), 85 ((11 << 4) | 8), ((12 << 4) | 9), 0}, 86 /* DDR3_1866M (13-13-13) */ 87 {((6 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7), 88 ((11 << 4) | 8), ((13 << 4) | 9), 0}, 89 /* DDR3_2133K (11-11-11) */ 90 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((7 << 4) | 7), 91 ((9 << 4) | 8), ((10 << 4) | 9), ((11 << 4) | 10)}, 92 /* DDR3_2133L (12-12-12) */ 93 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((8 << 4) | 7), 94 ((9 << 4) | 8), ((11 << 4) | 9), ((12 << 4) | 10)}, 95 /* DDR3_2133M (13-13-13) */ 96 {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7), 97 ((10 << 4) | 8), ((12 << 4) | 9), ((13 << 4) | 10)}, 98 /* DDR3_2133N (14-14-14) */ 99 {((6 << 4) | 5), ((6 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7), 100 ((11 << 4) | 8), ((13 << 4) | 9), ((14 << 4) | 10)}, 101 /* DDR3_DEFAULT */ 102 {((6 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7), 103 ((11 << 4) | 8), ((13 << 4) | 9), ((14 << 4) | 10)} 104 }; 105 106 static const uint16_t ddr3_trc_tfaw[] = { 107 /* tRC tFAW */ 108 ((50 << 8) | 50), /* DDR3_800D (5-5-5) */ 109 ((53 << 8) | 50), /* DDR3_800E (6-6-6) */ 110 111 ((49 << 8) | 50), /* DDR3_1066E (6-6-6) */ 112 ((51 << 8) | 50), /* DDR3_1066F (7-7-7) */ 113 ((53 << 8) | 50), /* DDR3_1066G (8-8-8) */ 114 115 ((47 << 8) | 45), /* DDR3_1333F (7-7-7) */ 116 ((48 << 8) | 45), /* DDR3_1333G (8-8-8) */ 117 ((50 << 8) | 45), /* DDR3_1333H (9-9-9) */ 118 ((51 << 8) | 45), /* DDR3_1333J (10-10-10) */ 119 120 ((45 << 8) | 40), /* DDR3_1600G (8-8-8) */ 121 ((47 << 8) | 40), /* DDR3_1600H (9-9-9)*/ 122 ((48 << 8) | 40), /* DDR3_1600J (10-10-10) */ 123 ((49 << 8) | 40), /* DDR3_1600K (11-11-11) */ 124 125 ((45 << 8) | 35), /* DDR3_1866J (10-10-10) */ 126 ((46 << 8) | 35), /* DDR3_1866K (11-11-11) */ 127 ((47 << 8) | 35), /* DDR3_1866L (12-12-12) */ 128 ((48 << 8) | 35), /* DDR3_1866M (13-13-13) */ 129 130 ((44 << 8) | 35), /* DDR3_2133K (11-11-11) */ 131 ((45 << 8) | 35), /* DDR3_2133L (12-12-12) */ 132 ((46 << 8) | 35), /* DDR3_2133M (13-13-13) */ 133 ((47 << 8) | 35), /* DDR3_2133N (14-14-14) */ 134 135 ((53 << 8) | 50) /* DDR3_DEFAULT */ 136 }; 137 138 static uint32_t get_max_speed_rate(struct timing_related_config *timing_config) 139 { 140 if (timing_config->ch_cnt > 1) 141 return max(timing_config->dram_info[0].speed_rate, 142 timing_config->dram_info[1].speed_rate); 143 else 144 return timing_config->dram_info[0].speed_rate; 145 } 146 147 static uint32_t 148 get_max_die_capability(struct timing_related_config *timing_config) 149 { 150 uint32_t die_cap = 0; 151 uint32_t cs, ch; 152 153 for (ch = 0; ch < timing_config->ch_cnt; ch++) { 154 for (cs = 0; cs < timing_config->dram_info[ch].cs_cnt; cs++) { 155 die_cap = max(die_cap, 156 timing_config-> 157 dram_info[ch].per_die_capability[cs]); 158 } 159 } 160 return die_cap; 161 } 162 163 /* tRSTL, 100ns */ 164 #define DDR3_TRSTL (100) 165 /* trsth, 500us */ 166 #define DDR3_TRSTH (500000) 167 /* trefi, 7.8us */ 168 #define DDR3_TREFI_7_8_US (7800) 169 /* tWR, 15ns */ 170 #define DDR3_TWR (15) 171 /* tRTP, max(4 tCK,7.5ns) */ 172 #define DDR3_TRTP (7) 173 /* tRRD = max(4nCK, 10ns) */ 174 #define DDR3_TRRD (10) 175 /* tCK */ 176 #define DDR3_TCCD (4) 177 /*tWTR, max(4 tCK,7.5ns)*/ 178 #define DDR3_TWTR (7) 179 /* tCK */ 180 #define DDR3_TRTW (0) 181 /* tRAS, 37.5ns(400MHz) 37.5ns(533MHz) */ 182 #define DDR3_TRAS (37) 183 /* ns */ 184 #define DDR3_TRFC_512MBIT (90) 185 /* ns */ 186 #define DDR3_TRFC_1GBIT (110) 187 /* ns */ 188 #define DDR3_TRFC_2GBIT (160) 189 /* ns */ 190 #define DDR3_TRFC_4GBIT (300) 191 /* ns */ 192 #define DDR3_TRFC_8GBIT (350) 193 194 /*pd and sr*/ 195 #define DDR3_TXP (7) /* tXP, max(3 tCK, 7.5ns)( < 933MHz) */ 196 #define DDR3_TXPDLL (24) /* tXPDLL, max(10 tCK, 24ns) */ 197 #define DDR3_TDLLK (512) /* tXSR, tDLLK=512 tCK */ 198 #define DDR3_TCKE_400MHZ (7) /* tCKE, max(3 tCK,7.5ns)(400MHz) */ 199 #define DDR3_TCKE_533MHZ (6) /* tCKE, max(3 tCK,5.625ns)(533MHz) */ 200 #define DDR3_TCKSRE (10) /* tCKSRX, max(5 tCK, 10ns) */ 201 202 /*mode register timing*/ 203 #define DDR3_TMOD (15) /* tMOD, max(12 tCK,15ns) */ 204 #define DDR3_TMRD (4) /* tMRD, 4 tCK */ 205 206 /* ZQ */ 207 #define DDR3_TZQINIT (640) /* tZQinit, max(512 tCK, 640ns) */ 208 #define DDR3_TZQCS (80) /* tZQCS, max(64 tCK, 80ns) */ 209 #define DDR3_TZQOPER (320) /* tZQoper, max(256 tCK, 320ns) */ 210 211 /* Write leveling */ 212 #define DDR3_TWLMRD (40) /* tCK */ 213 #define DDR3_TWLO (9) /* max 7.5ns */ 214 #define DDR3_TWLDQSEN (25) /* tCK */ 215 216 /* 217 * Description: depend on input parameter "timing_config", 218 * and calculate all ddr3 219 * spec timing to "pdram_timing" 220 * parameters: 221 * input: timing_config 222 * output: pdram_timing 223 */ 224 static void ddr3_get_parameter(struct timing_related_config *timing_config, 225 struct dram_timing_t *pdram_timing) 226 { 227 uint32_t nmhz = timing_config->freq; 228 uint32_t ddr_speed_bin = get_max_speed_rate(timing_config); 229 uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); 230 uint32_t tmp; 231 232 zeromem((void *)pdram_timing, sizeof(struct dram_timing_t)); 233 pdram_timing->mhz = nmhz; 234 pdram_timing->al = 0; 235 pdram_timing->bl = timing_config->bl; 236 if (nmhz <= 330) 237 tmp = 0; 238 else if (nmhz <= 400) 239 tmp = 1; 240 else if (nmhz <= 533) 241 tmp = 2; 242 else if (nmhz <= 666) 243 tmp = 3; 244 else if (nmhz <= 800) 245 tmp = 4; 246 else if (nmhz <= 933) 247 tmp = 5; 248 else 249 tmp = 6; 250 251 /* when dll bypss cl = cwl = 6 */ 252 if (nmhz < 300) { 253 pdram_timing->cl = 6; 254 pdram_timing->cwl = 6; 255 } else { 256 pdram_timing->cl = (ddr3_cl_cwl[ddr_speed_bin][tmp] >> 4) & 0xf; 257 pdram_timing->cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0xf; 258 } 259 260 switch (timing_config->dramds) { 261 case 40: 262 tmp = DDR3_DS_40; 263 break; 264 case 34: 265 default: 266 tmp = DDR3_DS_34; 267 break; 268 } 269 270 switch (timing_config->dramodt) { 271 case 60: 272 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_60; 273 break; 274 case 40: 275 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_40; 276 break; 277 case 120: 278 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_120; 279 break; 280 case 0: 281 default: 282 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_DIS; 283 break; 284 } 285 286 pdram_timing->mr[2] = DDR3_MR2_CWL(pdram_timing->cwl); 287 pdram_timing->mr[3] = 0; 288 289 pdram_timing->trstl = ((DDR3_TRSTL * nmhz + 999) / 1000); 290 pdram_timing->trsth = ((DDR3_TRSTH * nmhz + 999) / 1000); 291 /* tREFI, average periodic refresh interval, 7.8us */ 292 pdram_timing->trefi = ((DDR3_TREFI_7_8_US * nmhz + 999) / 1000); 293 /* base timing */ 294 pdram_timing->trcd = pdram_timing->cl; 295 pdram_timing->trp = pdram_timing->cl; 296 pdram_timing->trppb = pdram_timing->cl; 297 tmp = ((DDR3_TWR * nmhz + 999) / 1000); 298 pdram_timing->twr = tmp; 299 pdram_timing->tdal = tmp + pdram_timing->trp; 300 if (tmp < 9) { 301 tmp = tmp - 4; 302 } else { 303 tmp += (tmp & 0x1) ? 1 : 0; 304 tmp = tmp >> 1; 305 } 306 if (pdram_timing->bl == 4) 307 pdram_timing->mr[0] = DDR3_BC4 308 | DDR3_CL(pdram_timing->cl) 309 | DDR3_WR(tmp); 310 else 311 pdram_timing->mr[0] = DDR3_BL8 312 | DDR3_CL(pdram_timing->cl) 313 | DDR3_WR(tmp); 314 tmp = ((DDR3_TRTP * nmhz + (nmhz >> 1) + 999) / 1000); 315 pdram_timing->trtp = max(4, tmp); 316 pdram_timing->trc = 317 (((ddr3_trc_tfaw[ddr_speed_bin] >> 8) * nmhz + 999) / 1000); 318 tmp = ((DDR3_TRRD * nmhz + 999) / 1000); 319 pdram_timing->trrd = max(4, tmp); 320 pdram_timing->tccd = DDR3_TCCD; 321 tmp = ((DDR3_TWTR * nmhz + (nmhz >> 1) + 999) / 1000); 322 pdram_timing->twtr = max(4, tmp); 323 pdram_timing->trtw = DDR3_TRTW; 324 pdram_timing->tras_max = 9 * pdram_timing->trefi; 325 pdram_timing->tras_min = ((DDR3_TRAS * nmhz + (nmhz >> 1) + 999) 326 / 1000); 327 pdram_timing->tfaw = 328 (((ddr3_trc_tfaw[ddr_speed_bin] & 0x0ff) * nmhz + 999) 329 / 1000); 330 /* tRFC, 90ns(512Mb),110ns(1Gb),160ns(2Gb),300ns(4Gb),350ns(8Gb) */ 331 if (ddr_capability_per_die <= 0x4000000) 332 tmp = DDR3_TRFC_512MBIT; 333 else if (ddr_capability_per_die <= 0x8000000) 334 tmp = DDR3_TRFC_1GBIT; 335 else if (ddr_capability_per_die <= 0x10000000) 336 tmp = DDR3_TRFC_2GBIT; 337 else if (ddr_capability_per_die <= 0x20000000) 338 tmp = DDR3_TRFC_4GBIT; 339 else 340 tmp = DDR3_TRFC_8GBIT; 341 pdram_timing->trfc = (tmp * nmhz + 999) / 1000; 342 pdram_timing->txsnr = max(5, (((tmp + 10) * nmhz + 999) / 1000)); 343 pdram_timing->tdqsck_max = 0; 344 /*pd and sr*/ 345 pdram_timing->txsr = DDR3_TDLLK; 346 tmp = ((DDR3_TXP * nmhz + (nmhz >> 1) + 999) / 1000); 347 pdram_timing->txp = max(3, tmp); 348 tmp = ((DDR3_TXPDLL * nmhz + 999) / 1000); 349 pdram_timing->txpdll = max(10, tmp); 350 pdram_timing->tdllk = DDR3_TDLLK; 351 if (nmhz >= 533) 352 tmp = ((DDR3_TCKE_533MHZ * nmhz + 999) / 1000); 353 else 354 tmp = ((DDR3_TCKE_400MHZ * nmhz + (nmhz >> 1) + 999) / 1000); 355 pdram_timing->tcke = max(3, tmp); 356 pdram_timing->tckesr = (pdram_timing->tcke + 1); 357 tmp = ((DDR3_TCKSRE * nmhz + 999) / 1000); 358 pdram_timing->tcksre = max(5, tmp); 359 pdram_timing->tcksrx = max(5, tmp); 360 /*mode register timing*/ 361 tmp = ((DDR3_TMOD * nmhz + 999) / 1000); 362 pdram_timing->tmod = max(12, tmp); 363 pdram_timing->tmrd = DDR3_TMRD; 364 pdram_timing->tmrr = 0; 365 /*ODT*/ 366 pdram_timing->todton = pdram_timing->cwl - 2; 367 /*ZQ*/ 368 tmp = ((DDR3_TZQINIT * nmhz + 999) / 1000); 369 pdram_timing->tzqinit = max(512, tmp); 370 tmp = ((DDR3_TZQCS * nmhz + 999) / 1000); 371 pdram_timing->tzqcs = max(64, tmp); 372 tmp = ((DDR3_TZQOPER * nmhz + 999) / 1000); 373 pdram_timing->tzqoper = max(256, tmp); 374 /* write leveling */ 375 pdram_timing->twlmrd = DDR3_TWLMRD; 376 pdram_timing->twldqsen = DDR3_TWLDQSEN; 377 pdram_timing->twlo = ((DDR3_TWLO * nmhz + (nmhz >> 1) + 999) / 1000); 378 } 379 380 #define LPDDR2_TINIT1 (100) /* ns */ 381 #define LPDDR2_TINIT2 (5) /* tCK */ 382 #define LPDDR2_TINIT3 (200000) /* 200us */ 383 #define LPDDR2_TINIT4 (1000) /* 1us */ 384 #define LPDDR2_TINIT5 (10000) /* 10us */ 385 #define LPDDR2_TRSTL (0) /* tCK */ 386 #define LPDDR2_TRSTH (500000) /* 500us */ 387 #define LPDDR2_TREFI_3_9_US (3900) /* 3.9us */ 388 #define LPDDR2_TREFI_7_8_US (7800) /* 7.8us */ 389 390 /* base timing */ 391 #define LPDDR2_TRCD (24) /* tRCD,15ns(Fast)18ns(Typ)24ns(Slow) */ 392 #define LPDDR2_TRP_PB (18) /* tRPpb,15ns(Fast)18ns(Typ)24ns(Slow) */ 393 #define LPDDR2_TRP_AB_8_BANK (21) /* tRPab,18ns(Fast)21ns(Typ)27ns(Slow) */ 394 #define LPDDR2_TWR (15) /* tWR, max(3tCK,15ns) */ 395 #define LPDDR2_TRTP (7) /* tRTP, max(2tCK, 7.5ns) */ 396 #define LPDDR2_TRRD (10) /* tRRD, max(2tCK,10ns) */ 397 #define LPDDR2_TCCD (2) /* tCK */ 398 #define LPDDR2_TWTR_GREAT_200MHZ (7) /* ns */ 399 #define LPDDR2_TWTR_LITTLE_200MHZ (10) /* ns */ 400 #define LPDDR2_TRTW (0) /* tCK */ 401 #define LPDDR2_TRAS_MAX (70000) /* 70us */ 402 #define LPDDR2_TRAS (42) /* tRAS, max(3tCK,42ns) */ 403 #define LPDDR2_TFAW_GREAT_200MHZ (50) /* max(8tCK,50ns) */ 404 #define LPDDR2_TFAW_LITTLE_200MHZ (60) /* max(8tCK,60ns) */ 405 #define LPDDR2_TRFC_8GBIT (210) /* ns */ 406 #define LPDDR2_TRFC_4GBIT (130) /* ns */ 407 #define LPDDR2_TDQSCK_MIN (2) /* tDQSCKmin, 2.5ns */ 408 #define LPDDR2_TDQSCK_MAX (5) /* tDQSCKmax, 5.5ns */ 409 410 /*pd and sr*/ 411 #define LPDDR2_TXP (7) /* tXP, max(2tCK,7.5ns) */ 412 #define LPDDR2_TXPDLL (0) 413 #define LPDDR2_TDLLK (0) /* tCK */ 414 #define LPDDR2_TCKE (3) /* tCK */ 415 #define LPDDR2_TCKESR (15) /* tCKESR, max(3tCK,15ns) */ 416 #define LPDDR2_TCKSRE (1) /* tCK */ 417 #define LPDDR2_TCKSRX (2) /* tCK */ 418 419 /*mode register timing*/ 420 #define LPDDR2_TMOD (0) 421 #define LPDDR2_TMRD (5) /* tMRD, (=tMRW), 5 tCK */ 422 #define LPDDR2_TMRR (2) /* tCK */ 423 424 /*ZQ*/ 425 #define LPDDR2_TZQINIT (1000) /* ns */ 426 #define LPDDR2_TZQCS (90) /* tZQCS, max(6tCK,90ns) */ 427 #define LPDDR2_TZQCL (360) /* tZQCL, max(6tCK,360ns) */ 428 #define LPDDR2_TZQRESET (50) /* ZQreset, max(3tCK,50ns) */ 429 430 /* 431 * Description: depend on input parameter "timing_config", 432 * and calculate all lpddr2 433 * spec timing to "pdram_timing" 434 * parameters: 435 * input: timing_config 436 * output: pdram_timing 437 */ 438 static void lpddr2_get_parameter(struct timing_related_config *timing_config, 439 struct dram_timing_t *pdram_timing) 440 { 441 uint32_t nmhz = timing_config->freq; 442 uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); 443 uint32_t tmp, trp_tmp, trppb_tmp, tras_tmp, twr_tmp, bl_tmp; 444 445 zeromem((void *)pdram_timing, sizeof(struct dram_timing_t)); 446 pdram_timing->mhz = nmhz; 447 pdram_timing->al = 0; 448 pdram_timing->bl = timing_config->bl; 449 450 /* 1066 933 800 667 533 400 333 451 * RL, 8 7 6 5 4 3 3 452 * WL, 4 4 3 2 2 1 1 453 */ 454 if (nmhz <= 266) { 455 pdram_timing->cl = 4; 456 pdram_timing->cwl = 2; 457 pdram_timing->mr[2] = LPDDR2_RL4_WL2; 458 } else if (nmhz <= 333) { 459 pdram_timing->cl = 5; 460 pdram_timing->cwl = 2; 461 pdram_timing->mr[2] = LPDDR2_RL5_WL2; 462 } else if (nmhz <= 400) { 463 pdram_timing->cl = 6; 464 pdram_timing->cwl = 3; 465 pdram_timing->mr[2] = LPDDR2_RL6_WL3; 466 } else if (nmhz <= 466) { 467 pdram_timing->cl = 7; 468 pdram_timing->cwl = 4; 469 pdram_timing->mr[2] = LPDDR2_RL7_WL4; 470 } else { 471 pdram_timing->cl = 8; 472 pdram_timing->cwl = 4; 473 pdram_timing->mr[2] = LPDDR2_RL8_WL4; 474 } 475 switch (timing_config->dramds) { 476 case 120: 477 pdram_timing->mr[3] = LPDDR2_DS_120; 478 break; 479 case 80: 480 pdram_timing->mr[3] = LPDDR2_DS_80; 481 break; 482 case 60: 483 pdram_timing->mr[3] = LPDDR2_DS_60; 484 break; 485 case 48: 486 pdram_timing->mr[3] = LPDDR2_DS_48; 487 break; 488 case 40: 489 pdram_timing->mr[3] = LPDDR2_DS_40; 490 break; 491 case 34: 492 default: 493 pdram_timing->mr[3] = LPDDR2_DS_34; 494 break; 495 } 496 pdram_timing->mr[0] = 0; 497 498 pdram_timing->tinit1 = (LPDDR2_TINIT1 * nmhz + 999) / 1000; 499 pdram_timing->tinit2 = LPDDR2_TINIT2; 500 pdram_timing->tinit3 = (LPDDR2_TINIT3 * nmhz + 999) / 1000; 501 pdram_timing->tinit4 = (LPDDR2_TINIT4 * nmhz + 999) / 1000; 502 pdram_timing->tinit5 = (LPDDR2_TINIT5 * nmhz + 999) / 1000; 503 pdram_timing->trstl = LPDDR2_TRSTL; 504 pdram_timing->trsth = (LPDDR2_TRSTH * nmhz + 999) / 1000; 505 /* 506 * tREFI, average periodic refresh interval, 507 * 15.6us(<256Mb) 7.8us(256Mb-1Gb) 3.9us(2Gb-8Gb) 508 */ 509 if (ddr_capability_per_die >= 0x10000000) 510 pdram_timing->trefi = (LPDDR2_TREFI_3_9_US * nmhz + 999) 511 / 1000; 512 else 513 pdram_timing->trefi = (LPDDR2_TREFI_7_8_US * nmhz + 999) 514 / 1000; 515 /* base timing */ 516 tmp = ((LPDDR2_TRCD * nmhz + 999) / 1000); 517 pdram_timing->trcd = max(3, tmp); 518 /* 519 * tRPpb, max(3tCK, 15ns(Fast) 18ns(Typ) 24ns(Slow), 520 */ 521 trppb_tmp = ((LPDDR2_TRP_PB * nmhz + 999) / 1000); 522 trppb_tmp = max(3, trppb_tmp); 523 pdram_timing->trppb = trppb_tmp; 524 /* 525 * tRPab, max(3tCK, 4-bank:15ns(Fast) 18ns(Typ) 24ns(Slow), 526 * 8-bank:18ns(Fast) 21ns(Typ) 27ns(Slow)) 527 */ 528 trp_tmp = ((LPDDR2_TRP_AB_8_BANK * nmhz + 999) / 1000); 529 trp_tmp = max(3, trp_tmp); 530 pdram_timing->trp = trp_tmp; 531 twr_tmp = ((LPDDR2_TWR * nmhz + 999) / 1000); 532 twr_tmp = max(3, twr_tmp); 533 pdram_timing->twr = twr_tmp; 534 bl_tmp = (pdram_timing->bl == 16) ? LPDDR2_BL16 : 535 ((pdram_timing->bl == 8) ? LPDDR2_BL8 : LPDDR2_BL4); 536 pdram_timing->mr[1] = bl_tmp | LPDDR2_N_WR(twr_tmp); 537 tmp = ((LPDDR2_TRTP * nmhz + (nmhz >> 1) + 999) / 1000); 538 pdram_timing->trtp = max(2, tmp); 539 tras_tmp = ((LPDDR2_TRAS * nmhz + 999) / 1000); 540 tras_tmp = max(3, tras_tmp); 541 pdram_timing->tras_min = tras_tmp; 542 pdram_timing->tras_max = ((LPDDR2_TRAS_MAX * nmhz + 999) / 1000); 543 pdram_timing->trc = (tras_tmp + trp_tmp); 544 tmp = ((LPDDR2_TRRD * nmhz + 999) / 1000); 545 pdram_timing->trrd = max(2, tmp); 546 pdram_timing->tccd = LPDDR2_TCCD; 547 /* tWTR, max(2tCK, 7.5ns(533-266MHz) 10ns(200-166MHz)) */ 548 if (nmhz > 200) 549 tmp = ((LPDDR2_TWTR_GREAT_200MHZ * nmhz + (nmhz >> 1) + 550 999) / 1000); 551 else 552 tmp = ((LPDDR2_TWTR_LITTLE_200MHZ * nmhz + 999) / 1000); 553 pdram_timing->twtr = max(2, tmp); 554 pdram_timing->trtw = LPDDR2_TRTW; 555 if (nmhz <= 200) 556 pdram_timing->tfaw = (LPDDR2_TFAW_LITTLE_200MHZ * nmhz + 999) 557 / 1000; 558 else 559 pdram_timing->tfaw = (LPDDR2_TFAW_GREAT_200MHZ * nmhz + 999) 560 / 1000; 561 /* tRFC, 90ns(<=512Mb) 130ns(1Gb-4Gb) 210ns(8Gb) */ 562 if (ddr_capability_per_die >= 0x40000000) { 563 pdram_timing->trfc = 564 (LPDDR2_TRFC_8GBIT * nmhz + 999) / 1000; 565 tmp = (((LPDDR2_TRFC_8GBIT + 10) * nmhz + 999) / 1000); 566 } else { 567 pdram_timing->trfc = 568 (LPDDR2_TRFC_4GBIT * nmhz + 999) / 1000; 569 tmp = (((LPDDR2_TRFC_4GBIT + 10) * nmhz + 999) / 1000); 570 } 571 if (tmp < 2) 572 tmp = 2; 573 pdram_timing->txsr = tmp; 574 pdram_timing->txsnr = tmp; 575 /* tdqsck use rounded down */ 576 pdram_timing->tdqsck = ((LPDDR2_TDQSCK_MIN * nmhz + (nmhz >> 1)) 577 / 1000); 578 pdram_timing->tdqsck_max = 579 ((LPDDR2_TDQSCK_MAX * nmhz + (nmhz >> 1) + 999) 580 / 1000); 581 /* pd and sr */ 582 tmp = ((LPDDR2_TXP * nmhz + (nmhz >> 1) + 999) / 1000); 583 pdram_timing->txp = max(2, tmp); 584 pdram_timing->txpdll = LPDDR2_TXPDLL; 585 pdram_timing->tdllk = LPDDR2_TDLLK; 586 pdram_timing->tcke = LPDDR2_TCKE; 587 tmp = ((LPDDR2_TCKESR * nmhz + 999) / 1000); 588 pdram_timing->tckesr = max(3, tmp); 589 pdram_timing->tcksre = LPDDR2_TCKSRE; 590 pdram_timing->tcksrx = LPDDR2_TCKSRX; 591 /* mode register timing */ 592 pdram_timing->tmod = LPDDR2_TMOD; 593 pdram_timing->tmrd = LPDDR2_TMRD; 594 pdram_timing->tmrr = LPDDR2_TMRR; 595 /* ZQ */ 596 pdram_timing->tzqinit = (LPDDR2_TZQINIT * nmhz + 999) / 1000; 597 tmp = ((LPDDR2_TZQCS * nmhz + 999) / 1000); 598 pdram_timing->tzqcs = max(6, tmp); 599 tmp = ((LPDDR2_TZQCL * nmhz + 999) / 1000); 600 pdram_timing->tzqoper = max(6, tmp); 601 tmp = ((LPDDR2_TZQRESET * nmhz + 999) / 1000); 602 pdram_timing->tzqreset = max(3, tmp); 603 } 604 605 #define LPDDR3_TINIT1 (100) /* ns */ 606 #define LPDDR3_TINIT2 (5) /* tCK */ 607 #define LPDDR3_TINIT3 (200000) /* 200us */ 608 #define LPDDR3_TINIT4 (1000) /* 1us */ 609 #define LPDDR3_TINIT5 (10000) /* 10us */ 610 #define LPDDR3_TRSTL (0) 611 #define LPDDR3_TRSTH (0) /* 500us */ 612 #define LPDDR3_TREFI_3_9_US (3900) /* 3.9us */ 613 614 /* base timging */ 615 #define LPDDR3_TRCD (18) /* tRCD,15ns(Fast)18ns(Typ)24ns(Slow) */ 616 #define LPDDR3_TRP_PB (18) /* tRPpb, 15ns(Fast) 18ns(Typ) 24ns(Slow) */ 617 #define LPDDR3_TRP_AB (21) /* tRPab, 18ns(Fast) 21ns(Typ) 27ns(Slow) */ 618 #define LPDDR3_TWR (15) /* tWR, max(4tCK,15ns) */ 619 #define LPDDR3_TRTP (7) /* tRTP, max(4tCK, 7.5ns) */ 620 #define LPDDR3_TRRD (10) /* tRRD, max(2tCK,10ns) */ 621 #define LPDDR3_TCCD (4) /* tCK */ 622 #define LPDDR3_TWTR (7) /* tWTR, max(4tCK, 7.5ns) */ 623 #define LPDDR3_TRTW (0) /* tCK register min valid value */ 624 #define LPDDR3_TRAS_MAX (70000) /* 70us */ 625 #define LPDDR3_TRAS (42) /* tRAS, max(3tCK,42ns) */ 626 #define LPDDR3_TFAW (50) /* tFAW,max(8tCK, 50ns) */ 627 #define LPDDR3_TRFC_8GBIT (210) /* tRFC, 130ns(4Gb) 210ns(>4Gb) */ 628 #define LPDDR3_TRFC_4GBIT (130) /* ns */ 629 #define LPDDR3_TDQSCK_MIN (2) /* tDQSCKmin,2.5ns */ 630 #define LPDDR3_TDQSCK_MAX (5) /* tDQSCKmax,5.5ns */ 631 632 /* pd and sr */ 633 #define LPDDR3_TXP (7) /* tXP, max(3tCK,7.5ns) */ 634 #define LPDDR3_TXPDLL (0) 635 #define LPDDR3_TCKE (7) /* tCKE, (max 7.5ns,3 tCK) */ 636 #define LPDDR3_TCKESR (15) /* tCKESR, max(3tCK,15ns) */ 637 #define LPDDR3_TCKSRE (2) /* tCKSRE=tCPDED, 2 tCK */ 638 #define LPDDR3_TCKSRX (2) /* tCKSRX, 2 tCK */ 639 640 /* mode register timing */ 641 #define LPDDR3_TMOD (0) 642 #define LPDDR3_TMRD (14) /* tMRD, (=tMRW), max(14ns, 10 tCK) */ 643 #define LPDDR3_TMRR (4) /* tMRR, 4 tCK */ 644 #define LPDDR3_TMRRI LPDDR3_TRCD 645 646 /* ODT */ 647 #define LPDDR3_TODTON (3) /* 3.5ns */ 648 649 /* ZQ */ 650 #define LPDDR3_TZQINIT (1000) /* 1us */ 651 #define LPDDR3_TZQCS (90) /* tZQCS, 90ns */ 652 #define LPDDR3_TZQCL (360) /* 360ns */ 653 #define LPDDR3_TZQRESET (50) /* ZQreset, max(3tCK,50ns) */ 654 /* write leveling */ 655 #define LPDDR3_TWLMRD (40) /* ns */ 656 #define LPDDR3_TWLO (20) /* ns */ 657 #define LPDDR3_TWLDQSEN (25) /* ns */ 658 /* CA training */ 659 #define LPDDR3_TCACKEL (10) /* tCK */ 660 #define LPDDR3_TCAENT (10) /* tCK */ 661 #define LPDDR3_TCAMRD (20) /* tCK */ 662 #define LPDDR3_TCACKEH (10) /* tCK */ 663 #define LPDDR3_TCAEXT (10) /* tCK */ 664 #define LPDDR3_TADR (20) /* ns */ 665 #define LPDDR3_TMRZ (3) /* ns */ 666 667 /* 668 * Description: depend on input parameter "timing_config", 669 * and calculate all lpddr3 670 * spec timing to "pdram_timing" 671 * parameters: 672 * input: timing_config 673 * output: pdram_timing 674 */ 675 static void lpddr3_get_parameter(struct timing_related_config *timing_config, 676 struct dram_timing_t *pdram_timing) 677 { 678 uint32_t nmhz = timing_config->freq; 679 uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); 680 uint32_t tmp, trp_tmp, trppb_tmp, tras_tmp, twr_tmp, bl_tmp; 681 682 zeromem((void *)pdram_timing, sizeof(struct dram_timing_t)); 683 pdram_timing->mhz = nmhz; 684 pdram_timing->al = 0; 685 pdram_timing->bl = timing_config->bl; 686 687 /* 688 * Only support Write Latency Set A here 689 * 1066 933 800 733 667 600 533 400 166 690 * RL, 16 14 12 11 10 9 8 6 3 691 * WL, 8 8 6 6 6 5 4 3 1 692 */ 693 if (nmhz <= 400) { 694 pdram_timing->cl = 6; 695 pdram_timing->cwl = 3; 696 pdram_timing->mr[2] = LPDDR3_RL6_WL3; 697 } else if (nmhz <= 533) { 698 pdram_timing->cl = 8; 699 pdram_timing->cwl = 4; 700 pdram_timing->mr[2] = LPDDR3_RL8_WL4; 701 } else if (nmhz <= 600) { 702 pdram_timing->cl = 9; 703 pdram_timing->cwl = 5; 704 pdram_timing->mr[2] = LPDDR3_RL9_WL5; 705 } else if (nmhz <= 667) { 706 pdram_timing->cl = 10; 707 pdram_timing->cwl = 6; 708 pdram_timing->mr[2] = LPDDR3_RL10_WL6; 709 } else if (nmhz <= 733) { 710 pdram_timing->cl = 11; 711 pdram_timing->cwl = 6; 712 pdram_timing->mr[2] = LPDDR3_RL11_WL6; 713 } else if (nmhz <= 800) { 714 pdram_timing->cl = 12; 715 pdram_timing->cwl = 6; 716 pdram_timing->mr[2] = LPDDR3_RL12_WL6; 717 } else if (nmhz <= 933) { 718 pdram_timing->cl = 14; 719 pdram_timing->cwl = 8; 720 pdram_timing->mr[2] = LPDDR3_RL14_WL8; 721 } else { 722 pdram_timing->cl = 16; 723 pdram_timing->cwl = 8; 724 pdram_timing->mr[2] = LPDDR3_RL16_WL8; 725 } 726 switch (timing_config->dramds) { 727 case 80: 728 pdram_timing->mr[3] = LPDDR3_DS_80; 729 break; 730 case 60: 731 pdram_timing->mr[3] = LPDDR3_DS_60; 732 break; 733 case 48: 734 pdram_timing->mr[3] = LPDDR3_DS_48; 735 break; 736 case 40: 737 pdram_timing->mr[3] = LPDDR3_DS_40; 738 break; 739 case 3440: 740 pdram_timing->mr[3] = LPDDR3_DS_34D_40U; 741 break; 742 case 4048: 743 pdram_timing->mr[3] = LPDDR3_DS_40D_48U; 744 break; 745 case 3448: 746 pdram_timing->mr[3] = LPDDR3_DS_34D_48U; 747 break; 748 case 34: 749 default: 750 pdram_timing->mr[3] = LPDDR3_DS_34; 751 break; 752 } 753 pdram_timing->mr[0] = 0; 754 switch (timing_config->dramodt) { 755 case 60: 756 pdram_timing->mr11 = LPDDR3_ODT_60; 757 break; 758 case 120: 759 pdram_timing->mr11 = LPDDR3_ODT_120; 760 break; 761 case 240: 762 default: 763 pdram_timing->mr11 = LPDDR3_ODT_240; 764 break; 765 } 766 767 pdram_timing->tinit1 = (LPDDR3_TINIT1 * nmhz + 999) / 1000; 768 pdram_timing->tinit2 = LPDDR3_TINIT2; 769 pdram_timing->tinit3 = (LPDDR3_TINIT3 * nmhz + 999) / 1000; 770 pdram_timing->tinit4 = (LPDDR3_TINIT4 * nmhz + 999) / 1000; 771 pdram_timing->tinit5 = (LPDDR3_TINIT5 * nmhz + 999) / 1000; 772 pdram_timing->trstl = LPDDR3_TRSTL; 773 pdram_timing->trsth = (LPDDR3_TRSTH * nmhz + 999) / 1000; 774 /* tREFI, average periodic refresh interval, 3.9us(4Gb-16Gb) */ 775 pdram_timing->trefi = (LPDDR3_TREFI_3_9_US * nmhz + 999) / 1000; 776 /* base timing */ 777 tmp = ((LPDDR3_TRCD * nmhz + 999) / 1000); 778 pdram_timing->trcd = max(3, tmp); 779 trppb_tmp = ((LPDDR3_TRP_PB * nmhz + 999) / 1000); 780 trppb_tmp = max(3, trppb_tmp); 781 pdram_timing->trppb = trppb_tmp; 782 trp_tmp = ((LPDDR3_TRP_AB * nmhz + 999) / 1000); 783 trp_tmp = max(3, trp_tmp); 784 pdram_timing->trp = trp_tmp; 785 twr_tmp = ((LPDDR3_TWR * nmhz + 999) / 1000); 786 twr_tmp = max(4, twr_tmp); 787 pdram_timing->twr = twr_tmp; 788 if (twr_tmp <= 6) 789 twr_tmp = 6; 790 else if (twr_tmp <= 8) 791 twr_tmp = 8; 792 else if (twr_tmp <= 12) 793 twr_tmp = twr_tmp; 794 else if (twr_tmp <= 14) 795 twr_tmp = 14; 796 else 797 twr_tmp = 16; 798 if (twr_tmp > 9) 799 pdram_timing->mr[2] |= (1 << 4); /*enable nWR > 9*/ 800 twr_tmp = (twr_tmp > 9) ? (twr_tmp - 10) : (twr_tmp - 2); 801 bl_tmp = LPDDR3_BL8; 802 pdram_timing->mr[1] = bl_tmp | LPDDR3_N_WR(twr_tmp); 803 tmp = ((LPDDR3_TRTP * nmhz + (nmhz >> 1) + 999) / 1000); 804 pdram_timing->trtp = max(4, tmp); 805 tras_tmp = ((LPDDR3_TRAS * nmhz + 999) / 1000); 806 tras_tmp = max(3, tras_tmp); 807 pdram_timing->tras_min = tras_tmp; 808 pdram_timing->trc = (tras_tmp + trp_tmp); 809 tmp = ((LPDDR3_TRRD * nmhz + 999) / 1000); 810 pdram_timing->trrd = max(2, tmp); 811 pdram_timing->tccd = LPDDR3_TCCD; 812 tmp = ((LPDDR3_TWTR * nmhz + (nmhz >> 1) + 999) / 1000); 813 pdram_timing->twtr = max(4, tmp); 814 pdram_timing->trtw = ((LPDDR3_TRTW * nmhz + 999) / 1000); 815 pdram_timing->tras_max = ((LPDDR3_TRAS_MAX * nmhz + 999) / 1000); 816 tmp = (LPDDR3_TFAW * nmhz + 999) / 1000; 817 pdram_timing->tfaw = max(8, tmp); 818 if (ddr_capability_per_die > 0x20000000) { 819 pdram_timing->trfc = 820 (LPDDR3_TRFC_8GBIT * nmhz + 999) / 1000; 821 tmp = (((LPDDR3_TRFC_8GBIT + 10) * nmhz + 999) / 1000); 822 } else { 823 pdram_timing->trfc = 824 (LPDDR3_TRFC_4GBIT * nmhz + 999) / 1000; 825 tmp = (((LPDDR3_TRFC_4GBIT + 10) * nmhz + 999) / 1000); 826 } 827 pdram_timing->txsr = max(2, tmp); 828 pdram_timing->txsnr = max(2, tmp); 829 /* tdqsck use rounded down */ 830 pdram_timing->tdqsck = 831 ((LPDDR3_TDQSCK_MIN * nmhz + (nmhz >> 1)) 832 / 1000); 833 pdram_timing->tdqsck_max = 834 ((LPDDR3_TDQSCK_MAX * nmhz + (nmhz >> 1) + 999) 835 / 1000); 836 /*pd and sr*/ 837 tmp = ((LPDDR3_TXP * nmhz + (nmhz >> 1) + 999) / 1000); 838 pdram_timing->txp = max(3, tmp); 839 pdram_timing->txpdll = LPDDR3_TXPDLL; 840 tmp = ((LPDDR3_TCKE * nmhz + (nmhz >> 1) + 999) / 1000); 841 pdram_timing->tcke = max(3, tmp); 842 tmp = ((LPDDR3_TCKESR * nmhz + 999) / 1000); 843 pdram_timing->tckesr = max(3, tmp); 844 pdram_timing->tcksre = LPDDR3_TCKSRE; 845 pdram_timing->tcksrx = LPDDR3_TCKSRX; 846 /*mode register timing*/ 847 pdram_timing->tmod = LPDDR3_TMOD; 848 tmp = ((LPDDR3_TMRD * nmhz + 999) / 1000); 849 pdram_timing->tmrd = max(10, tmp); 850 pdram_timing->tmrr = LPDDR3_TMRR; 851 tmp = ((LPDDR3_TRCD * nmhz + 999) / 1000); 852 pdram_timing->tmrri = max(3, tmp); 853 /* ODT */ 854 pdram_timing->todton = (LPDDR3_TODTON * nmhz + (nmhz >> 1) + 999) 855 / 1000; 856 /* ZQ */ 857 pdram_timing->tzqinit = (LPDDR3_TZQINIT * nmhz + 999) / 1000; 858 pdram_timing->tzqcs = 859 ((LPDDR3_TZQCS * nmhz + 999) / 1000); 860 pdram_timing->tzqoper = 861 ((LPDDR3_TZQCL * nmhz + 999) / 1000); 862 tmp = ((LPDDR3_TZQRESET * nmhz + 999) / 1000); 863 pdram_timing->tzqreset = max(3, tmp); 864 /* write leveling */ 865 pdram_timing->twlmrd = (LPDDR3_TWLMRD * nmhz + 999) / 1000; 866 pdram_timing->twlo = (LPDDR3_TWLO * nmhz + 999) / 1000; 867 pdram_timing->twldqsen = (LPDDR3_TWLDQSEN * nmhz + 999) / 1000; 868 /* CA training */ 869 pdram_timing->tcackel = LPDDR3_TCACKEL; 870 pdram_timing->tcaent = LPDDR3_TCAENT; 871 pdram_timing->tcamrd = LPDDR3_TCAMRD; 872 pdram_timing->tcackeh = LPDDR3_TCACKEH; 873 pdram_timing->tcaext = LPDDR3_TCAEXT; 874 pdram_timing->tadr = (LPDDR3_TADR * nmhz + 999) / 1000; 875 pdram_timing->tmrz = (LPDDR3_TMRZ * nmhz + 999) / 1000; 876 pdram_timing->tcacd = pdram_timing->tadr + 2; 877 } 878 879 #define LPDDR4_TINIT1 (200000) /* 200us */ 880 #define LPDDR4_TINIT2 (10) /* 10ns */ 881 #define LPDDR4_TINIT3 (2000000) /* 2ms */ 882 #define LPDDR4_TINIT4 (5) /* tCK */ 883 #define LPDDR4_TINIT5 (2000) /* 2us */ 884 #define LPDDR4_TRSTL LPDDR4_TINIT1 885 #define LPDDR4_TRSTH LPDDR4_TINIT3 886 #define LPDDR4_TREFI_3_9_US (3900) /* 3.9us */ 887 888 /* base timging */ 889 #define LPDDR4_TRCD (18) /* tRCD, max(18ns,4tCK) */ 890 #define LPDDR4_TRP_PB (18) /* tRPpb, max(18ns, 4tCK) */ 891 #define LPDDR4_TRP_AB (21) /* tRPab, max(21ns, 4tCK) */ 892 #define LPDDR4_TRRD (10) /* tRRD, max(4tCK,10ns) */ 893 #define LPDDR4_TCCD_BL16 (8) /* tCK */ 894 #define LPDDR4_TCCD_BL32 (16) /* tCK */ 895 #define LPDDR4_TWTR (10) /* tWTR, max(8tCK, 10ns) */ 896 #define LPDDR4_TRTW (0) /* tCK register min valid value */ 897 #define LPDDR4_TRAS_MAX (70000) /* 70us */ 898 #define LPDDR4_TRAS (42) /* tRAS, max(3tCK,42ns) */ 899 #define LPDDR4_TFAW (40) /* tFAW,min 40ns) */ 900 #define LPDDR4_TRFC_12GBIT (280) /* tRFC, 280ns(>=12Gb) */ 901 #define LPDDR4_TRFC_6GBIT (180) /* 6Gb/8Gb 180ns */ 902 #define LPDDR4_TRFC_4GBIT (130) /* 4Gb 130ns */ 903 #define LPDDR4_TDQSCK_MIN (1) /* tDQSCKmin,1.5ns */ 904 #define LPDDR4_TDQSCK_MAX (3) /* tDQSCKmax,3.5ns */ 905 #define LPDDR4_TPPD (4) /* tCK */ 906 907 /* pd and sr */ 908 #define LPDDR4_TXP (7) /* tXP, max(5tCK,7.5ns) */ 909 #define LPDDR4_TCKE (7) /* tCKE, max(7.5ns,4 tCK) */ 910 #define LPDDR4_TESCKE (1) /* tESCKE, max(1.75ns, 3tCK) */ 911 #define LPDDR4_TSR (15) /* tSR, max(15ns, 3tCK) */ 912 #define LPDDR4_TCMDCKE (1) /* max(1.75ns, 3tCK) */ 913 #define LPDDR4_TCSCKE (1) /* 1.75ns */ 914 #define LPDDR4_TCKELCS (5) /* max(5ns, 5tCK) */ 915 #define LPDDR4_TCSCKEH (1) /* 1.75ns */ 916 #define LPDDR4_TCKEHCS (7) /* max(7.5ns, 5tCK) */ 917 #define LPDDR4_TMRWCKEL (14) /* max(14ns, 10tCK) */ 918 #define LPDDR4_TCKELCMD (7) /* max(7.5ns, 3tCK) */ 919 #define LPDDR4_TCKEHCMD (7) /* max(7.5ns, 3tCK) */ 920 #define LPDDR4_TCKELPD (7) /* max(7.5ns, 3tCK) */ 921 #define LPDDR4_TCKCKEL (7) /* max(7.5ns, 3tCK) */ 922 923 /* mode register timing */ 924 #define LPDDR4_TMRD (14) /* tMRD, (=tMRW), max(14ns, 10 tCK) */ 925 #define LPDDR4_TMRR (8) /* tMRR, 8 tCK */ 926 927 /* ODT */ 928 #define LPDDR4_TODTON (3) /* 3.5ns */ 929 930 /* ZQ */ 931 #define LPDDR4_TZQCAL (1000) /* 1us */ 932 #define LPDDR4_TZQLAT (30) /* tZQLAT, max(30ns,8tCK) */ 933 #define LPDDR4_TZQRESET (50) /* ZQreset, max(3tCK,50ns) */ 934 #define LPDDR4_TZQCKE (1) /* tZQCKE, max(1.75ns, 3tCK) */ 935 936 /* write leveling */ 937 #define LPDDR4_TWLMRD (40) /* tCK */ 938 #define LPDDR4_TWLO (20) /* ns */ 939 #define LPDDR4_TWLDQSEN (20) /* tCK */ 940 941 /* CA training */ 942 #define LPDDR4_TCAENT (250) /* ns */ 943 #define LPDDR4_TADR (20) /* ns */ 944 #define LPDDR4_TMRZ (1) /* 1.5ns */ 945 #define LPDDR4_TVREF_LONG (250) /* ns */ 946 #define LPDDR4_TVREF_SHORT (100) /* ns */ 947 948 /* VRCG */ 949 #define LPDDR4_TVRCG_ENABLE (200) /* ns */ 950 #define LPDDR4_TVRCG_DISABLE (100) /* ns */ 951 952 /* FSP */ 953 #define LPDDR4_TFC_LONG (250) /* ns */ 954 #define LPDDR4_TCKFSPE (7) /* max(7.5ns, 4tCK) */ 955 #define LPDDR4_TCKFSPX (7) /* max(7.5ns, 4tCK) */ 956 957 /* 958 * Description: depend on input parameter "timing_config", 959 * and calculate all lpddr4 960 * spec timing to "pdram_timing" 961 * parameters: 962 * input: timing_config 963 * output: pdram_timing 964 */ 965 static void lpddr4_get_parameter(struct timing_related_config *timing_config, 966 struct dram_timing_t *pdram_timing) 967 { 968 uint32_t nmhz = timing_config->freq; 969 uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); 970 uint32_t tmp, trp_tmp, trppb_tmp, tras_tmp; 971 972 zeromem((void *)pdram_timing, sizeof(struct dram_timing_t)); 973 pdram_timing->mhz = nmhz; 974 pdram_timing->al = 0; 975 pdram_timing->bl = timing_config->bl; 976 977 /* 978 * Only support Write Latency Set A here 979 * 2133 1866 1600 1333 1066 800 533 266 980 * RL, 36 32 28 24 20 14 10 6 981 * WL, 18 16 14 12 10 8 6 4 982 * nWR, 40 34 30 24 20 16 10 6 983 * nRTP,16 14 12 10 8 8 8 8 984 */ 985 tmp = (timing_config->bl == 32) ? 1 : 0; 986 987 /* 988 * we always use WR preamble = 2tCK 989 * RD preamble = Static 990 */ 991 tmp |= (1 << 2); 992 if (nmhz <= 266) { 993 pdram_timing->cl = 6; 994 pdram_timing->cwl = 4; 995 pdram_timing->twr = 6; 996 pdram_timing->trtp = 8; 997 pdram_timing->mr[2] = LPDDR4_RL6_NRTP8 | LPDDR4_A_WL4; 998 } else if (nmhz <= 533) { 999 if (timing_config->rdbi) { 1000 pdram_timing->cl = 12; 1001 pdram_timing->mr[2] = LPDDR4_RL12_NRTP8 | LPDDR4_A_WL6; 1002 } else { 1003 pdram_timing->cl = 10; 1004 pdram_timing->mr[2] = LPDDR4_RL10_NRTP8 | LPDDR4_A_WL6; 1005 } 1006 pdram_timing->cwl = 6; 1007 pdram_timing->twr = 10; 1008 pdram_timing->trtp = 8; 1009 tmp |= (1 << 4); 1010 } else if (nmhz <= 800) { 1011 if (timing_config->rdbi) { 1012 pdram_timing->cl = 16; 1013 pdram_timing->mr[2] = LPDDR4_RL16_NRTP8 | LPDDR4_A_WL8; 1014 } else { 1015 pdram_timing->cl = 14; 1016 pdram_timing->mr[2] = LPDDR4_RL14_NRTP8 | LPDDR4_A_WL8; 1017 } 1018 pdram_timing->cwl = 8; 1019 pdram_timing->twr = 16; 1020 pdram_timing->trtp = 8; 1021 tmp |= (2 << 4); 1022 } else if (nmhz <= 1066) { 1023 if (timing_config->rdbi) { 1024 pdram_timing->cl = 22; 1025 pdram_timing->mr[2] = LPDDR4_RL22_NRTP8 | LPDDR4_A_WL10; 1026 } else { 1027 pdram_timing->cl = 20; 1028 pdram_timing->mr[2] = LPDDR4_RL20_NRTP8 | LPDDR4_A_WL10; 1029 } 1030 pdram_timing->cwl = 10; 1031 pdram_timing->twr = 20; 1032 pdram_timing->trtp = 8; 1033 tmp |= (3 << 4); 1034 } else if (nmhz <= 1333) { 1035 if (timing_config->rdbi) { 1036 pdram_timing->cl = 28; 1037 pdram_timing->mr[2] = LPDDR4_RL28_NRTP10 | 1038 LPDDR4_A_WL12; 1039 } else { 1040 pdram_timing->cl = 24; 1041 pdram_timing->mr[2] = LPDDR4_RL24_NRTP10 | 1042 LPDDR4_A_WL12; 1043 } 1044 pdram_timing->cwl = 12; 1045 pdram_timing->twr = 24; 1046 pdram_timing->trtp = 10; 1047 tmp |= (4 << 4); 1048 } else if (nmhz <= 1600) { 1049 if (timing_config->rdbi) { 1050 pdram_timing->cl = 32; 1051 pdram_timing->mr[2] = LPDDR4_RL32_NRTP12 | 1052 LPDDR4_A_WL14; 1053 } else { 1054 pdram_timing->cl = 28; 1055 pdram_timing->mr[2] = LPDDR4_RL28_NRTP12 | 1056 LPDDR4_A_WL14; 1057 } 1058 pdram_timing->cwl = 14; 1059 pdram_timing->twr = 30; 1060 pdram_timing->trtp = 12; 1061 tmp |= (5 << 4); 1062 } else if (nmhz <= 1866) { 1063 if (timing_config->rdbi) { 1064 pdram_timing->cl = 36; 1065 pdram_timing->mr[2] = LPDDR4_RL36_NRTP14 | 1066 LPDDR4_A_WL16; 1067 } else { 1068 pdram_timing->cl = 32; 1069 pdram_timing->mr[2] = LPDDR4_RL32_NRTP14 | 1070 LPDDR4_A_WL16; 1071 } 1072 pdram_timing->cwl = 16; 1073 pdram_timing->twr = 34; 1074 pdram_timing->trtp = 14; 1075 tmp |= (6 << 4); 1076 } else { 1077 if (timing_config->rdbi) { 1078 pdram_timing->cl = 40; 1079 pdram_timing->mr[2] = LPDDR4_RL40_NRTP16 | 1080 LPDDR4_A_WL18; 1081 } else { 1082 pdram_timing->cl = 36; 1083 pdram_timing->mr[2] = LPDDR4_RL36_NRTP16 | 1084 LPDDR4_A_WL18; 1085 } 1086 pdram_timing->cwl = 18; 1087 pdram_timing->twr = 40; 1088 pdram_timing->trtp = 16; 1089 tmp |= (7 << 4); 1090 } 1091 pdram_timing->mr[1] = tmp; 1092 tmp = (timing_config->rdbi ? LPDDR4_DBI_RD_EN : 0) | 1093 (timing_config->wdbi ? LPDDR4_DBI_WR_EN : 0); 1094 switch (timing_config->dramds) { 1095 case 240: 1096 pdram_timing->mr[3] = LPDDR4_PDDS_240 | tmp; 1097 break; 1098 case 120: 1099 pdram_timing->mr[3] = LPDDR4_PDDS_120 | tmp; 1100 break; 1101 case 80: 1102 pdram_timing->mr[3] = LPDDR4_PDDS_80 | tmp; 1103 break; 1104 case 60: 1105 pdram_timing->mr[3] = LPDDR4_PDDS_60 | tmp; 1106 break; 1107 case 48: 1108 pdram_timing->mr[3] = LPDDR4_PDDS_48 | tmp; 1109 break; 1110 case 40: 1111 default: 1112 pdram_timing->mr[3] = LPDDR4_PDDS_40 | tmp; 1113 break; 1114 } 1115 pdram_timing->mr[0] = 0; 1116 switch (timing_config->dramodt) { 1117 case 240: 1118 tmp = LPDDR4_DQODT_240; 1119 break; 1120 case 120: 1121 tmp = LPDDR4_DQODT_120; 1122 break; 1123 case 80: 1124 tmp = LPDDR4_DQODT_80; 1125 break; 1126 case 60: 1127 tmp = LPDDR4_DQODT_60; 1128 break; 1129 case 48: 1130 tmp = LPDDR4_DQODT_48; 1131 break; 1132 case 40: 1133 default: 1134 tmp = LPDDR4_DQODT_40; 1135 break; 1136 } 1137 switch (timing_config->caodt) { 1138 case 240: 1139 pdram_timing->mr11 = LPDDR4_CAODT_240 | tmp; 1140 break; 1141 case 120: 1142 pdram_timing->mr11 = LPDDR4_CAODT_120 | tmp; 1143 break; 1144 case 80: 1145 pdram_timing->mr11 = LPDDR4_CAODT_80 | tmp; 1146 break; 1147 case 60: 1148 pdram_timing->mr11 = LPDDR4_CAODT_60 | tmp; 1149 break; 1150 case 48: 1151 pdram_timing->mr11 = LPDDR4_CAODT_48 | tmp; 1152 break; 1153 case 40: 1154 default: 1155 pdram_timing->mr11 = LPDDR4_CAODT_40 | tmp; 1156 break; 1157 } 1158 1159 pdram_timing->tinit1 = (LPDDR4_TINIT1 * nmhz + 999) / 1000; 1160 pdram_timing->tinit2 = (LPDDR4_TINIT2 * nmhz + 999) / 1000; 1161 pdram_timing->tinit3 = (LPDDR4_TINIT3 * nmhz + 999) / 1000; 1162 pdram_timing->tinit4 = (LPDDR4_TINIT4 * nmhz + 999) / 1000; 1163 pdram_timing->tinit5 = (LPDDR4_TINIT5 * nmhz + 999) / 1000; 1164 pdram_timing->trstl = (LPDDR4_TRSTL * nmhz + 999) / 1000; 1165 pdram_timing->trsth = (LPDDR4_TRSTH * nmhz + 999) / 1000; 1166 /* tREFI, average periodic refresh interval, 3.9us(4Gb-16Gb) */ 1167 pdram_timing->trefi = (LPDDR4_TREFI_3_9_US * nmhz + 999) / 1000; 1168 /* base timing */ 1169 tmp = ((LPDDR4_TRCD * nmhz + 999) / 1000); 1170 pdram_timing->trcd = max(4, tmp); 1171 trppb_tmp = ((LPDDR4_TRP_PB * nmhz + 999) / 1000); 1172 trppb_tmp = max(4, trppb_tmp); 1173 pdram_timing->trppb = trppb_tmp; 1174 trp_tmp = ((LPDDR4_TRP_AB * nmhz + 999) / 1000); 1175 trp_tmp = max(4, trp_tmp); 1176 pdram_timing->trp = trp_tmp; 1177 tras_tmp = ((LPDDR4_TRAS * nmhz + 999) / 1000); 1178 tras_tmp = max(3, tras_tmp); 1179 pdram_timing->tras_min = tras_tmp; 1180 pdram_timing->trc = (tras_tmp + trp_tmp); 1181 tmp = ((LPDDR4_TRRD * nmhz + 999) / 1000); 1182 pdram_timing->trrd = max(4, tmp); 1183 if (timing_config->bl == 32) 1184 pdram_timing->tccd = LPDDR4_TCCD_BL16; 1185 else 1186 pdram_timing->tccd = LPDDR4_TCCD_BL32; 1187 pdram_timing->tccdmw = 4 * pdram_timing->tccd; 1188 tmp = ((LPDDR4_TWTR * nmhz + 999) / 1000); 1189 pdram_timing->twtr = max(8, tmp); 1190 pdram_timing->trtw = ((LPDDR4_TRTW * nmhz + 999) / 1000); 1191 pdram_timing->tras_max = ((LPDDR4_TRAS_MAX * nmhz + 999) / 1000); 1192 pdram_timing->tfaw = (LPDDR4_TFAW * nmhz + 999) / 1000; 1193 if (ddr_capability_per_die > 0x60000000) { 1194 /* >= 12Gb */ 1195 pdram_timing->trfc = 1196 (LPDDR4_TRFC_12GBIT * nmhz + 999) / 1000; 1197 tmp = (((LPDDR4_TRFC_12GBIT + 7) * nmhz + (nmhz >> 1) + 1198 999) / 1000); 1199 } else if (ddr_capability_per_die > 0x30000000) { 1200 pdram_timing->trfc = 1201 (LPDDR4_TRFC_6GBIT * nmhz + 999) / 1000; 1202 tmp = (((LPDDR4_TRFC_6GBIT + 7) * nmhz + (nmhz >> 1) + 1203 999) / 1000); 1204 } else { 1205 pdram_timing->trfc = 1206 (LPDDR4_TRFC_4GBIT * nmhz + 999) / 1000; 1207 tmp = (((LPDDR4_TRFC_4GBIT + 7) * nmhz + (nmhz >> 1) + 1208 999) / 1000); 1209 } 1210 pdram_timing->txsr = max(2, tmp); 1211 pdram_timing->txsnr = max(2, tmp); 1212 /* tdqsck use rounded down */ 1213 pdram_timing->tdqsck = ((LPDDR4_TDQSCK_MIN * nmhz + 1214 (nmhz >> 1)) / 1000); 1215 pdram_timing->tdqsck_max = ((LPDDR4_TDQSCK_MAX * nmhz + 1216 (nmhz >> 1) + 999) / 1000); 1217 pdram_timing->tppd = LPDDR4_TPPD; 1218 /* pd and sr */ 1219 tmp = ((LPDDR4_TXP * nmhz + (nmhz >> 1) + 999) / 1000); 1220 pdram_timing->txp = max(5, tmp); 1221 tmp = ((LPDDR4_TCKE * nmhz + (nmhz >> 1) + 999) / 1000); 1222 pdram_timing->tcke = max(4, tmp); 1223 tmp = ((LPDDR4_TESCKE * nmhz + 1224 ((nmhz * 3) / 4) + 1225 999) / 1000); 1226 pdram_timing->tescke = max(3, tmp); 1227 tmp = ((LPDDR4_TSR * nmhz + 999) / 1000); 1228 pdram_timing->tsr = max(3, tmp); 1229 tmp = ((LPDDR4_TCMDCKE * nmhz + 1230 ((nmhz * 3) / 4) + 1231 999) / 1000); 1232 pdram_timing->tcmdcke = max(3, tmp); 1233 pdram_timing->tcscke = ((LPDDR4_TCSCKE * nmhz + 1234 ((nmhz * 3) / 4) + 1235 999) / 1000); 1236 tmp = ((LPDDR4_TCKELCS * nmhz + 999) / 1000); 1237 pdram_timing->tckelcs = max(5, tmp); 1238 pdram_timing->tcsckeh = ((LPDDR4_TCSCKEH * nmhz + 1239 ((nmhz * 3) / 4) + 1240 999) / 1000); 1241 tmp = ((LPDDR4_TCKEHCS * nmhz + 1242 (nmhz >> 1) + 999) / 1000); 1243 pdram_timing->tckehcs = max(5, tmp); 1244 tmp = ((LPDDR4_TMRWCKEL * nmhz + 999) / 1000); 1245 pdram_timing->tmrwckel = max(10, tmp); 1246 tmp = ((LPDDR4_TCKELCMD * nmhz + (nmhz >> 1) + 1247 999) / 1000); 1248 pdram_timing->tckelcmd = max(3, tmp); 1249 tmp = ((LPDDR4_TCKEHCMD * nmhz + (nmhz >> 1) + 1250 999) / 1000); 1251 pdram_timing->tckehcmd = max(3, tmp); 1252 tmp = ((LPDDR4_TCKELPD * nmhz + (nmhz >> 1) + 1253 999) / 1000); 1254 pdram_timing->tckelpd = max(3, tmp); 1255 tmp = ((LPDDR4_TCKCKEL * nmhz + (nmhz >> 1) + 1256 999) / 1000); 1257 pdram_timing->tckckel = max(3, tmp); 1258 /* mode register timing */ 1259 tmp = ((LPDDR4_TMRD * nmhz + 999) / 1000); 1260 pdram_timing->tmrd = max(10, tmp); 1261 pdram_timing->tmrr = LPDDR4_TMRR; 1262 pdram_timing->tmrri = pdram_timing->trcd + 3; 1263 /* ODT */ 1264 pdram_timing->todton = (LPDDR4_TODTON * nmhz + (nmhz >> 1) + 999) 1265 / 1000; 1266 /* ZQ */ 1267 pdram_timing->tzqcal = (LPDDR4_TZQCAL * nmhz + 999) / 1000; 1268 tmp = ((LPDDR4_TZQLAT * nmhz + 999) / 1000); 1269 pdram_timing->tzqlat = max(8, tmp); 1270 tmp = ((LPDDR4_TZQRESET * nmhz + 999) / 1000); 1271 pdram_timing->tzqreset = max(3, tmp); 1272 tmp = ((LPDDR4_TZQCKE * nmhz + 1273 ((nmhz * 3) / 4) + 1274 999) / 1000); 1275 pdram_timing->tzqcke = max(3, tmp); 1276 /* write leveling */ 1277 pdram_timing->twlmrd = LPDDR4_TWLMRD; 1278 pdram_timing->twlo = (LPDDR4_TWLO * nmhz + 999) / 1000; 1279 pdram_timing->twldqsen = LPDDR4_TWLDQSEN; 1280 /* CA training */ 1281 pdram_timing->tcaent = (LPDDR4_TCAENT * nmhz + 999) / 1000; 1282 pdram_timing->tadr = (LPDDR4_TADR * nmhz + 999) / 1000; 1283 pdram_timing->tmrz = (LPDDR4_TMRZ * nmhz + (nmhz >> 1) + 999) / 1000; 1284 pdram_timing->tvref_long = (LPDDR4_TVREF_LONG * nmhz + 999) / 1000; 1285 pdram_timing->tvref_short = (LPDDR4_TVREF_SHORT * nmhz + 999) / 1000; 1286 /* VRCG */ 1287 pdram_timing->tvrcg_enable = (LPDDR4_TVRCG_ENABLE * nmhz + 1288 999) / 1000; 1289 pdram_timing->tvrcg_disable = (LPDDR4_TVRCG_DISABLE * nmhz + 1290 999) / 1000; 1291 /* FSP */ 1292 pdram_timing->tfc_long = (LPDDR4_TFC_LONG * nmhz + 999) / 1000; 1293 tmp = (LPDDR4_TCKFSPE * nmhz + (nmhz >> 1) + 999) / 1000; 1294 pdram_timing->tckfspe = max(4, tmp); 1295 tmp = (LPDDR4_TCKFSPX * nmhz + (nmhz >> 1) + 999) / 1000; 1296 pdram_timing->tckfspx = max(4, tmp); 1297 } 1298 1299 /* 1300 * Description: depend on input parameter "timing_config", 1301 * and calculate correspond "dram_type" 1302 * spec timing to "pdram_timing" 1303 * parameters: 1304 * input: timing_config 1305 * output: pdram_timing 1306 * NOTE: MR ODT is set, need to disable by controller 1307 */ 1308 void dram_get_parameter(struct timing_related_config *timing_config, 1309 struct dram_timing_t *pdram_timing) 1310 { 1311 switch (timing_config->dram_type) { 1312 case DDR3: 1313 ddr3_get_parameter(timing_config, pdram_timing); 1314 break; 1315 case LPDDR2: 1316 lpddr2_get_parameter(timing_config, pdram_timing); 1317 break; 1318 case LPDDR3: 1319 lpddr3_get_parameter(timing_config, pdram_timing); 1320 break; 1321 case LPDDR4: 1322 lpddr4_get_parameter(timing_config, pdram_timing); 1323 break; 1324 } 1325 } 1326