1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <string.h> 32 #include <stdint.h> 33 #include "dram_spec_timing.h" 34 35 static const uint8_t ddr3_cl_cwl[][7] = { 36 /* 37 * speed 0~330 331 ~ 400 401 ~ 533 534~666 667~800 801~933 934~1066 38 * tCK>3 2.5~3 1.875~2.5 1.5~1.875 1.25~1.5 1.07~1.25 0.938~1.07 39 * cl<<4, cwl cl<<4, cwl cl<<4, cwl 40 */ 41 /* DDR3_800D (5-5-5) */ 42 {((5 << 4) | 5), ((5 << 4) | 5), 0, 0, 0, 0, 0}, 43 /* DDR3_800E (6-6-6) */ 44 {((5 << 4) | 5), ((6 << 4) | 5), 0, 0, 0, 0, 0}, 45 /* DDR3_1066E (6-6-6) */ 46 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), 0, 0, 0, 0}, 47 /* DDR3_1066F (7-7-7) */ 48 {((5 << 4) | 5), ((6 << 4) | 5), ((7 << 4) | 6), 0, 0, 0, 0}, 49 /* DDR3_1066G (8-8-8) */ 50 {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), 0, 0, 0, 0}, 51 /* DDR3_1333F (7-7-7) */ 52 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((7 << 4) | 7), 53 0, 0, 0}, 54 /* DDR3_1333G (8-8-8) */ 55 {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((8 << 4) | 7), 56 0, 0, 0}, 57 /* DDR3_1333H (9-9-9) */ 58 {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((9 << 4) | 7), 59 0, 0, 0}, 60 /* DDR3_1333J (10-10-10) */ 61 {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7), 62 0, 0, 0}, 63 /* DDR3_1600G (8-8-8) */ 64 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((7 << 4) | 7), 65 ((8 << 4) | 8), 0, 0}, 66 /* DDR3_1600H (9-9-9) */ 67 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((8 << 4) | 7), 68 ((9 << 4) | 8), 0, 0}, 69 /* DDR3_1600J (10-10-10) */ 70 {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7), 71 ((10 << 4) | 8), 0, 0}, 72 /* DDR3_1600K (11-11-11) */ 73 {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7), 74 ((11 << 4) | 8), 0, 0}, 75 /* DDR3_1866J (10-10-10) */ 76 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((8 << 4) | 7), 77 ((9 << 4) | 8), ((11 << 4) | 9), 0}, 78 /* DDR3_1866K (11-11-11) */ 79 {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((8 << 4) | 7), 80 ((10 << 4) | 8), ((11 << 4) | 9), 0}, 81 /* DDR3_1866L (12-12-12) */ 82 {((6 << 4) | 5), ((6 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7), 83 ((11 << 4) | 8), ((12 << 4) | 9), 0}, 84 /* DDR3_1866M (13-13-13) */ 85 {((6 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7), 86 ((11 << 4) | 8), ((13 << 4) | 9), 0}, 87 /* DDR3_2133K (11-11-11) */ 88 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((7 << 4) | 7), 89 ((9 << 4) | 8), ((10 << 4) | 9), ((11 << 4) | 10)}, 90 /* DDR3_2133L (12-12-12) */ 91 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((8 << 4) | 7), 92 ((9 << 4) | 8), ((11 << 4) | 9), ((12 << 4) | 10)}, 93 /* DDR3_2133M (13-13-13) */ 94 {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7), 95 ((10 << 4) | 8), ((12 << 4) | 9), ((13 << 4) | 10)}, 96 /* DDR3_2133N (14-14-14) */ 97 {((6 << 4) | 5), ((6 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7), 98 ((11 << 4) | 8), ((13 << 4) | 9), ((14 << 4) | 10)}, 99 /* DDR3_DEFAULT */ 100 {((6 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7), 101 ((11 << 4) | 8), ((13 << 4) | 9), ((14 << 4) | 10)} 102 }; 103 104 static const uint16_t ddr3_trc_tfaw[] = { 105 /* tRC tFAW */ 106 ((50 << 8) | 50), /* DDR3_800D (5-5-5) */ 107 ((53 << 8) | 50), /* DDR3_800E (6-6-6) */ 108 109 ((49 << 8) | 50), /* DDR3_1066E (6-6-6) */ 110 ((51 << 8) | 50), /* DDR3_1066F (7-7-7) */ 111 ((53 << 8) | 50), /* DDR3_1066G (8-8-8) */ 112 113 ((47 << 8) | 45), /* DDR3_1333F (7-7-7) */ 114 ((48 << 8) | 45), /* DDR3_1333G (8-8-8) */ 115 ((50 << 8) | 45), /* DDR3_1333H (9-9-9) */ 116 ((51 << 8) | 45), /* DDR3_1333J (10-10-10) */ 117 118 ((45 << 8) | 40), /* DDR3_1600G (8-8-8) */ 119 ((47 << 8) | 40), /* DDR3_1600H (9-9-9)*/ 120 ((48 << 8) | 40), /* DDR3_1600J (10-10-10) */ 121 ((49 << 8) | 40), /* DDR3_1600K (11-11-11) */ 122 123 ((45 << 8) | 35), /* DDR3_1866J (10-10-10) */ 124 ((46 << 8) | 35), /* DDR3_1866K (11-11-11) */ 125 ((47 << 8) | 35), /* DDR3_1866L (12-12-12) */ 126 ((48 << 8) | 35), /* DDR3_1866M (13-13-13) */ 127 128 ((44 << 8) | 35), /* DDR3_2133K (11-11-11) */ 129 ((45 << 8) | 35), /* DDR3_2133L (12-12-12) */ 130 ((46 << 8) | 35), /* DDR3_2133M (13-13-13) */ 131 ((47 << 8) | 35), /* DDR3_2133N (14-14-14) */ 132 133 ((53 << 8) | 50) /* DDR3_DEFAULT */ 134 }; 135 136 static uint32_t get_max_speed_rate(struct timing_related_config *timing_config) 137 { 138 if (timing_config->ch_cnt > 1) 139 return max(timing_config->dram_info[0].speed_rate, 140 timing_config->dram_info[1].speed_rate); 141 else 142 return timing_config->dram_info[0].speed_rate; 143 } 144 145 static uint32_t 146 get_max_die_capability(struct timing_related_config *timing_config) 147 { 148 uint32_t die_cap = 0; 149 uint32_t cs, ch; 150 151 for (ch = 0; ch < timing_config->ch_cnt; ch++) { 152 for (cs = 0; cs < timing_config->dram_info[ch].cs_cnt; cs++) { 153 die_cap = max(die_cap, 154 timing_config-> 155 dram_info[ch].per_die_capability[cs]); 156 } 157 } 158 return die_cap; 159 } 160 161 /* tRSTL, 100ns */ 162 #define DDR3_TRSTL (100) 163 /* trsth, 500us */ 164 #define DDR3_TRSTH (500000) 165 /* trefi, 7.8us */ 166 #define DDR3_TREFI_7_8_US (7800) 167 /* tWR, 15ns */ 168 #define DDR3_TWR (15) 169 /* tRTP, max(4 tCK,7.5ns) */ 170 #define DDR3_TRTP (7) 171 /* tRRD = max(4nCK, 10ns) */ 172 #define DDR3_TRRD (10) 173 /* tCK */ 174 #define DDR3_TCCD (4) 175 /*tWTR, max(4 tCK,7.5ns)*/ 176 #define DDR3_TWTR (7) 177 /* tCK */ 178 #define DDR3_TRTW (0) 179 /* tRAS, 37.5ns(400MHz) 37.5ns(533MHz) */ 180 #define DDR3_TRAS (37) 181 /* ns */ 182 #define DDR3_TRFC_512MBIT (90) 183 /* ns */ 184 #define DDR3_TRFC_1GBIT (110) 185 /* ns */ 186 #define DDR3_TRFC_2GBIT (160) 187 /* ns */ 188 #define DDR3_TRFC_4GBIT (300) 189 /* ns */ 190 #define DDR3_TRFC_8GBIT (350) 191 192 /*pd and sr*/ 193 #define DDR3_TXP (7) /* tXP, max(3 tCK, 7.5ns)( < 933MHz) */ 194 #define DDR3_TXPDLL (24) /* tXPDLL, max(10 tCK, 24ns) */ 195 #define DDR3_TDLLK (512) /* tXSR, tDLLK=512 tCK */ 196 #define DDR3_TCKE_400MHZ (7) /* tCKE, max(3 tCK,7.5ns)(400MHz) */ 197 #define DDR3_TCKE_533MHZ (6) /* tCKE, max(3 tCK,5.625ns)(533MHz) */ 198 #define DDR3_TCKSRE (10) /* tCKSRX, max(5 tCK, 10ns) */ 199 200 /*mode register timing*/ 201 #define DDR3_TMOD (15) /* tMOD, max(12 tCK,15ns) */ 202 #define DDR3_TMRD (4) /* tMRD, 4 tCK */ 203 204 /* ZQ */ 205 #define DDR3_TZQINIT (640) /* tZQinit, max(512 tCK, 640ns) */ 206 #define DDR3_TZQCS (80) /* tZQCS, max(64 tCK, 80ns) */ 207 #define DDR3_TZQOPER (320) /* tZQoper, max(256 tCK, 320ns) */ 208 209 /* Write leveling */ 210 #define DDR3_TWLMRD (40) /* tCK */ 211 #define DDR3_TWLO (9) /* max 7.5ns */ 212 #define DDR3_TWLDQSEN (25) /* tCK */ 213 214 /* 215 * Description: depend on input parameter "timing_config", 216 * and calculate all ddr3 217 * spec timing to "pdram_timing" 218 * parameters: 219 * input: timing_config 220 * output: pdram_timing 221 */ 222 static void ddr3_get_parameter(struct timing_related_config *timing_config, 223 struct dram_timing_t *pdram_timing) 224 { 225 uint32_t nmhz = timing_config->freq; 226 uint32_t ddr_speed_bin = get_max_speed_rate(timing_config); 227 uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); 228 uint32_t tmp; 229 230 memset((void *)pdram_timing, 0, sizeof(struct dram_timing_t)); 231 pdram_timing->mhz = nmhz; 232 pdram_timing->al = 0; 233 pdram_timing->bl = timing_config->bl; 234 if (nmhz <= 330) 235 tmp = 0; 236 else if (nmhz <= 400) 237 tmp = 1; 238 else if (nmhz <= 533) 239 tmp = 2; 240 else if (nmhz <= 666) 241 tmp = 3; 242 else if (nmhz <= 800) 243 tmp = 4; 244 else if (nmhz <= 933) 245 tmp = 5; 246 else 247 tmp = 6; 248 249 /* when dll bypss cl = cwl = 6 */ 250 if (nmhz < 300) { 251 pdram_timing->cl = 6; 252 pdram_timing->cwl = 6; 253 } else { 254 pdram_timing->cl = (ddr3_cl_cwl[ddr_speed_bin][tmp] >> 4) & 0xf; 255 pdram_timing->cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0xf; 256 } 257 258 switch (timing_config->dramds) { 259 case 40: 260 tmp = DDR3_DS_40; 261 break; 262 case 34: 263 default: 264 tmp = DDR3_DS_34; 265 break; 266 } 267 268 switch (timing_config->dramodt) { 269 case 60: 270 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_60; 271 break; 272 case 40: 273 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_40; 274 break; 275 case 120: 276 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_120; 277 break; 278 case 0: 279 default: 280 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_DIS; 281 break; 282 } 283 284 pdram_timing->mr[2] = DDR3_MR2_CWL(pdram_timing->cwl); 285 pdram_timing->mr[3] = 0; 286 287 pdram_timing->trstl = ((DDR3_TRSTL * nmhz + 999) / 1000); 288 pdram_timing->trsth = ((DDR3_TRSTH * nmhz + 999) / 1000); 289 /* tREFI, average periodic refresh interval, 7.8us */ 290 pdram_timing->trefi = ((DDR3_TREFI_7_8_US * nmhz + 999) / 1000); 291 /* base timing */ 292 pdram_timing->trcd = pdram_timing->cl; 293 pdram_timing->trp = pdram_timing->cl; 294 pdram_timing->trppb = pdram_timing->cl; 295 tmp = ((DDR3_TWR * nmhz + 999) / 1000); 296 pdram_timing->twr = tmp; 297 pdram_timing->tdal = tmp + pdram_timing->trp; 298 if (tmp < 9) { 299 tmp = tmp - 4; 300 } else { 301 tmp += (tmp & 0x1) ? 1 : 0; 302 tmp = tmp >> 1; 303 } 304 if (pdram_timing->bl == 4) 305 pdram_timing->mr[0] = DDR3_BC4 306 | DDR3_CL(pdram_timing->cl) 307 | DDR3_WR(tmp); 308 else 309 pdram_timing->mr[0] = DDR3_BL8 310 | DDR3_CL(pdram_timing->cl) 311 | DDR3_WR(tmp); 312 tmp = ((DDR3_TRTP * nmhz + (nmhz >> 1) + 999) / 1000); 313 pdram_timing->trtp = max(4, tmp); 314 pdram_timing->trc = 315 (((ddr3_trc_tfaw[ddr_speed_bin] >> 8) * nmhz + 999) / 1000); 316 tmp = ((DDR3_TRRD * nmhz + 999) / 1000); 317 pdram_timing->trrd = max(4, tmp); 318 pdram_timing->tccd = DDR3_TCCD; 319 tmp = ((DDR3_TWTR * nmhz + (nmhz >> 1) + 999) / 1000); 320 pdram_timing->twtr = max(4, tmp); 321 pdram_timing->trtw = DDR3_TRTW; 322 pdram_timing->tras_max = 9 * pdram_timing->trefi; 323 pdram_timing->tras_min = ((DDR3_TRAS * nmhz + (nmhz >> 1) + 999) 324 / 1000); 325 pdram_timing->tfaw = 326 (((ddr3_trc_tfaw[ddr_speed_bin] & 0x0ff) * nmhz + 999) 327 / 1000); 328 /* tRFC, 90ns(512Mb),110ns(1Gb),160ns(2Gb),300ns(4Gb),350ns(8Gb) */ 329 if (ddr_capability_per_die <= 0x4000000) 330 tmp = DDR3_TRFC_512MBIT; 331 else if (ddr_capability_per_die <= 0x8000000) 332 tmp = DDR3_TRFC_1GBIT; 333 else if (ddr_capability_per_die <= 0x10000000) 334 tmp = DDR3_TRFC_2GBIT; 335 else if (ddr_capability_per_die <= 0x20000000) 336 tmp = DDR3_TRFC_4GBIT; 337 else 338 tmp = DDR3_TRFC_8GBIT; 339 pdram_timing->trfc = (tmp * nmhz + 999) / 1000; 340 pdram_timing->txsnr = max(5, (((tmp + 10) * nmhz + 999) / 1000)); 341 pdram_timing->tdqsck_max = 0; 342 /*pd and sr*/ 343 pdram_timing->txsr = DDR3_TDLLK; 344 tmp = ((DDR3_TXP * nmhz + (nmhz >> 1) + 999) / 1000); 345 pdram_timing->txp = max(3, tmp); 346 tmp = ((DDR3_TXPDLL * nmhz + 999) / 1000); 347 pdram_timing->txpdll = max(10, tmp); 348 pdram_timing->tdllk = DDR3_TDLLK; 349 if (nmhz >= 533) 350 tmp = ((DDR3_TCKE_533MHZ * nmhz + 999) / 1000); 351 else 352 tmp = ((DDR3_TCKE_400MHZ * nmhz + (nmhz >> 1) + 999) / 1000); 353 pdram_timing->tcke = max(3, tmp); 354 pdram_timing->tckesr = (pdram_timing->tcke + 1); 355 tmp = ((DDR3_TCKSRE * nmhz + 999) / 1000); 356 pdram_timing->tcksre = max(5, tmp); 357 pdram_timing->tcksrx = max(5, tmp); 358 /*mode register timing*/ 359 tmp = ((DDR3_TMOD * nmhz + 999) / 1000); 360 pdram_timing->tmod = max(12, tmp); 361 pdram_timing->tmrd = DDR3_TMRD; 362 pdram_timing->tmrr = 0; 363 /*ODT*/ 364 pdram_timing->todton = pdram_timing->cwl - 2; 365 /*ZQ*/ 366 tmp = ((DDR3_TZQINIT * nmhz + 999) / 1000); 367 pdram_timing->tzqinit = max(512, tmp); 368 tmp = ((DDR3_TZQCS * nmhz + 999) / 1000); 369 pdram_timing->tzqcs = max(64, tmp); 370 tmp = ((DDR3_TZQOPER * nmhz + 999) / 1000); 371 pdram_timing->tzqoper = max(256, tmp); 372 /* write leveling */ 373 pdram_timing->twlmrd = DDR3_TWLMRD; 374 pdram_timing->twldqsen = DDR3_TWLDQSEN; 375 pdram_timing->twlo = ((DDR3_TWLO * nmhz + (nmhz >> 1) + 999) / 1000); 376 } 377 378 #define LPDDR2_TINIT1 (100) /* ns */ 379 #define LPDDR2_TINIT2 (5) /* tCK */ 380 #define LPDDR2_TINIT3 (200000) /* 200us */ 381 #define LPDDR2_TINIT4 (1000) /* 1us */ 382 #define LPDDR2_TINIT5 (10000) /* 10us */ 383 #define LPDDR2_TRSTL (0) /* tCK */ 384 #define LPDDR2_TRSTH (500000) /* 500us */ 385 #define LPDDR2_TREFI_3_9_US (3900) /* 3.9us */ 386 #define LPDDR2_TREFI_7_8_US (7800) /* 7.8us */ 387 388 /* base timing */ 389 #define LPDDR2_TRCD (24) /* tRCD,15ns(Fast)18ns(Typ)24ns(Slow) */ 390 #define LPDDR2_TRP_PB (18) /* tRPpb,15ns(Fast)18ns(Typ)24ns(Slow) */ 391 #define LPDDR2_TRP_AB_8_BANK (21) /* tRPab,18ns(Fast)21ns(Typ)27ns(Slow) */ 392 #define LPDDR2_TWR (15) /* tWR, max(3tCK,15ns) */ 393 #define LPDDR2_TRTP (7) /* tRTP, max(2tCK, 7.5ns) */ 394 #define LPDDR2_TRRD (10) /* tRRD, max(2tCK,10ns) */ 395 #define LPDDR2_TCCD (2) /* tCK */ 396 #define LPDDR2_TWTR_GREAT_200MHZ (7) /* ns */ 397 #define LPDDR2_TWTR_LITTLE_200MHZ (10) /* ns */ 398 #define LPDDR2_TRTW (0) /* tCK */ 399 #define LPDDR2_TRAS_MAX (70000) /* 70us */ 400 #define LPDDR2_TRAS (42) /* tRAS, max(3tCK,42ns) */ 401 #define LPDDR2_TFAW_GREAT_200MHZ (50) /* max(8tCK,50ns) */ 402 #define LPDDR2_TFAW_LITTLE_200MHZ (60) /* max(8tCK,60ns) */ 403 #define LPDDR2_TRFC_8GBIT (210) /* ns */ 404 #define LPDDR2_TRFC_4GBIT (130) /* ns */ 405 #define LPDDR2_TDQSCK_MIN (2) /* tDQSCKmin, 2.5ns */ 406 #define LPDDR2_TDQSCK_MAX (5) /* tDQSCKmax, 5.5ns */ 407 408 /*pd and sr*/ 409 #define LPDDR2_TXP (7) /* tXP, max(2tCK,7.5ns) */ 410 #define LPDDR2_TXPDLL (0) 411 #define LPDDR2_TDLLK (0) /* tCK */ 412 #define LPDDR2_TCKE (3) /* tCK */ 413 #define LPDDR2_TCKESR (15) /* tCKESR, max(3tCK,15ns) */ 414 #define LPDDR2_TCKSRE (1) /* tCK */ 415 #define LPDDR2_TCKSRX (2) /* tCK */ 416 417 /*mode register timing*/ 418 #define LPDDR2_TMOD (0) 419 #define LPDDR2_TMRD (5) /* tMRD, (=tMRW), 5 tCK */ 420 #define LPDDR2_TMRR (2) /* tCK */ 421 422 /*ZQ*/ 423 #define LPDDR2_TZQINIT (1000) /* ns */ 424 #define LPDDR2_TZQCS (90) /* tZQCS, max(6tCK,90ns) */ 425 #define LPDDR2_TZQCL (360) /* tZQCL, max(6tCK,360ns) */ 426 #define LPDDR2_TZQRESET (50) /* ZQreset, max(3tCK,50ns) */ 427 428 /* 429 * Description: depend on input parameter "timing_config", 430 * and calculate all lpddr2 431 * spec timing to "pdram_timing" 432 * parameters: 433 * input: timing_config 434 * output: pdram_timing 435 */ 436 static void lpddr2_get_parameter(struct timing_related_config *timing_config, 437 struct dram_timing_t *pdram_timing) 438 { 439 uint32_t nmhz = timing_config->freq; 440 uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); 441 uint32_t tmp, trp_tmp, trppb_tmp, tras_tmp, twr_tmp, bl_tmp; 442 443 memset((void *)pdram_timing, 0, sizeof(struct dram_timing_t)); 444 pdram_timing->mhz = nmhz; 445 pdram_timing->al = 0; 446 pdram_timing->bl = timing_config->bl; 447 448 /* 1066 933 800 667 533 400 333 449 * RL, 8 7 6 5 4 3 3 450 * WL, 4 4 3 2 2 1 1 451 */ 452 if (nmhz <= 266) { 453 pdram_timing->cl = 4; 454 pdram_timing->cwl = 2; 455 pdram_timing->mr[2] = LPDDR2_RL4_WL2; 456 } else if (nmhz <= 333) { 457 pdram_timing->cl = 5; 458 pdram_timing->cwl = 2; 459 pdram_timing->mr[2] = LPDDR2_RL5_WL2; 460 } else if (nmhz <= 400) { 461 pdram_timing->cl = 6; 462 pdram_timing->cwl = 3; 463 pdram_timing->mr[2] = LPDDR2_RL6_WL3; 464 } else if (nmhz <= 466) { 465 pdram_timing->cl = 7; 466 pdram_timing->cwl = 4; 467 pdram_timing->mr[2] = LPDDR2_RL7_WL4; 468 } else { 469 pdram_timing->cl = 8; 470 pdram_timing->cwl = 4; 471 pdram_timing->mr[2] = LPDDR2_RL8_WL4; 472 } 473 switch (timing_config->dramds) { 474 case 120: 475 pdram_timing->mr[3] = LPDDR2_DS_120; 476 break; 477 case 80: 478 pdram_timing->mr[3] = LPDDR2_DS_80; 479 break; 480 case 60: 481 pdram_timing->mr[3] = LPDDR2_DS_60; 482 break; 483 case 48: 484 pdram_timing->mr[3] = LPDDR2_DS_48; 485 break; 486 case 40: 487 pdram_timing->mr[3] = LPDDR2_DS_40; 488 break; 489 case 34: 490 default: 491 pdram_timing->mr[3] = LPDDR2_DS_34; 492 break; 493 } 494 pdram_timing->mr[0] = 0; 495 496 pdram_timing->tinit1 = (LPDDR2_TINIT1 * nmhz + 999) / 1000; 497 pdram_timing->tinit2 = LPDDR2_TINIT2; 498 pdram_timing->tinit3 = (LPDDR2_TINIT3 * nmhz + 999) / 1000; 499 pdram_timing->tinit4 = (LPDDR2_TINIT4 * nmhz + 999) / 1000; 500 pdram_timing->tinit5 = (LPDDR2_TINIT5 * nmhz + 999) / 1000; 501 pdram_timing->trstl = LPDDR2_TRSTL; 502 pdram_timing->trsth = (LPDDR2_TRSTH * nmhz + 999) / 1000; 503 /* 504 * tREFI, average periodic refresh interval, 505 * 15.6us(<256Mb) 7.8us(256Mb-1Gb) 3.9us(2Gb-8Gb) 506 */ 507 if (ddr_capability_per_die >= 0x10000000) 508 pdram_timing->trefi = (LPDDR2_TREFI_3_9_US * nmhz + 999) 509 / 1000; 510 else 511 pdram_timing->trefi = (LPDDR2_TREFI_7_8_US * nmhz + 999) 512 / 1000; 513 /* base timing */ 514 tmp = ((LPDDR2_TRCD * nmhz + 999) / 1000); 515 pdram_timing->trcd = max(3, tmp); 516 /* 517 * tRPpb, max(3tCK, 15ns(Fast) 18ns(Typ) 24ns(Slow), 518 */ 519 trppb_tmp = ((LPDDR2_TRP_PB * nmhz + 999) / 1000); 520 trppb_tmp = max(3, trppb_tmp); 521 pdram_timing->trppb = trppb_tmp; 522 /* 523 * tRPab, max(3tCK, 4-bank:15ns(Fast) 18ns(Typ) 24ns(Slow), 524 * 8-bank:18ns(Fast) 21ns(Typ) 27ns(Slow)) 525 */ 526 trp_tmp = ((LPDDR2_TRP_AB_8_BANK * nmhz + 999) / 1000); 527 trp_tmp = max(3, trp_tmp); 528 pdram_timing->trp = trp_tmp; 529 twr_tmp = ((LPDDR2_TWR * nmhz + 999) / 1000); 530 twr_tmp = max(3, twr_tmp); 531 pdram_timing->twr = twr_tmp; 532 bl_tmp = (pdram_timing->bl == 16) ? LPDDR2_BL16 : 533 ((pdram_timing->bl == 8) ? LPDDR2_BL8 : LPDDR2_BL4); 534 pdram_timing->mr[1] = bl_tmp | LPDDR2_N_WR(twr_tmp); 535 tmp = ((LPDDR2_TRTP * nmhz + (nmhz >> 1) + 999) / 1000); 536 pdram_timing->trtp = max(2, tmp); 537 tras_tmp = ((LPDDR2_TRAS * nmhz + 999) / 1000); 538 tras_tmp = max(3, tras_tmp); 539 pdram_timing->tras_min = tras_tmp; 540 pdram_timing->tras_max = ((LPDDR2_TRAS_MAX * nmhz + 999) / 1000); 541 pdram_timing->trc = (tras_tmp + trp_tmp); 542 tmp = ((LPDDR2_TRRD * nmhz + 999) / 1000); 543 pdram_timing->trrd = max(2, tmp); 544 pdram_timing->tccd = LPDDR2_TCCD; 545 /* tWTR, max(2tCK, 7.5ns(533-266MHz) 10ns(200-166MHz)) */ 546 if (nmhz > 200) 547 tmp = ((LPDDR2_TWTR_GREAT_200MHZ * nmhz + (nmhz >> 1) + 548 999) / 1000); 549 else 550 tmp = ((LPDDR2_TWTR_LITTLE_200MHZ * nmhz + 999) / 1000); 551 pdram_timing->twtr = max(2, tmp); 552 pdram_timing->trtw = LPDDR2_TRTW; 553 if (nmhz <= 200) 554 pdram_timing->tfaw = (LPDDR2_TFAW_LITTLE_200MHZ * nmhz + 999) 555 / 1000; 556 else 557 pdram_timing->tfaw = (LPDDR2_TFAW_GREAT_200MHZ * nmhz + 999) 558 / 1000; 559 /* tRFC, 90ns(<=512Mb) 130ns(1Gb-4Gb) 210ns(8Gb) */ 560 if (ddr_capability_per_die >= 0x40000000) { 561 pdram_timing->trfc = 562 (LPDDR2_TRFC_8GBIT * nmhz + 999) / 1000; 563 tmp = (((LPDDR2_TRFC_8GBIT + 10) * nmhz + 999) / 1000); 564 } else { 565 pdram_timing->trfc = 566 (LPDDR2_TRFC_4GBIT * nmhz + 999) / 1000; 567 tmp = (((LPDDR2_TRFC_4GBIT + 10) * nmhz + 999) / 1000); 568 } 569 if (tmp < 2) 570 tmp = 2; 571 pdram_timing->txsr = tmp; 572 pdram_timing->txsnr = tmp; 573 /* tdqsck use rounded down */ 574 pdram_timing->tdqsck = ((LPDDR2_TDQSCK_MIN * nmhz + (nmhz >> 1)) 575 / 1000); 576 pdram_timing->tdqsck_max = 577 ((LPDDR2_TDQSCK_MAX * nmhz + (nmhz >> 1) + 999) 578 / 1000); 579 /* pd and sr */ 580 tmp = ((LPDDR2_TXP * nmhz + (nmhz >> 1) + 999) / 1000); 581 pdram_timing->txp = max(2, tmp); 582 pdram_timing->txpdll = LPDDR2_TXPDLL; 583 pdram_timing->tdllk = LPDDR2_TDLLK; 584 pdram_timing->tcke = LPDDR2_TCKE; 585 tmp = ((LPDDR2_TCKESR * nmhz + 999) / 1000); 586 pdram_timing->tckesr = max(3, tmp); 587 pdram_timing->tcksre = LPDDR2_TCKSRE; 588 pdram_timing->tcksrx = LPDDR2_TCKSRX; 589 /* mode register timing */ 590 pdram_timing->tmod = LPDDR2_TMOD; 591 pdram_timing->tmrd = LPDDR2_TMRD; 592 pdram_timing->tmrr = LPDDR2_TMRR; 593 /* ZQ */ 594 pdram_timing->tzqinit = (LPDDR2_TZQINIT * nmhz + 999) / 1000; 595 tmp = ((LPDDR2_TZQCS * nmhz + 999) / 1000); 596 pdram_timing->tzqcs = max(6, tmp); 597 tmp = ((LPDDR2_TZQCL * nmhz + 999) / 1000); 598 pdram_timing->tzqoper = max(6, tmp); 599 tmp = ((LPDDR2_TZQRESET * nmhz + 999) / 1000); 600 pdram_timing->tzqreset = max(3, tmp); 601 } 602 603 #define LPDDR3_TINIT1 (100) /* ns */ 604 #define LPDDR3_TINIT2 (5) /* tCK */ 605 #define LPDDR3_TINIT3 (200000) /* 200us */ 606 #define LPDDR3_TINIT4 (1000) /* 1us */ 607 #define LPDDR3_TINIT5 (10000) /* 10us */ 608 #define LPDDR3_TRSTL (0) 609 #define LPDDR3_TRSTH (0) /* 500us */ 610 #define LPDDR3_TREFI_3_9_US (3900) /* 3.9us */ 611 612 /* base timging */ 613 #define LPDDR3_TRCD (18) /* tRCD,15ns(Fast)18ns(Typ)24ns(Slow) */ 614 #define LPDDR3_TRP_PB (18) /* tRPpb, 15ns(Fast) 18ns(Typ) 24ns(Slow) */ 615 #define LPDDR3_TRP_AB (21) /* tRPab, 18ns(Fast) 21ns(Typ) 27ns(Slow) */ 616 #define LPDDR3_TWR (15) /* tWR, max(4tCK,15ns) */ 617 #define LPDDR3_TRTP (7) /* tRTP, max(4tCK, 7.5ns) */ 618 #define LPDDR3_TRRD (10) /* tRRD, max(2tCK,10ns) */ 619 #define LPDDR3_TCCD (4) /* tCK */ 620 #define LPDDR3_TWTR (7) /* tWTR, max(4tCK, 7.5ns) */ 621 #define LPDDR3_TRTW (0) /* tCK register min valid value */ 622 #define LPDDR3_TRAS_MAX (70000) /* 70us */ 623 #define LPDDR3_TRAS (42) /* tRAS, max(3tCK,42ns) */ 624 #define LPDDR3_TFAW (50) /* tFAW,max(8tCK, 50ns) */ 625 #define LPDDR3_TRFC_8GBIT (210) /* tRFC, 130ns(4Gb) 210ns(>4Gb) */ 626 #define LPDDR3_TRFC_4GBIT (130) /* ns */ 627 #define LPDDR3_TDQSCK_MIN (2) /* tDQSCKmin,2.5ns */ 628 #define LPDDR3_TDQSCK_MAX (5) /* tDQSCKmax,5.5ns */ 629 630 /* pd and sr */ 631 #define LPDDR3_TXP (7) /* tXP, max(3tCK,7.5ns) */ 632 #define LPDDR3_TXPDLL (0) 633 #define LPDDR3_TCKE (7) /* tCKE, (max 7.5ns,3 tCK) */ 634 #define LPDDR3_TCKESR (15) /* tCKESR, max(3tCK,15ns) */ 635 #define LPDDR3_TCKSRE (2) /* tCKSRE=tCPDED, 2 tCK */ 636 #define LPDDR3_TCKSRX (2) /* tCKSRX, 2 tCK */ 637 638 /* mode register timing */ 639 #define LPDDR3_TMOD (0) 640 #define LPDDR3_TMRD (14) /* tMRD, (=tMRW), max(14ns, 10 tCK) */ 641 #define LPDDR3_TMRR (4) /* tMRR, 4 tCK */ 642 #define LPDDR3_TMRRI LPDDR3_TRCD 643 644 /* ODT */ 645 #define LPDDR3_TODTON (3) /* 3.5ns */ 646 647 /* ZQ */ 648 #define LPDDR3_TZQINIT (1000) /* 1us */ 649 #define LPDDR3_TZQCS (90) /* tZQCS, 90ns */ 650 #define LPDDR3_TZQCL (360) /* 360ns */ 651 #define LPDDR3_TZQRESET (50) /* ZQreset, max(3tCK,50ns) */ 652 /* write leveling */ 653 #define LPDDR3_TWLMRD (40) /* ns */ 654 #define LPDDR3_TWLO (20) /* ns */ 655 #define LPDDR3_TWLDQSEN (25) /* ns */ 656 /* CA training */ 657 #define LPDDR3_TCACKEL (10) /* tCK */ 658 #define LPDDR3_TCAENT (10) /* tCK */ 659 #define LPDDR3_TCAMRD (20) /* tCK */ 660 #define LPDDR3_TCACKEH (10) /* tCK */ 661 #define LPDDR3_TCAEXT (10) /* tCK */ 662 #define LPDDR3_TADR (20) /* ns */ 663 #define LPDDR3_TMRZ (3) /* ns */ 664 665 /* 666 * Description: depend on input parameter "timing_config", 667 * and calculate all lpddr3 668 * spec timing to "pdram_timing" 669 * parameters: 670 * input: timing_config 671 * output: pdram_timing 672 */ 673 static void lpddr3_get_parameter(struct timing_related_config *timing_config, 674 struct dram_timing_t *pdram_timing) 675 { 676 uint32_t nmhz = timing_config->freq; 677 uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); 678 uint32_t tmp, trp_tmp, trppb_tmp, tras_tmp, twr_tmp, bl_tmp; 679 680 memset((void *)pdram_timing, 0, sizeof(struct dram_timing_t)); 681 pdram_timing->mhz = nmhz; 682 pdram_timing->al = 0; 683 pdram_timing->bl = timing_config->bl; 684 685 /* 686 * Only support Write Latency Set A here 687 * 1066 933 800 733 667 600 533 400 166 688 * RL, 16 14 12 11 10 9 8 6 3 689 * WL, 8 8 6 6 6 5 4 3 1 690 */ 691 if (nmhz <= 400) { 692 pdram_timing->cl = 6; 693 pdram_timing->cwl = 3; 694 pdram_timing->mr[2] = LPDDR3_RL6_WL3; 695 } else if (nmhz <= 533) { 696 pdram_timing->cl = 8; 697 pdram_timing->cwl = 4; 698 pdram_timing->mr[2] = LPDDR3_RL8_WL4; 699 } else if (nmhz <= 600) { 700 pdram_timing->cl = 9; 701 pdram_timing->cwl = 5; 702 pdram_timing->mr[2] = LPDDR3_RL9_WL5; 703 } else if (nmhz <= 667) { 704 pdram_timing->cl = 10; 705 pdram_timing->cwl = 6; 706 pdram_timing->mr[2] = LPDDR3_RL10_WL6; 707 } else if (nmhz <= 733) { 708 pdram_timing->cl = 11; 709 pdram_timing->cwl = 6; 710 pdram_timing->mr[2] = LPDDR3_RL11_WL6; 711 } else if (nmhz <= 800) { 712 pdram_timing->cl = 12; 713 pdram_timing->cwl = 6; 714 pdram_timing->mr[2] = LPDDR3_RL12_WL6; 715 } else if (nmhz <= 933) { 716 pdram_timing->cl = 14; 717 pdram_timing->cwl = 8; 718 pdram_timing->mr[2] = LPDDR3_RL14_WL8; 719 } else { 720 pdram_timing->cl = 16; 721 pdram_timing->cwl = 8; 722 pdram_timing->mr[2] = LPDDR3_RL16_WL8; 723 } 724 switch (timing_config->dramds) { 725 case 80: 726 pdram_timing->mr[3] = LPDDR3_DS_80; 727 break; 728 case 60: 729 pdram_timing->mr[3] = LPDDR3_DS_60; 730 break; 731 case 48: 732 pdram_timing->mr[3] = LPDDR3_DS_48; 733 break; 734 case 40: 735 pdram_timing->mr[3] = LPDDR3_DS_40; 736 break; 737 case 3440: 738 pdram_timing->mr[3] = LPDDR3_DS_34D_40U; 739 break; 740 case 4048: 741 pdram_timing->mr[3] = LPDDR3_DS_40D_48U; 742 break; 743 case 3448: 744 pdram_timing->mr[3] = LPDDR3_DS_34D_48U; 745 break; 746 case 34: 747 default: 748 pdram_timing->mr[3] = LPDDR3_DS_34; 749 break; 750 } 751 pdram_timing->mr[0] = 0; 752 switch (timing_config->dramodt) { 753 case 60: 754 pdram_timing->mr11 = LPDDR3_ODT_60; 755 break; 756 case 120: 757 pdram_timing->mr11 = LPDDR3_ODT_120; 758 break; 759 case 240: 760 default: 761 pdram_timing->mr11 = LPDDR3_ODT_240; 762 break; 763 } 764 765 pdram_timing->tinit1 = (LPDDR3_TINIT1 * nmhz + 999) / 1000; 766 pdram_timing->tinit2 = LPDDR3_TINIT2; 767 pdram_timing->tinit3 = (LPDDR3_TINIT3 * nmhz + 999) / 1000; 768 pdram_timing->tinit4 = (LPDDR3_TINIT4 * nmhz + 999) / 1000; 769 pdram_timing->tinit5 = (LPDDR3_TINIT5 * nmhz + 999) / 1000; 770 pdram_timing->trstl = LPDDR3_TRSTL; 771 pdram_timing->trsth = (LPDDR3_TRSTH * nmhz + 999) / 1000; 772 /* tREFI, average periodic refresh interval, 3.9us(4Gb-16Gb) */ 773 pdram_timing->trefi = (LPDDR3_TREFI_3_9_US * nmhz + 999) / 1000; 774 /* base timing */ 775 tmp = ((LPDDR3_TRCD * nmhz + 999) / 1000); 776 pdram_timing->trcd = max(3, tmp); 777 trppb_tmp = ((LPDDR3_TRP_PB * nmhz + 999) / 1000); 778 trppb_tmp = max(3, trppb_tmp); 779 pdram_timing->trppb = trppb_tmp; 780 trp_tmp = ((LPDDR3_TRP_AB * nmhz + 999) / 1000); 781 trp_tmp = max(3, trp_tmp); 782 pdram_timing->trp = trp_tmp; 783 twr_tmp = ((LPDDR3_TWR * nmhz + 999) / 1000); 784 twr_tmp = max(4, twr_tmp); 785 pdram_timing->twr = twr_tmp; 786 if (twr_tmp <= 6) 787 twr_tmp = 6; 788 else if (twr_tmp <= 8) 789 twr_tmp = 8; 790 else if (twr_tmp <= 12) 791 twr_tmp = twr_tmp; 792 else if (twr_tmp <= 14) 793 twr_tmp = 14; 794 else 795 twr_tmp = 16; 796 if (twr_tmp > 9) 797 pdram_timing->mr[2] |= (1 << 4); /*enable nWR > 9*/ 798 twr_tmp = (twr_tmp > 9) ? (twr_tmp - 10) : (twr_tmp - 2); 799 bl_tmp = LPDDR3_BL8; 800 pdram_timing->mr[1] = bl_tmp | LPDDR3_N_WR(twr_tmp); 801 tmp = ((LPDDR3_TRTP * nmhz + (nmhz >> 1) + 999) / 1000); 802 pdram_timing->trtp = max(4, tmp); 803 tras_tmp = ((LPDDR3_TRAS * nmhz + 999) / 1000); 804 tras_tmp = max(3, tras_tmp); 805 pdram_timing->tras_min = tras_tmp; 806 pdram_timing->trc = (tras_tmp + trp_tmp); 807 tmp = ((LPDDR3_TRRD * nmhz + 999) / 1000); 808 pdram_timing->trrd = max(2, tmp); 809 pdram_timing->tccd = LPDDR3_TCCD; 810 tmp = ((LPDDR3_TWTR * nmhz + (nmhz >> 1) + 999) / 1000); 811 pdram_timing->twtr = max(4, tmp); 812 pdram_timing->trtw = ((LPDDR3_TRTW * nmhz + 999) / 1000); 813 pdram_timing->tras_max = ((LPDDR3_TRAS_MAX * nmhz + 999) / 1000); 814 tmp = (LPDDR3_TFAW * nmhz + 999) / 1000; 815 pdram_timing->tfaw = max(8, tmp); 816 if (ddr_capability_per_die > 0x20000000) { 817 pdram_timing->trfc = 818 (LPDDR3_TRFC_8GBIT * nmhz + 999) / 1000; 819 tmp = (((LPDDR3_TRFC_8GBIT + 10) * nmhz + 999) / 1000); 820 } else { 821 pdram_timing->trfc = 822 (LPDDR3_TRFC_4GBIT * nmhz + 999) / 1000; 823 tmp = (((LPDDR3_TRFC_4GBIT + 10) * nmhz + 999) / 1000); 824 } 825 pdram_timing->txsr = max(2, tmp); 826 pdram_timing->txsnr = max(2, tmp); 827 /* tdqsck use rounded down */ 828 pdram_timing->tdqsck = 829 ((LPDDR3_TDQSCK_MIN * nmhz + (nmhz >> 1)) 830 / 1000); 831 pdram_timing->tdqsck_max = 832 ((LPDDR3_TDQSCK_MAX * nmhz + (nmhz >> 1) + 999) 833 / 1000); 834 /*pd and sr*/ 835 tmp = ((LPDDR3_TXP * nmhz + (nmhz >> 1) + 999) / 1000); 836 pdram_timing->txp = max(3, tmp); 837 pdram_timing->txpdll = LPDDR3_TXPDLL; 838 tmp = ((LPDDR3_TCKE * nmhz + (nmhz >> 1) + 999) / 1000); 839 pdram_timing->tcke = max(3, tmp); 840 tmp = ((LPDDR3_TCKESR * nmhz + 999) / 1000); 841 pdram_timing->tckesr = max(3, tmp); 842 pdram_timing->tcksre = LPDDR3_TCKSRE; 843 pdram_timing->tcksrx = LPDDR3_TCKSRX; 844 /*mode register timing*/ 845 pdram_timing->tmod = LPDDR3_TMOD; 846 tmp = ((LPDDR3_TMRD * nmhz + 999) / 1000); 847 pdram_timing->tmrd = max(10, tmp); 848 pdram_timing->tmrr = LPDDR3_TMRR; 849 tmp = ((LPDDR3_TRCD * nmhz + 999) / 1000); 850 pdram_timing->tmrri = max(3, tmp); 851 /* ODT */ 852 pdram_timing->todton = (LPDDR3_TODTON * nmhz + (nmhz >> 1) + 999) 853 / 1000; 854 /* ZQ */ 855 pdram_timing->tzqinit = (LPDDR3_TZQINIT * nmhz + 999) / 1000; 856 pdram_timing->tzqcs = 857 ((LPDDR3_TZQCS * nmhz + 999) / 1000); 858 pdram_timing->tzqoper = 859 ((LPDDR3_TZQCL * nmhz + 999) / 1000); 860 tmp = ((LPDDR3_TZQRESET * nmhz + 999) / 1000); 861 pdram_timing->tzqreset = max(3, tmp); 862 /* write leveling */ 863 pdram_timing->twlmrd = (LPDDR3_TWLMRD * nmhz + 999) / 1000; 864 pdram_timing->twlo = (LPDDR3_TWLO * nmhz + 999) / 1000; 865 pdram_timing->twldqsen = (LPDDR3_TWLDQSEN * nmhz + 999) / 1000; 866 /* CA training */ 867 pdram_timing->tcackel = LPDDR3_TCACKEL; 868 pdram_timing->tcaent = LPDDR3_TCAENT; 869 pdram_timing->tcamrd = LPDDR3_TCAMRD; 870 pdram_timing->tcackeh = LPDDR3_TCACKEH; 871 pdram_timing->tcaext = LPDDR3_TCAEXT; 872 pdram_timing->tadr = (LPDDR3_TADR * nmhz + 999) / 1000; 873 pdram_timing->tmrz = (LPDDR3_TMRZ * nmhz + 999) / 1000; 874 pdram_timing->tcacd = pdram_timing->tadr + 2; 875 } 876 877 #define LPDDR4_TINIT1 (200000) /* 200us */ 878 #define LPDDR4_TINIT2 (10) /* 10ns */ 879 #define LPDDR4_TINIT3 (2000000) /* 2ms */ 880 #define LPDDR4_TINIT4 (5) /* tCK */ 881 #define LPDDR4_TINIT5 (2000) /* 2us */ 882 #define LPDDR4_TRSTL LPDDR4_TINIT1 883 #define LPDDR4_TRSTH LPDDR4_TINIT3 884 #define LPDDR4_TREFI_3_9_US (3900) /* 3.9us */ 885 886 /* base timging */ 887 #define LPDDR4_TRCD (18) /* tRCD, max(18ns,4tCK) */ 888 #define LPDDR4_TRP_PB (18) /* tRPpb, max(18ns, 4tCK) */ 889 #define LPDDR4_TRP_AB (21) /* tRPab, max(21ns, 4tCK) */ 890 #define LPDDR4_TRRD (10) /* tRRD, max(4tCK,10ns) */ 891 #define LPDDR4_TCCD_BL16 (8) /* tCK */ 892 #define LPDDR4_TCCD_BL32 (16) /* tCK */ 893 #define LPDDR4_TWTR (10) /* tWTR, max(8tCK, 10ns) */ 894 #define LPDDR4_TRTW (0) /* tCK register min valid value */ 895 #define LPDDR4_TRAS_MAX (70000) /* 70us */ 896 #define LPDDR4_TRAS (42) /* tRAS, max(3tCK,42ns) */ 897 #define LPDDR4_TFAW (40) /* tFAW,min 40ns) */ 898 #define LPDDR4_TRFC_12GBIT (280) /* tRFC, 280ns(>=12Gb) */ 899 #define LPDDR4_TRFC_6GBIT (180) /* 6Gb/8Gb 180ns */ 900 #define LPDDR4_TRFC_4GBIT (130) /* 4Gb 130ns */ 901 #define LPDDR4_TDQSCK_MIN (1) /* tDQSCKmin,1.5ns */ 902 #define LPDDR4_TDQSCK_MAX (3) /* tDQSCKmax,3.5ns */ 903 #define LPDDR4_TPPD (4) /* tCK */ 904 905 /* pd and sr */ 906 #define LPDDR4_TXP (7) /* tXP, max(5tCK,7.5ns) */ 907 #define LPDDR4_TCKE (7) /* tCKE, max(7.5ns,4 tCK) */ 908 #define LPDDR4_TESCKE (1) /* tESCKE, max(1.75ns, 3tCK) */ 909 #define LPDDR4_TSR (15) /* tSR, max(15ns, 3tCK) */ 910 #define LPDDR4_TCMDCKE (1) /* max(1.75ns, 3tCK) */ 911 #define LPDDR4_TCSCKE (1) /* 1.75ns */ 912 #define LPDDR4_TCKELCS (5) /* max(5ns, 5tCK) */ 913 #define LPDDR4_TCSCKEH (1) /* 1.75ns */ 914 #define LPDDR4_TCKEHCS (7) /* max(7.5ns, 5tCK) */ 915 #define LPDDR4_TMRWCKEL (14) /* max(14ns, 10tCK) */ 916 #define LPDDR4_TCKELCMD (7) /* max(7.5ns, 3tCK) */ 917 #define LPDDR4_TCKEHCMD (7) /* max(7.5ns, 3tCK) */ 918 #define LPDDR4_TCKELPD (7) /* max(7.5ns, 3tCK) */ 919 #define LPDDR4_TCKCKEL (7) /* max(7.5ns, 3tCK) */ 920 921 /* mode register timing */ 922 #define LPDDR4_TMRD (14) /* tMRD, (=tMRW), max(14ns, 10 tCK) */ 923 #define LPDDR4_TMRR (8) /* tMRR, 8 tCK */ 924 925 /* ODT */ 926 #define LPDDR4_TODTON (3) /* 3.5ns */ 927 928 /* ZQ */ 929 #define LPDDR4_TZQCAL (1000) /* 1us */ 930 #define LPDDR4_TZQLAT (30) /* tZQLAT, max(30ns,8tCK) */ 931 #define LPDDR4_TZQRESET (50) /* ZQreset, max(3tCK,50ns) */ 932 #define LPDDR4_TZQCKE (1) /* tZQCKE, max(1.75ns, 3tCK) */ 933 934 /* write leveling */ 935 #define LPDDR4_TWLMRD (40) /* tCK */ 936 #define LPDDR4_TWLO (20) /* ns */ 937 #define LPDDR4_TWLDQSEN (20) /* tCK */ 938 939 /* CA training */ 940 #define LPDDR4_TCAENT (250) /* ns */ 941 #define LPDDR4_TADR (20) /* ns */ 942 #define LPDDR4_TMRZ (1) /* 1.5ns */ 943 #define LPDDR4_TVREF_LONG (250) /* ns */ 944 #define LPDDR4_TVREF_SHORT (100) /* ns */ 945 946 /* VRCG */ 947 #define LPDDR4_TVRCG_ENABLE (200) /* ns */ 948 #define LPDDR4_TVRCG_DISABLE (100) /* ns */ 949 950 /* FSP */ 951 #define LPDDR4_TFC_LONG (250) /* ns */ 952 #define LPDDR4_TCKFSPE (7) /* max(7.5ns, 4tCK) */ 953 #define LPDDR4_TCKFSPX (7) /* max(7.5ns, 4tCK) */ 954 955 /* 956 * Description: depend on input parameter "timing_config", 957 * and calculate all lpddr4 958 * spec timing to "pdram_timing" 959 * parameters: 960 * input: timing_config 961 * output: pdram_timing 962 */ 963 static void lpddr4_get_parameter(struct timing_related_config *timing_config, 964 struct dram_timing_t *pdram_timing) 965 { 966 uint32_t nmhz = timing_config->freq; 967 uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); 968 uint32_t tmp, trp_tmp, trppb_tmp, tras_tmp; 969 970 memset((void *)pdram_timing, 0, sizeof(struct dram_timing_t)); 971 pdram_timing->mhz = nmhz; 972 pdram_timing->al = 0; 973 pdram_timing->bl = timing_config->bl; 974 975 /* 976 * Only support Write Latency Set A here 977 * 2133 1866 1600 1333 1066 800 533 266 978 * RL, 36 32 28 24 20 14 10 6 979 * WL, 18 16 14 12 10 8 6 4 980 * nWR, 40 34 30 24 20 16 10 6 981 * nRTP,16 14 12 10 8 8 8 8 982 */ 983 tmp = (timing_config->bl == 32) ? 1 : 0; 984 985 /* 986 * we always use WR preamble = 2tCK 987 * RD preamble = Static 988 */ 989 tmp |= (1 << 2); 990 if (nmhz <= 266) { 991 pdram_timing->cl = 6; 992 pdram_timing->cwl = 4; 993 pdram_timing->twr = 6; 994 pdram_timing->trtp = 8; 995 pdram_timing->mr[2] = LPDDR4_RL6_NRTP8 | LPDDR4_A_WL4; 996 } else if (nmhz <= 533) { 997 if (timing_config->rdbi) { 998 pdram_timing->cl = 12; 999 pdram_timing->mr[2] = LPDDR4_RL12_NRTP8 | LPDDR4_A_WL6; 1000 } else { 1001 pdram_timing->cl = 10; 1002 pdram_timing->mr[2] = LPDDR4_RL10_NRTP8 | LPDDR4_A_WL6; 1003 } 1004 pdram_timing->cwl = 6; 1005 pdram_timing->twr = 10; 1006 pdram_timing->trtp = 8; 1007 tmp |= (1 << 4); 1008 } else if (nmhz <= 800) { 1009 if (timing_config->rdbi) { 1010 pdram_timing->cl = 16; 1011 pdram_timing->mr[2] = LPDDR4_RL16_NRTP8 | LPDDR4_A_WL8; 1012 } else { 1013 pdram_timing->cl = 14; 1014 pdram_timing->mr[2] = LPDDR4_RL14_NRTP8 | LPDDR4_A_WL8; 1015 } 1016 pdram_timing->cwl = 8; 1017 pdram_timing->twr = 16; 1018 pdram_timing->trtp = 8; 1019 tmp |= (2 << 4); 1020 } else if (nmhz <= 1066) { 1021 if (timing_config->rdbi) { 1022 pdram_timing->cl = 22; 1023 pdram_timing->mr[2] = LPDDR4_RL22_NRTP8 | LPDDR4_A_WL10; 1024 } else { 1025 pdram_timing->cl = 20; 1026 pdram_timing->mr[2] = LPDDR4_RL20_NRTP8 | LPDDR4_A_WL10; 1027 } 1028 pdram_timing->cwl = 10; 1029 pdram_timing->twr = 20; 1030 pdram_timing->trtp = 8; 1031 tmp |= (3 << 4); 1032 } else if (nmhz <= 1333) { 1033 if (timing_config->rdbi) { 1034 pdram_timing->cl = 28; 1035 pdram_timing->mr[2] = LPDDR4_RL28_NRTP10 | 1036 LPDDR4_A_WL12; 1037 } else { 1038 pdram_timing->cl = 24; 1039 pdram_timing->mr[2] = LPDDR4_RL24_NRTP10 | 1040 LPDDR4_A_WL12; 1041 } 1042 pdram_timing->cwl = 12; 1043 pdram_timing->twr = 24; 1044 pdram_timing->trtp = 10; 1045 tmp |= (4 << 4); 1046 } else if (nmhz <= 1600) { 1047 if (timing_config->rdbi) { 1048 pdram_timing->cl = 32; 1049 pdram_timing->mr[2] = LPDDR4_RL32_NRTP12 | 1050 LPDDR4_A_WL14; 1051 } else { 1052 pdram_timing->cl = 28; 1053 pdram_timing->mr[2] = LPDDR4_RL28_NRTP12 | 1054 LPDDR4_A_WL14; 1055 } 1056 pdram_timing->cwl = 14; 1057 pdram_timing->twr = 30; 1058 pdram_timing->trtp = 12; 1059 tmp |= (5 << 4); 1060 } else if (nmhz <= 1866) { 1061 if (timing_config->rdbi) { 1062 pdram_timing->cl = 36; 1063 pdram_timing->mr[2] = LPDDR4_RL36_NRTP14 | 1064 LPDDR4_A_WL16; 1065 } else { 1066 pdram_timing->cl = 32; 1067 pdram_timing->mr[2] = LPDDR4_RL32_NRTP14 | 1068 LPDDR4_A_WL16; 1069 } 1070 pdram_timing->cwl = 16; 1071 pdram_timing->twr = 34; 1072 pdram_timing->trtp = 14; 1073 tmp |= (6 << 4); 1074 } else { 1075 if (timing_config->rdbi) { 1076 pdram_timing->cl = 40; 1077 pdram_timing->mr[2] = LPDDR4_RL40_NRTP16 | 1078 LPDDR4_A_WL18; 1079 } else { 1080 pdram_timing->cl = 36; 1081 pdram_timing->mr[2] = LPDDR4_RL36_NRTP16 | 1082 LPDDR4_A_WL18; 1083 } 1084 pdram_timing->cwl = 18; 1085 pdram_timing->twr = 40; 1086 pdram_timing->trtp = 16; 1087 tmp |= (7 << 4); 1088 } 1089 pdram_timing->mr[1] = tmp; 1090 tmp = (timing_config->rdbi ? LPDDR4_DBI_RD_EN : 0) | 1091 (timing_config->wdbi ? LPDDR4_DBI_WR_EN : 0); 1092 switch (timing_config->dramds) { 1093 case 240: 1094 pdram_timing->mr[3] = LPDDR4_PDDS_240 | tmp; 1095 break; 1096 case 120: 1097 pdram_timing->mr[3] = LPDDR4_PDDS_120 | tmp; 1098 break; 1099 case 80: 1100 pdram_timing->mr[3] = LPDDR4_PDDS_80 | tmp; 1101 break; 1102 case 60: 1103 pdram_timing->mr[3] = LPDDR4_PDDS_60 | tmp; 1104 break; 1105 case 48: 1106 pdram_timing->mr[3] = LPDDR4_PDDS_48 | tmp; 1107 break; 1108 case 40: 1109 default: 1110 pdram_timing->mr[3] = LPDDR4_PDDS_40 | tmp; 1111 break; 1112 } 1113 pdram_timing->mr[0] = 0; 1114 switch (timing_config->dramodt) { 1115 case 240: 1116 tmp = LPDDR4_DQODT_240; 1117 break; 1118 case 120: 1119 tmp = LPDDR4_DQODT_120; 1120 break; 1121 case 80: 1122 tmp = LPDDR4_DQODT_80; 1123 break; 1124 case 60: 1125 tmp = LPDDR4_DQODT_60; 1126 break; 1127 case 48: 1128 tmp = LPDDR4_DQODT_48; 1129 break; 1130 case 40: 1131 default: 1132 tmp = LPDDR4_DQODT_40; 1133 break; 1134 } 1135 switch (timing_config->caodt) { 1136 case 240: 1137 pdram_timing->mr11 = LPDDR4_CAODT_240 | tmp; 1138 break; 1139 case 120: 1140 pdram_timing->mr11 = LPDDR4_CAODT_120 | tmp; 1141 break; 1142 case 80: 1143 pdram_timing->mr11 = LPDDR4_CAODT_80 | tmp; 1144 break; 1145 case 60: 1146 pdram_timing->mr11 = LPDDR4_CAODT_60 | tmp; 1147 break; 1148 case 48: 1149 pdram_timing->mr11 = LPDDR4_CAODT_48 | tmp; 1150 break; 1151 case 40: 1152 default: 1153 pdram_timing->mr11 = LPDDR4_CAODT_40 | tmp; 1154 break; 1155 } 1156 1157 pdram_timing->tinit1 = (LPDDR4_TINIT1 * nmhz + 999) / 1000; 1158 pdram_timing->tinit2 = (LPDDR4_TINIT2 * nmhz + 999) / 1000; 1159 pdram_timing->tinit3 = (LPDDR4_TINIT3 * nmhz + 999) / 1000; 1160 pdram_timing->tinit4 = (LPDDR4_TINIT4 * nmhz + 999) / 1000; 1161 pdram_timing->tinit5 = (LPDDR4_TINIT5 * nmhz + 999) / 1000; 1162 pdram_timing->trstl = (LPDDR4_TRSTL * nmhz + 999) / 1000; 1163 pdram_timing->trsth = (LPDDR4_TRSTH * nmhz + 999) / 1000; 1164 /* tREFI, average periodic refresh interval, 3.9us(4Gb-16Gb) */ 1165 pdram_timing->trefi = (LPDDR4_TREFI_3_9_US * nmhz + 999) / 1000; 1166 /* base timing */ 1167 tmp = ((LPDDR4_TRCD * nmhz + 999) / 1000); 1168 pdram_timing->trcd = max(4, tmp); 1169 trppb_tmp = ((LPDDR4_TRP_PB * nmhz + 999) / 1000); 1170 trppb_tmp = max(4, trppb_tmp); 1171 pdram_timing->trppb = trppb_tmp; 1172 trp_tmp = ((LPDDR4_TRP_AB * nmhz + 999) / 1000); 1173 trp_tmp = max(4, trp_tmp); 1174 pdram_timing->trp = trp_tmp; 1175 tras_tmp = ((LPDDR4_TRAS * nmhz + 999) / 1000); 1176 tras_tmp = max(3, tras_tmp); 1177 pdram_timing->tras_min = tras_tmp; 1178 pdram_timing->trc = (tras_tmp + trp_tmp); 1179 tmp = ((LPDDR4_TRRD * nmhz + 999) / 1000); 1180 pdram_timing->trrd = max(4, tmp); 1181 if (timing_config->bl == 32) 1182 pdram_timing->tccd = LPDDR4_TCCD_BL16; 1183 else 1184 pdram_timing->tccd = LPDDR4_TCCD_BL32; 1185 pdram_timing->tccdmw = 4 * pdram_timing->tccd; 1186 tmp = ((LPDDR4_TWTR * nmhz + 999) / 1000); 1187 pdram_timing->twtr = max(8, tmp); 1188 pdram_timing->trtw = ((LPDDR4_TRTW * nmhz + 999) / 1000); 1189 pdram_timing->tras_max = ((LPDDR4_TRAS_MAX * nmhz + 999) / 1000); 1190 pdram_timing->tfaw = (LPDDR4_TFAW * nmhz + 999) / 1000; 1191 if (ddr_capability_per_die > 0x60000000) { 1192 /* >= 12Gb */ 1193 pdram_timing->trfc = 1194 (LPDDR4_TRFC_12GBIT * nmhz + 999) / 1000; 1195 tmp = (((LPDDR4_TRFC_12GBIT + 7) * nmhz + (nmhz >> 1) + 1196 999) / 1000); 1197 } else if (ddr_capability_per_die > 0x30000000) { 1198 pdram_timing->trfc = 1199 (LPDDR4_TRFC_6GBIT * nmhz + 999) / 1000; 1200 tmp = (((LPDDR4_TRFC_6GBIT + 7) * nmhz + (nmhz >> 1) + 1201 999) / 1000); 1202 } else { 1203 pdram_timing->trfc = 1204 (LPDDR4_TRFC_4GBIT * nmhz + 999) / 1000; 1205 tmp = (((LPDDR4_TRFC_4GBIT + 7) * nmhz + (nmhz >> 1) + 1206 999) / 1000); 1207 } 1208 pdram_timing->txsr = max(2, tmp); 1209 pdram_timing->txsnr = max(2, tmp); 1210 /* tdqsck use rounded down */ 1211 pdram_timing->tdqsck = ((LPDDR4_TDQSCK_MIN * nmhz + 1212 (nmhz >> 1)) / 1000); 1213 pdram_timing->tdqsck_max = ((LPDDR4_TDQSCK_MAX * nmhz + 1214 (nmhz >> 1) + 999) / 1000); 1215 pdram_timing->tppd = LPDDR4_TPPD; 1216 /* pd and sr */ 1217 tmp = ((LPDDR4_TXP * nmhz + (nmhz >> 1) + 999) / 1000); 1218 pdram_timing->txp = max(5, tmp); 1219 tmp = ((LPDDR4_TCKE * nmhz + (nmhz >> 1) + 999) / 1000); 1220 pdram_timing->tcke = max(4, tmp); 1221 tmp = ((LPDDR4_TESCKE * nmhz + 1222 ((nmhz * 3) / 4) + 1223 999) / 1000); 1224 pdram_timing->tescke = max(3, tmp); 1225 tmp = ((LPDDR4_TSR * nmhz + 999) / 1000); 1226 pdram_timing->tsr = max(3, tmp); 1227 tmp = ((LPDDR4_TCMDCKE * nmhz + 1228 ((nmhz * 3) / 4) + 1229 999) / 1000); 1230 pdram_timing->tcmdcke = max(3, tmp); 1231 pdram_timing->tcscke = ((LPDDR4_TCSCKE * nmhz + 1232 ((nmhz * 3) / 4) + 1233 999) / 1000); 1234 tmp = ((LPDDR4_TCKELCS * nmhz + 999) / 1000); 1235 pdram_timing->tckelcs = max(5, tmp); 1236 pdram_timing->tcsckeh = ((LPDDR4_TCSCKEH * nmhz + 1237 ((nmhz * 3) / 4) + 1238 999) / 1000); 1239 tmp = ((LPDDR4_TCKEHCS * nmhz + 1240 (nmhz >> 1) + 999) / 1000); 1241 pdram_timing->tckehcs = max(5, tmp); 1242 tmp = ((LPDDR4_TMRWCKEL * nmhz + 999) / 1000); 1243 pdram_timing->tmrwckel = max(10, tmp); 1244 tmp = ((LPDDR4_TCKELCMD * nmhz + (nmhz >> 1) + 1245 999) / 1000); 1246 pdram_timing->tckelcmd = max(3, tmp); 1247 tmp = ((LPDDR4_TCKEHCMD * nmhz + (nmhz >> 1) + 1248 999) / 1000); 1249 pdram_timing->tckehcmd = max(3, tmp); 1250 tmp = ((LPDDR4_TCKELPD * nmhz + (nmhz >> 1) + 1251 999) / 1000); 1252 pdram_timing->tckelpd = max(3, tmp); 1253 tmp = ((LPDDR4_TCKCKEL * nmhz + (nmhz >> 1) + 1254 999) / 1000); 1255 pdram_timing->tckckel = max(3, tmp); 1256 /* mode register timing */ 1257 tmp = ((LPDDR4_TMRD * nmhz + 999) / 1000); 1258 pdram_timing->tmrd = max(10, tmp); 1259 pdram_timing->tmrr = LPDDR4_TMRR; 1260 pdram_timing->tmrri = pdram_timing->trcd + 3; 1261 /* ODT */ 1262 pdram_timing->todton = (LPDDR4_TODTON * nmhz + (nmhz >> 1) + 999) 1263 / 1000; 1264 /* ZQ */ 1265 pdram_timing->tzqcal = (LPDDR4_TZQCAL * nmhz + 999) / 1000; 1266 tmp = ((LPDDR4_TZQLAT * nmhz + 999) / 1000); 1267 pdram_timing->tzqlat = max(8, tmp); 1268 tmp = ((LPDDR4_TZQRESET * nmhz + 999) / 1000); 1269 pdram_timing->tzqreset = max(3, tmp); 1270 tmp = ((LPDDR4_TZQCKE * nmhz + 1271 ((nmhz * 3) / 4) + 1272 999) / 1000); 1273 pdram_timing->tzqcke = max(3, tmp); 1274 /* write leveling */ 1275 pdram_timing->twlmrd = LPDDR4_TWLMRD; 1276 pdram_timing->twlo = (LPDDR4_TWLO * nmhz + 999) / 1000; 1277 pdram_timing->twldqsen = LPDDR4_TWLDQSEN; 1278 /* CA training */ 1279 pdram_timing->tcaent = (LPDDR4_TCAENT * nmhz + 999) / 1000; 1280 pdram_timing->tadr = (LPDDR4_TADR * nmhz + 999) / 1000; 1281 pdram_timing->tmrz = (LPDDR4_TMRZ * nmhz + (nmhz >> 1) + 999) / 1000; 1282 pdram_timing->tvref_long = (LPDDR4_TVREF_LONG * nmhz + 999) / 1000; 1283 pdram_timing->tvref_short = (LPDDR4_TVREF_SHORT * nmhz + 999) / 1000; 1284 /* VRCG */ 1285 pdram_timing->tvrcg_enable = (LPDDR4_TVRCG_ENABLE * nmhz + 1286 999) / 1000; 1287 pdram_timing->tvrcg_disable = (LPDDR4_TVRCG_DISABLE * nmhz + 1288 999) / 1000; 1289 /* FSP */ 1290 pdram_timing->tfc_long = (LPDDR4_TFC_LONG * nmhz + 999) / 1000; 1291 tmp = (LPDDR4_TCKFSPE * nmhz + (nmhz >> 1) + 999) / 1000; 1292 pdram_timing->tckfspe = max(4, tmp); 1293 tmp = (LPDDR4_TCKFSPX * nmhz + (nmhz >> 1) + 999) / 1000; 1294 pdram_timing->tckfspx = max(4, tmp); 1295 } 1296 1297 /* 1298 * Description: depend on input parameter "timing_config", 1299 * and calculate correspond "dram_type" 1300 * spec timing to "pdram_timing" 1301 * parameters: 1302 * input: timing_config 1303 * output: pdram_timing 1304 * NOTE: MR ODT is set, need to disable by controller 1305 */ 1306 void dram_get_parameter(struct timing_related_config *timing_config, 1307 struct dram_timing_t *pdram_timing) 1308 { 1309 switch (timing_config->dram_type) { 1310 case DDR3: 1311 ddr3_get_parameter(timing_config, pdram_timing); 1312 break; 1313 case LPDDR2: 1314 lpddr2_get_parameter(timing_config, pdram_timing); 1315 break; 1316 case LPDDR3: 1317 lpddr3_get_parameter(timing_config, pdram_timing); 1318 break; 1319 case LPDDR4: 1320 lpddr4_get_parameter(timing_config, pdram_timing); 1321 break; 1322 } 1323 } 1324