1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __SOC_ROCKCHIP_RK3399_DRAM_H__ 32 #define __SOC_ROCKCHIP_RK3399_DRAM_H__ 33 #include <plat_private.h> 34 #include <stdint.h> 35 36 #define CTL_BASE(ch) (0xffa80000 + (ch) * 0x8000) 37 #define CTL_REG(ch, n) (CTL_BASE(ch) + (n) * 0x4) 38 39 #define PI_OFFSET 0x800 40 #define PI_BASE(ch) (CTL_BASE(ch) + PI_OFFSET) 41 #define PI_REG(ch, n) (PI_BASE(ch) + (n) * 0x4) 42 43 #define PHY_OFFSET 0x2000 44 #define PHY_BASE(ch) (CTL_BASE(ch) + PHY_OFFSET) 45 #define PHY_REG(ch, n) (PHY_BASE(ch) + (n) * 0x4) 46 47 #define MSCH_BASE(ch) (0xffa84000 + (ch) * 0x8000) 48 #define MSCH_ID_COREID 0x0 49 #define MSCH_ID_REVISIONID 0x4 50 #define MSCH_DEVICECONF 0x8 51 #define MSCH_DEVICESIZE 0xc 52 #define MSCH_DDRTIMINGA0 0x10 53 #define MSCH_DDRTIMINGB0 0x14 54 #define MSCH_DDRTIMINGC0 0x18 55 #define MSCH_DEVTODEV0 0x1c 56 #define MSCH_DDRMODE 0x110 57 #define MSCH_AGINGX0 0x1000 58 59 #define CIC_CTRL0 0x0 60 #define CIC_CTRL1 0x4 61 #define CIC_IDLE_TH 0x8 62 #define CIC_CG_WAIT_TH 0xc 63 #define CIC_STATUS0 0x10 64 #define CIC_STATUS1 0x14 65 #define CIC_CTRL2 0x18 66 #define CIC_CTRL3 0x1c 67 #define CIC_CTRL4 0x20 68 69 /* DENALI_CTL_00 */ 70 #define START 1 71 72 /* DENALI_CTL_68 */ 73 #define PWRUP_SREFRESH_EXIT (1 << 16) 74 75 /* DENALI_CTL_274 */ 76 #define MEM_RST_VALID 1 77 78 #define PHY_DRV_ODT_Hi_Z 0x0 79 #define PHY_DRV_ODT_240 0x1 80 #define PHY_DRV_ODT_120 0x8 81 #define PHY_DRV_ODT_80 0x9 82 #define PHY_DRV_ODT_60 0xc 83 #define PHY_DRV_ODT_48 0xd 84 #define PHY_DRV_ODT_40 0xe 85 #define PHY_DRV_ODT_34_3 0xf 86 87 /* 88 * sys_reg bitfield struct 89 * [31] row_3_4_ch1 90 * [30] row_3_4_ch0 91 * [29:28] chinfo 92 * [27] rank_ch1 93 * [26:25] col_ch1 94 * [24] bk_ch1 95 * [23:22] cs0_row_ch1 96 * [21:20] cs1_row_ch1 97 * [19:18] bw_ch1 98 * [17:16] dbw_ch1; 99 * [15:13] ddrtype 100 * [12] channelnum 101 * [11] rank_ch0 102 * [10:9] col_ch0 103 * [8] bk_ch0 104 * [7:6] cs0_row_ch0 105 * [5:4] cs1_row_ch0 106 * [3:2] bw_ch0 107 * [1:0] dbw_ch0 108 */ 109 #define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) 110 #define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1) 111 #define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch))) 112 #define SYS_REG_DEC_CHINFO(n, ch) (((n) >> (28 + (ch))) & 0x1) 113 #define SYS_REG_ENC_DDRTYPE(n) ((n) << 13) 114 #define SYS_REG_DEC_DDRTYPE(n) (((n) >> 13) & 0x7) 115 #define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12) 116 #define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1)) 117 #define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + (ch) * 16)) 118 #define SYS_REG_DEC_RANK(n, ch) (1 + (((n) >> (11 + (ch) * 16)) & 0x1)) 119 #define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + (ch) * 16)) 120 #define SYS_REG_DEC_COL(n, ch) (9 + (((n) >> (9 + (ch) * 16)) & 0x3)) 121 #define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << (8 + (ch) * 16)) 122 #define SYS_REG_DEC_BK(n, ch) (3 - (((n) >> (8 + (ch) * 16)) & 0x1)) 123 #define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << (6 + (ch) * 16)) 124 #define SYS_REG_DEC_CS0_ROW(n, ch) (13 + (((n) >> (6 + (ch) * 16)) & 0x3)) 125 #define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << (4 + (ch) * 16)) 126 #define SYS_REG_DEC_CS1_ROW(n, ch) (13 + (((n) >> (4 + (ch) * 16)) & 0x3)) 127 #define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + (ch) * 16)) 128 #define SYS_REG_DEC_BW(n, ch) (2 >> (((n) >> (2 + (ch) * 16)) & 0x3)) 129 #define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + (ch) * 16)) 130 #define SYS_REG_DEC_DBW(n, ch) (2 >> (((n) >> (0 + (ch) * 16)) & 0x3)) 131 #define DDR_STRIDE(n) mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(4), \ 132 (0x1f<<(10+16))|((n)<<10)) 133 134 #define CTL_REG_NUM 332 135 #define PHY_REG_NUM 959 136 #define PI_REG_NUM 200 137 138 enum { 139 DDR3 = 3, 140 LPDDR2 = 5, 141 LPDDR3 = 6, 142 LPDDR4 = 7, 143 UNUSED = 0xff 144 }; 145 146 struct rk3399_ddr_pctl_regs { 147 uint32_t denali_ctl[CTL_REG_NUM]; 148 }; 149 150 struct rk3399_ddr_publ_regs { 151 uint32_t denali_phy[PHY_REG_NUM]; 152 }; 153 154 struct rk3399_ddr_pi_regs { 155 uint32_t denali_pi[PI_REG_NUM]; 156 }; 157 union noc_ddrtiminga0 { 158 uint32_t d32; 159 struct { 160 unsigned acttoact : 6; 161 unsigned reserved0 : 2; 162 unsigned rdtomiss : 6; 163 unsigned reserved1 : 2; 164 unsigned wrtomiss : 6; 165 unsigned reserved2 : 2; 166 unsigned readlatency : 8; 167 } b; 168 }; 169 170 union noc_ddrtimingb0 { 171 uint32_t d32; 172 struct { 173 unsigned rdtowr : 5; 174 unsigned reserved0 : 3; 175 unsigned wrtord : 5; 176 unsigned reserved1 : 3; 177 unsigned rrd : 4; 178 unsigned reserved2 : 4; 179 unsigned faw : 6; 180 unsigned reserved3 : 2; 181 } b; 182 }; 183 184 union noc_ddrtimingc0 { 185 uint32_t d32; 186 struct { 187 unsigned burstpenalty : 4; 188 unsigned reserved0 : 4; 189 unsigned wrtomwr : 6; 190 unsigned reserved1 : 18; 191 } b; 192 }; 193 194 union noc_devtodev0 { 195 uint32_t d32; 196 struct { 197 unsigned busrdtord : 3; 198 unsigned reserved0 : 1; 199 unsigned busrdtowr : 3; 200 unsigned reserved1 : 1; 201 unsigned buswrtord : 3; 202 unsigned reserved2 : 1; 203 unsigned buswrtowr : 3; 204 unsigned reserved3 : 17; 205 } b; 206 }; 207 208 union noc_ddrmode { 209 uint32_t d32; 210 struct { 211 unsigned autoprecharge : 1; 212 unsigned bypassfiltering : 1; 213 unsigned fawbank : 1; 214 unsigned burstsize : 2; 215 unsigned mwrsize : 2; 216 unsigned reserved2 : 1; 217 unsigned forceorder : 8; 218 unsigned forceorderstate : 8; 219 unsigned reserved3 : 8; 220 } b; 221 }; 222 223 struct rk3399_msch_timings { 224 union noc_ddrtiminga0 ddrtiminga0; 225 union noc_ddrtimingb0 ddrtimingb0; 226 union noc_ddrtimingc0 ddrtimingc0; 227 union noc_devtodev0 devtodev0; 228 union noc_ddrmode ddrmode; 229 uint32_t agingx0; 230 }; 231 232 struct rk3399_sdram_channel { 233 unsigned char rank; 234 /* col = 0, means this channel is invalid */ 235 unsigned char col; 236 /* 3:8bank, 2:4bank */ 237 unsigned char bk; 238 /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ 239 unsigned char bw; 240 /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ 241 unsigned char dbw; 242 /* row_3_4 = 1: 6Gb or 12Gb die 243 * row_3_4 = 0: normal die, power of 2 244 */ 245 unsigned char row_3_4; 246 unsigned char cs0_row; 247 unsigned char cs1_row; 248 uint32_t ddrconfig; 249 struct rk3399_msch_timings noc_timings; 250 }; 251 252 struct rk3399_sdram_params { 253 struct rk3399_sdram_channel ch[2]; 254 uint32_t ddr_freq; 255 unsigned char dramtype; 256 unsigned char num_channels; 257 unsigned char stride; 258 unsigned char odt; 259 struct rk3399_ddr_pctl_regs pctl_regs; 260 struct rk3399_ddr_pi_regs pi_regs; 261 struct rk3399_ddr_publ_regs phy_regs; 262 }; 263 264 extern __sramdata struct rk3399_sdram_params sdram_config; 265 266 void dram_init(void); 267 268 #endif 269