1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __SOC_ROCKCHIP_RK3399_SDRAM_H__ 32 #define __SOC_ROCKCHIP_RK3399_SDRAM_H__ 33 34 struct rk3399_ddr_cic_regs { 35 uint32_t cic_ctrl0; 36 uint32_t cic_ctrl1; 37 uint32_t cic_idle_th; 38 uint32_t cic_cg_wait_th; 39 uint32_t cic_status0; 40 uint32_t cic_status1; 41 uint32_t cic_ctrl2; 42 uint32_t cic_ctrl3; 43 uint32_t cic_ctrl4; 44 }; 45 46 /* DENALI_CTL_00 */ 47 #define START (1) 48 49 /* DENALI_CTL_68 */ 50 #define PWRUP_SREFRESH_EXIT (1 << 16) 51 52 /* DENALI_CTL_274 */ 53 #define MEM_RST_VALID (1) 54 55 struct rk3399_ddr_pctl_regs { 56 uint32_t denali_ctl[332]; 57 }; 58 59 struct rk3399_ddr_publ_regs { 60 uint32_t denali_phy[959]; 61 }; 62 63 #define PHY_DRV_ODT_Hi_Z (0x0) 64 #define PHY_DRV_ODT_240 (0x1) 65 #define PHY_DRV_ODT_120 (0x8) 66 #define PHY_DRV_ODT_80 (0x9) 67 #define PHY_DRV_ODT_60 (0xc) 68 #define PHY_DRV_ODT_48 (0xd) 69 #define PHY_DRV_ODT_40 (0xe) 70 #define PHY_DRV_ODT_34_3 (0xf) 71 72 struct rk3399_ddr_pi_regs { 73 uint32_t denali_pi[200]; 74 }; 75 union noc_ddrtiminga0 { 76 uint32_t d32; 77 struct { 78 unsigned acttoact : 6; 79 unsigned reserved0 : 2; 80 unsigned rdtomiss : 6; 81 unsigned reserved1 : 2; 82 unsigned wrtomiss : 6; 83 unsigned reserved2 : 2; 84 unsigned readlatency : 8; 85 } b; 86 }; 87 88 union noc_ddrtimingb0 { 89 uint32_t d32; 90 struct { 91 unsigned rdtowr : 5; 92 unsigned reserved0 : 3; 93 unsigned wrtord : 5; 94 unsigned reserved1 : 3; 95 unsigned rrd : 4; 96 unsigned reserved2 : 4; 97 unsigned faw : 6; 98 unsigned reserved3 : 2; 99 } b; 100 }; 101 102 union noc_ddrtimingc0 { 103 uint32_t d32; 104 struct { 105 unsigned burstpenalty : 4; 106 unsigned reserved0 : 4; 107 unsigned wrtomwr : 6; 108 unsigned reserved1 : 18; 109 } b; 110 }; 111 112 union noc_devtodev0 { 113 uint32_t d32; 114 struct { 115 unsigned busrdtord : 3; 116 unsigned reserved0 : 1; 117 unsigned busrdtowr : 3; 118 unsigned reserved1 : 1; 119 unsigned buswrtord : 3; 120 unsigned reserved2 : 1; 121 unsigned buswrtowr : 3; 122 unsigned reserved3 : 17; 123 } b; 124 }; 125 126 union noc_ddrmode { 127 uint32_t d32; 128 struct { 129 unsigned autoprecharge : 1; 130 unsigned bypassfiltering : 1; 131 unsigned fawbank : 1; 132 unsigned burstsize : 2; 133 unsigned mwrsize : 2; 134 unsigned reserved2 : 1; 135 unsigned forceorder : 8; 136 unsigned forceorderstate : 8; 137 unsigned reserved3 : 8; 138 } b; 139 }; 140 141 struct rk3399_msch_regs { 142 uint32_t coreid; 143 uint32_t revisionid; 144 uint32_t ddrconf; 145 uint32_t ddrsize; 146 union noc_ddrtiminga0 ddrtiminga0; 147 union noc_ddrtimingb0 ddrtimingb0; 148 union noc_ddrtimingc0 ddrtimingc0; 149 union noc_devtodev0 devtodev0; 150 uint32_t reserved0[(0x110-0x20)/4]; 151 union noc_ddrmode ddrmode; 152 uint32_t reserved1[(0x1000-0x114)/4]; 153 uint32_t agingx0; 154 }; 155 156 struct rk3399_msch_timings { 157 union noc_ddrtiminga0 ddrtiminga0; 158 union noc_ddrtimingb0 ddrtimingb0; 159 union noc_ddrtimingc0 ddrtimingc0; 160 union noc_devtodev0 devtodev0; 161 union noc_ddrmode ddrmode; 162 uint32_t agingx0; 163 }; 164 #if 1 165 struct rk3399_sdram_channel { 166 unsigned char rank; 167 /* col = 0, means this channel is invalid */ 168 unsigned char col; 169 /* 3:8bank, 2:4bank */ 170 unsigned char bk; 171 /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ 172 unsigned char bw; 173 /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ 174 unsigned char dbw; 175 /* row_3_4 = 1: 6Gb or 12Gb die 176 * row_3_4 = 0: normal die, power of 2 177 */ 178 unsigned char row_3_4; 179 unsigned char cs0_row; 180 unsigned char cs1_row; 181 uint32_t ddrconfig; 182 struct rk3399_msch_timings noc_timings; 183 }; 184 185 struct rk3399_sdram_params { 186 struct rk3399_sdram_channel ch[2]; 187 uint32_t ddr_freq; 188 unsigned char dramtype; 189 unsigned char num_channels; 190 unsigned char stride; 191 unsigned char odt; 192 struct rk3399_ddr_pctl_regs pctl_regs; 193 struct rk3399_ddr_pi_regs pi_regs; 194 struct rk3399_ddr_publ_regs phy_regs; 195 }; 196 #endif 197 struct rk3399_sdram_channel_config { 198 uint32_t bus_width; 199 uint32_t cs_cnt; 200 uint32_t cs0_row; 201 uint32_t cs1_row; 202 uint32_t bank; 203 uint32_t col; 204 uint32_t each_die_bus_width; 205 uint32_t each_die_6gb_or_12gb; 206 }; 207 208 struct rk3399_sdram_config { 209 struct rk3399_sdram_channel_config ch[2]; 210 uint32_t dramtype; 211 uint32_t channal_num; 212 }; 213 214 struct rk3399_sdram_default_config { 215 unsigned char bl; 216 /* 1:auto precharge, 0:never auto precharge */ 217 unsigned char ap; 218 /* dram driver strength */ 219 unsigned char dramds; 220 /* dram ODT, if odt=0, this parameter invalid */ 221 unsigned char dramodt; 222 /* ca ODT, if odt=0, this parameter invalid 223 * only used by LPDDR4 224 */ 225 unsigned char caodt; 226 unsigned char burst_ref_cnt; 227 /* zqcs period, unit(s) */ 228 unsigned char zqcsi; 229 }; 230 231 struct ddr_dts_config_timing { 232 unsigned int ddr3_speed_bin; 233 unsigned int pd_idle; 234 unsigned int sr_idle; 235 unsigned int sr_mc_gate_idle; 236 unsigned int srpd_lite_idle; 237 unsigned int standby_idle; 238 unsigned int auto_pd_dis_freq; 239 unsigned int ddr3_dll_dis_freq; 240 unsigned int phy_dll_dis_freq; 241 unsigned int ddr3_odt_dis_freq; 242 unsigned int ddr3_drv; 243 unsigned int ddr3_odt; 244 unsigned int phy_ddr3_ca_drv; 245 unsigned int phy_ddr3_dq_drv; 246 unsigned int phy_ddr3_odt; 247 unsigned int lpddr3_odt_dis_freq; 248 unsigned int lpddr3_drv; 249 unsigned int lpddr3_odt; 250 unsigned int phy_lpddr3_ca_drv; 251 unsigned int phy_lpddr3_dq_drv; 252 unsigned int phy_lpddr3_odt; 253 unsigned int lpddr4_odt_dis_freq; 254 unsigned int lpddr4_drv; 255 unsigned int lpddr4_dq_odt; 256 unsigned int lpddr4_ca_odt; 257 unsigned int phy_lpddr4_ca_drv; 258 unsigned int phy_lpddr4_ck_cs_drv; 259 unsigned int phy_lpddr4_dq_drv; 260 unsigned int phy_lpddr4_odt; 261 uint32_t available; 262 }; 263 264 struct drv_odt_lp_config { 265 uint32_t ddr3_speed_bin; 266 uint32_t pd_idle; 267 uint32_t sr_idle; 268 uint32_t sr_mc_gate_idle; 269 uint32_t srpd_lite_idle; 270 uint32_t standby_idle; 271 272 uint32_t ddr3_dll_dis_freq;/* for ddr3 only */ 273 uint32_t phy_dll_dis_freq; 274 uint32_t odt_dis_freq; 275 276 uint32_t dram_side_drv; 277 uint32_t dram_side_dq_odt; 278 uint32_t dram_side_ca_odt; 279 280 uint32_t phy_side_ca_drv; 281 uint32_t phy_side_ck_cs_drv; 282 uint32_t phy_side_dq_drv; 283 uint32_t phy_side_odt; 284 }; 285 286 #define KHz (1000) 287 #define MHz (1000*KHz) 288 #define GHz (1000*MHz) 289 290 #define PI_CA_TRAINING (1 << 0) 291 #define PI_WRITE_LEVELING (1 << 1) 292 #define PI_READ_GATE_TRAINING (1 << 2) 293 #define PI_READ_LEVELING (1 << 3) 294 #define PI_WDQ_LEVELING (1 << 4) 295 #define PI_FULL_TARINING (0xff) 296 297 #define READ_CH_CNT(val) (1+((val>>12)&0x1)) 298 #define READ_CH_INFO(val) ((val>>28)&0x3) 299 /* row_3_4:0=normal, 1=6Gb or 12Gb */ 300 #define READ_CH_ROW_INFO(val, ch) ((val>>(30+(ch)))&0x1) 301 302 #define READ_DRAMTYPE_INFO(val) ((val>>13)&0x7) 303 #define READ_CS_INFO(val, ch) ((((val)>>(11+(ch)*16))&0x1)+1) 304 #define READ_BW_INFO(val, ch) (2>>(((val)>>(2+(ch)*16))&0x3)) 305 #define READ_COL_INFO(val, ch) (9+(((val)>>(9+(ch)*16))&0x3)) 306 #define READ_BK_INFO(val, ch) (3-(((val)>>(8+(ch)*16))&0x1)) 307 #define READ_CS0_ROW_INFO(val, ch) (13+(((val)>>(6+(ch)*16))&0x3)) 308 #define READ_CS1_ROW_INFO(val, ch) (13+(((val)>>(4+(ch)*16))&0x3)) 309 #define READ_DIE_BW_INFO(val, ch) (2>>((val>>((ch)*16))&0x3)) 310 311 #define __sramdata __attribute__((section(".sram.data"))) 312 #define __sramconst __attribute__((section(".sram.rodata"))) 313 #define __sramlocalfunc __attribute__((section(".sram.text"))) 314 #define __sramfunc __attribute__((section(".sram.text"))) \ 315 __attribute__((noinline)) 316 317 318 #define DDR_SAVE_SP(save_sp) (save_sp = ddr_save_sp(((uint32_t)\ 319 (SRAM_CODE_BASE + 0x2000) & (~7)))) 320 321 #define DDR_RESTORE_SP(save_sp) ddr_save_sp(save_sp) 322 323 void ddr_init(void); 324 uint32_t ddr_set_rate(uint32_t hz); 325 uint32_t ddr_round_rate(uint32_t hz); 326 uint32_t ddr_get_rate(void); 327 void clr_dcf_irq(void); 328 uint32_t dts_timing_receive(uint32_t timing, uint32_t index); 329 #endif 330