1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __SOC_ROCKCHIP_RK3399_DRAM_H__ 32 #define __SOC_ROCKCHIP_RK3399_DRAM_H__ 33 34 #include <dram_regs.h> 35 #include <plat_private.h> 36 #include <stdint.h> 37 38 enum { 39 DDR3 = 3, 40 LPDDR2 = 5, 41 LPDDR3 = 6, 42 LPDDR4 = 7, 43 UNUSED = 0xff 44 }; 45 46 struct rk3399_ddr_pctl_regs { 47 uint32_t denali_ctl[CTL_REG_NUM]; 48 }; 49 50 struct rk3399_ddr_publ_regs { 51 uint32_t denali_phy[PHY_REG_NUM]; 52 }; 53 54 struct rk3399_ddr_pi_regs { 55 uint32_t denali_pi[PI_REG_NUM]; 56 }; 57 union noc_ddrtiminga0 { 58 uint32_t d32; 59 struct { 60 unsigned acttoact : 6; 61 unsigned reserved0 : 2; 62 unsigned rdtomiss : 6; 63 unsigned reserved1 : 2; 64 unsigned wrtomiss : 6; 65 unsigned reserved2 : 2; 66 unsigned readlatency : 8; 67 } b; 68 }; 69 70 union noc_ddrtimingb0 { 71 uint32_t d32; 72 struct { 73 unsigned rdtowr : 5; 74 unsigned reserved0 : 3; 75 unsigned wrtord : 5; 76 unsigned reserved1 : 3; 77 unsigned rrd : 4; 78 unsigned reserved2 : 4; 79 unsigned faw : 6; 80 unsigned reserved3 : 2; 81 } b; 82 }; 83 84 union noc_ddrtimingc0 { 85 uint32_t d32; 86 struct { 87 unsigned burstpenalty : 4; 88 unsigned reserved0 : 4; 89 unsigned wrtomwr : 6; 90 unsigned reserved1 : 18; 91 } b; 92 }; 93 94 union noc_devtodev0 { 95 uint32_t d32; 96 struct { 97 unsigned busrdtord : 3; 98 unsigned reserved0 : 1; 99 unsigned busrdtowr : 3; 100 unsigned reserved1 : 1; 101 unsigned buswrtord : 3; 102 unsigned reserved2 : 1; 103 unsigned buswrtowr : 3; 104 unsigned reserved3 : 17; 105 } b; 106 }; 107 108 union noc_ddrmode { 109 uint32_t d32; 110 struct { 111 unsigned autoprecharge : 1; 112 unsigned bypassfiltering : 1; 113 unsigned fawbank : 1; 114 unsigned burstsize : 2; 115 unsigned mwrsize : 2; 116 unsigned reserved2 : 1; 117 unsigned forceorder : 8; 118 unsigned forceorderstate : 8; 119 unsigned reserved3 : 8; 120 } b; 121 }; 122 123 struct rk3399_msch_timings { 124 union noc_ddrtiminga0 ddrtiminga0; 125 union noc_ddrtimingb0 ddrtimingb0; 126 union noc_ddrtimingc0 ddrtimingc0; 127 union noc_devtodev0 devtodev0; 128 union noc_ddrmode ddrmode; 129 uint32_t agingx0; 130 }; 131 132 struct rk3399_sdram_channel { 133 unsigned char rank; 134 /* col = 0, means this channel is invalid */ 135 unsigned char col; 136 /* 3:8bank, 2:4bank */ 137 unsigned char bk; 138 /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ 139 unsigned char bw; 140 /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ 141 unsigned char dbw; 142 /* row_3_4 = 1: 6Gb or 12Gb die 143 * row_3_4 = 0: normal die, power of 2 144 */ 145 unsigned char row_3_4; 146 unsigned char cs0_row; 147 unsigned char cs1_row; 148 uint32_t ddrconfig; 149 struct rk3399_msch_timings noc_timings; 150 }; 151 152 struct rk3399_sdram_params { 153 struct rk3399_sdram_channel ch[2]; 154 uint32_t ddr_freq; 155 unsigned char dramtype; 156 unsigned char num_channels; 157 unsigned char stride; 158 unsigned char odt; 159 struct rk3399_ddr_pctl_regs pctl_regs; 160 struct rk3399_ddr_pi_regs pi_regs; 161 struct rk3399_ddr_publ_regs phy_regs; 162 uint32_t rx_cal_dqs[2][4]; 163 }; 164 165 extern __sramdata struct rk3399_sdram_params sdram_config; 166 167 void dram_init(void); 168 169 #endif 170