1fe877779SCaesar Wang /* 2fe877779SCaesar Wang * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3fe877779SCaesar Wang * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5fe877779SCaesar Wang */ 6fe877779SCaesar Wang 7c3cf06f1SAntonio Nino Diaz #ifndef DRAM_H 8c3cf06f1SAntonio Nino Diaz #define DRAM_H 91830f790SXing Zheng 1009d40e0eSAntonio Nino Diaz #include <stdint.h> 1109d40e0eSAntonio Nino Diaz 121830f790SXing Zheng #include <dram_regs.h> 13613038bcSCaesar Wang #include <plat_private.h> 14fe877779SCaesar Wang 15613038bcSCaesar Wang enum { 16613038bcSCaesar Wang DDR3 = 3, 17613038bcSCaesar Wang LPDDR2 = 5, 18613038bcSCaesar Wang LPDDR3 = 6, 19613038bcSCaesar Wang LPDDR4 = 7, 20613038bcSCaesar Wang UNUSED = 0xff 21613038bcSCaesar Wang }; 22fe877779SCaesar Wang 23fe877779SCaesar Wang struct rk3399_ddr_pctl_regs { 24613038bcSCaesar Wang uint32_t denali_ctl[CTL_REG_NUM]; 25fe877779SCaesar Wang }; 26fe877779SCaesar Wang 27fe877779SCaesar Wang struct rk3399_ddr_publ_regs { 2860400fc8SDerek Basehore /* 294c3770d9SLin Huang * PHY registers from 0 to 90 for slice1. 304c3770d9SLin Huang * These are used to restore slice1-4 on resume. 3160400fc8SDerek Basehore */ 324c3770d9SLin Huang uint32_t phy0[91]; 3360400fc8SDerek Basehore /* 3460400fc8SDerek Basehore * PHY registers from 512 to 895. 3560400fc8SDerek Basehore * Only registers 0-37 of each 128 register range are used. 3660400fc8SDerek Basehore */ 3760400fc8SDerek Basehore uint32_t phy512[3][38]; 3860400fc8SDerek Basehore uint32_t phy896[63]; 39fe877779SCaesar Wang }; 40fe877779SCaesar Wang 41fe877779SCaesar Wang struct rk3399_ddr_pi_regs { 42613038bcSCaesar Wang uint32_t denali_pi[PI_REG_NUM]; 43fe877779SCaesar Wang }; 44fe877779SCaesar Wang union noc_ddrtiminga0 { 45fe877779SCaesar Wang uint32_t d32; 46fe877779SCaesar Wang struct { 47fe877779SCaesar Wang unsigned acttoact : 6; 48fe877779SCaesar Wang unsigned reserved0 : 2; 49fe877779SCaesar Wang unsigned rdtomiss : 6; 50fe877779SCaesar Wang unsigned reserved1 : 2; 51fe877779SCaesar Wang unsigned wrtomiss : 6; 52fe877779SCaesar Wang unsigned reserved2 : 2; 53fe877779SCaesar Wang unsigned readlatency : 8; 54fe877779SCaesar Wang } b; 55fe877779SCaesar Wang }; 56fe877779SCaesar Wang 57fe877779SCaesar Wang union noc_ddrtimingb0 { 58fe877779SCaesar Wang uint32_t d32; 59fe877779SCaesar Wang struct { 60fe877779SCaesar Wang unsigned rdtowr : 5; 61fe877779SCaesar Wang unsigned reserved0 : 3; 62fe877779SCaesar Wang unsigned wrtord : 5; 63fe877779SCaesar Wang unsigned reserved1 : 3; 64fe877779SCaesar Wang unsigned rrd : 4; 65fe877779SCaesar Wang unsigned reserved2 : 4; 66fe877779SCaesar Wang unsigned faw : 6; 67fe877779SCaesar Wang unsigned reserved3 : 2; 68fe877779SCaesar Wang } b; 69fe877779SCaesar Wang }; 70fe877779SCaesar Wang 71fe877779SCaesar Wang union noc_ddrtimingc0 { 72fe877779SCaesar Wang uint32_t d32; 73fe877779SCaesar Wang struct { 74fe877779SCaesar Wang unsigned burstpenalty : 4; 75fe877779SCaesar Wang unsigned reserved0 : 4; 76fe877779SCaesar Wang unsigned wrtomwr : 6; 77fe877779SCaesar Wang unsigned reserved1 : 18; 78fe877779SCaesar Wang } b; 79fe877779SCaesar Wang }; 80fe877779SCaesar Wang 81fe877779SCaesar Wang union noc_devtodev0 { 82fe877779SCaesar Wang uint32_t d32; 83fe877779SCaesar Wang struct { 84fe877779SCaesar Wang unsigned busrdtord : 3; 85fe877779SCaesar Wang unsigned reserved0 : 1; 86fe877779SCaesar Wang unsigned busrdtowr : 3; 87fe877779SCaesar Wang unsigned reserved1 : 1; 88fe877779SCaesar Wang unsigned buswrtord : 3; 89fe877779SCaesar Wang unsigned reserved2 : 1; 90fe877779SCaesar Wang unsigned buswrtowr : 3; 91fe877779SCaesar Wang unsigned reserved3 : 17; 92fe877779SCaesar Wang } b; 93fe877779SCaesar Wang }; 94fe877779SCaesar Wang 95fe877779SCaesar Wang union noc_ddrmode { 96fe877779SCaesar Wang uint32_t d32; 97fe877779SCaesar Wang struct { 98fe877779SCaesar Wang unsigned autoprecharge : 1; 99fe877779SCaesar Wang unsigned bypassfiltering : 1; 100fe877779SCaesar Wang unsigned fawbank : 1; 101fe877779SCaesar Wang unsigned burstsize : 2; 102fe877779SCaesar Wang unsigned mwrsize : 2; 103fe877779SCaesar Wang unsigned reserved2 : 1; 104fe877779SCaesar Wang unsigned forceorder : 8; 105fe877779SCaesar Wang unsigned forceorderstate : 8; 106fe877779SCaesar Wang unsigned reserved3 : 8; 107fe877779SCaesar Wang } b; 108fe877779SCaesar Wang }; 109fe877779SCaesar Wang 110fe877779SCaesar Wang struct rk3399_msch_timings { 111fe877779SCaesar Wang union noc_ddrtiminga0 ddrtiminga0; 112fe877779SCaesar Wang union noc_ddrtimingb0 ddrtimingb0; 113fe877779SCaesar Wang union noc_ddrtimingc0 ddrtimingc0; 114fe877779SCaesar Wang union noc_devtodev0 devtodev0; 115fe877779SCaesar Wang union noc_ddrmode ddrmode; 116fe877779SCaesar Wang uint32_t agingx0; 117fe877779SCaesar Wang }; 118613038bcSCaesar Wang 119fe877779SCaesar Wang struct rk3399_sdram_channel { 120fe877779SCaesar Wang unsigned char rank; 121fe877779SCaesar Wang /* col = 0, means this channel is invalid */ 122fe877779SCaesar Wang unsigned char col; 123fe877779SCaesar Wang /* 3:8bank, 2:4bank */ 124fe877779SCaesar Wang unsigned char bk; 125fe877779SCaesar Wang /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ 126fe877779SCaesar Wang unsigned char bw; 127fe877779SCaesar Wang /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ 128fe877779SCaesar Wang unsigned char dbw; 129fe877779SCaesar Wang /* row_3_4 = 1: 6Gb or 12Gb die 130fe877779SCaesar Wang * row_3_4 = 0: normal die, power of 2 131fe877779SCaesar Wang */ 132fe877779SCaesar Wang unsigned char row_3_4; 133fe877779SCaesar Wang unsigned char cs0_row; 134fe877779SCaesar Wang unsigned char cs1_row; 135fe877779SCaesar Wang uint32_t ddrconfig; 136fe877779SCaesar Wang struct rk3399_msch_timings noc_timings; 137fe877779SCaesar Wang }; 138fe877779SCaesar Wang 139fe877779SCaesar Wang struct rk3399_sdram_params { 140fe877779SCaesar Wang struct rk3399_sdram_channel ch[2]; 141fe877779SCaesar Wang uint32_t ddr_freq; 142fe877779SCaesar Wang unsigned char dramtype; 143fe877779SCaesar Wang unsigned char num_channels; 144fe877779SCaesar Wang unsigned char stride; 145fe877779SCaesar Wang unsigned char odt; 146fe877779SCaesar Wang struct rk3399_ddr_pctl_regs pctl_regs; 147fe877779SCaesar Wang struct rk3399_ddr_pi_regs pi_regs; 148fe877779SCaesar Wang struct rk3399_ddr_publ_regs phy_regs; 149951752ddSDerek Basehore uint32_t rx_cal_dqs[2][4]; 150fe877779SCaesar Wang }; 151fe877779SCaesar Wang 152*f943b7c8SPatrick Georgi extern struct rk3399_sdram_params sdram_config; 153fe877779SCaesar Wang 154613038bcSCaesar Wang void dram_init(void); 155fe877779SCaesar Wang 156c3cf06f1SAntonio Nino Diaz #endif /* DRAM_H */ 157