1fe877779SCaesar Wang /* 2fe877779SCaesar Wang * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3fe877779SCaesar Wang * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5fe877779SCaesar Wang */ 6fe877779SCaesar Wang 7613038bcSCaesar Wang #ifndef __SOC_ROCKCHIP_RK3399_DRAM_H__ 8613038bcSCaesar Wang #define __SOC_ROCKCHIP_RK3399_DRAM_H__ 91830f790SXing Zheng 101830f790SXing Zheng #include <dram_regs.h> 11613038bcSCaesar Wang #include <plat_private.h> 12613038bcSCaesar Wang #include <stdint.h> 13fe877779SCaesar Wang 14613038bcSCaesar Wang enum { 15613038bcSCaesar Wang DDR3 = 3, 16613038bcSCaesar Wang LPDDR2 = 5, 17613038bcSCaesar Wang LPDDR3 = 6, 18613038bcSCaesar Wang LPDDR4 = 7, 19613038bcSCaesar Wang UNUSED = 0xff 20613038bcSCaesar Wang }; 21fe877779SCaesar Wang 22fe877779SCaesar Wang struct rk3399_ddr_pctl_regs { 23613038bcSCaesar Wang uint32_t denali_ctl[CTL_REG_NUM]; 24fe877779SCaesar Wang }; 25fe877779SCaesar Wang 26fe877779SCaesar Wang struct rk3399_ddr_publ_regs { 27*60400fc8SDerek Basehore /* 28*60400fc8SDerek Basehore * PHY registers from 0 to 511. 29*60400fc8SDerek Basehore * Only registers 0-90 of each 128 register range are used. 30*60400fc8SDerek Basehore */ 31*60400fc8SDerek Basehore uint32_t phy0[4][91]; 32*60400fc8SDerek Basehore /* 33*60400fc8SDerek Basehore * PHY registers from 512 to 895. 34*60400fc8SDerek Basehore * Only registers 0-37 of each 128 register range are used. 35*60400fc8SDerek Basehore */ 36*60400fc8SDerek Basehore uint32_t phy512[3][38]; 37*60400fc8SDerek Basehore uint32_t phy896[63]; 38fe877779SCaesar Wang }; 39fe877779SCaesar Wang 40fe877779SCaesar Wang struct rk3399_ddr_pi_regs { 41613038bcSCaesar Wang uint32_t denali_pi[PI_REG_NUM]; 42fe877779SCaesar Wang }; 43fe877779SCaesar Wang union noc_ddrtiminga0 { 44fe877779SCaesar Wang uint32_t d32; 45fe877779SCaesar Wang struct { 46fe877779SCaesar Wang unsigned acttoact : 6; 47fe877779SCaesar Wang unsigned reserved0 : 2; 48fe877779SCaesar Wang unsigned rdtomiss : 6; 49fe877779SCaesar Wang unsigned reserved1 : 2; 50fe877779SCaesar Wang unsigned wrtomiss : 6; 51fe877779SCaesar Wang unsigned reserved2 : 2; 52fe877779SCaesar Wang unsigned readlatency : 8; 53fe877779SCaesar Wang } b; 54fe877779SCaesar Wang }; 55fe877779SCaesar Wang 56fe877779SCaesar Wang union noc_ddrtimingb0 { 57fe877779SCaesar Wang uint32_t d32; 58fe877779SCaesar Wang struct { 59fe877779SCaesar Wang unsigned rdtowr : 5; 60fe877779SCaesar Wang unsigned reserved0 : 3; 61fe877779SCaesar Wang unsigned wrtord : 5; 62fe877779SCaesar Wang unsigned reserved1 : 3; 63fe877779SCaesar Wang unsigned rrd : 4; 64fe877779SCaesar Wang unsigned reserved2 : 4; 65fe877779SCaesar Wang unsigned faw : 6; 66fe877779SCaesar Wang unsigned reserved3 : 2; 67fe877779SCaesar Wang } b; 68fe877779SCaesar Wang }; 69fe877779SCaesar Wang 70fe877779SCaesar Wang union noc_ddrtimingc0 { 71fe877779SCaesar Wang uint32_t d32; 72fe877779SCaesar Wang struct { 73fe877779SCaesar Wang unsigned burstpenalty : 4; 74fe877779SCaesar Wang unsigned reserved0 : 4; 75fe877779SCaesar Wang unsigned wrtomwr : 6; 76fe877779SCaesar Wang unsigned reserved1 : 18; 77fe877779SCaesar Wang } b; 78fe877779SCaesar Wang }; 79fe877779SCaesar Wang 80fe877779SCaesar Wang union noc_devtodev0 { 81fe877779SCaesar Wang uint32_t d32; 82fe877779SCaesar Wang struct { 83fe877779SCaesar Wang unsigned busrdtord : 3; 84fe877779SCaesar Wang unsigned reserved0 : 1; 85fe877779SCaesar Wang unsigned busrdtowr : 3; 86fe877779SCaesar Wang unsigned reserved1 : 1; 87fe877779SCaesar Wang unsigned buswrtord : 3; 88fe877779SCaesar Wang unsigned reserved2 : 1; 89fe877779SCaesar Wang unsigned buswrtowr : 3; 90fe877779SCaesar Wang unsigned reserved3 : 17; 91fe877779SCaesar Wang } b; 92fe877779SCaesar Wang }; 93fe877779SCaesar Wang 94fe877779SCaesar Wang union noc_ddrmode { 95fe877779SCaesar Wang uint32_t d32; 96fe877779SCaesar Wang struct { 97fe877779SCaesar Wang unsigned autoprecharge : 1; 98fe877779SCaesar Wang unsigned bypassfiltering : 1; 99fe877779SCaesar Wang unsigned fawbank : 1; 100fe877779SCaesar Wang unsigned burstsize : 2; 101fe877779SCaesar Wang unsigned mwrsize : 2; 102fe877779SCaesar Wang unsigned reserved2 : 1; 103fe877779SCaesar Wang unsigned forceorder : 8; 104fe877779SCaesar Wang unsigned forceorderstate : 8; 105fe877779SCaesar Wang unsigned reserved3 : 8; 106fe877779SCaesar Wang } b; 107fe877779SCaesar Wang }; 108fe877779SCaesar Wang 109fe877779SCaesar Wang struct rk3399_msch_timings { 110fe877779SCaesar Wang union noc_ddrtiminga0 ddrtiminga0; 111fe877779SCaesar Wang union noc_ddrtimingb0 ddrtimingb0; 112fe877779SCaesar Wang union noc_ddrtimingc0 ddrtimingc0; 113fe877779SCaesar Wang union noc_devtodev0 devtodev0; 114fe877779SCaesar Wang union noc_ddrmode ddrmode; 115fe877779SCaesar Wang uint32_t agingx0; 116fe877779SCaesar Wang }; 117613038bcSCaesar Wang 118fe877779SCaesar Wang struct rk3399_sdram_channel { 119fe877779SCaesar Wang unsigned char rank; 120fe877779SCaesar Wang /* col = 0, means this channel is invalid */ 121fe877779SCaesar Wang unsigned char col; 122fe877779SCaesar Wang /* 3:8bank, 2:4bank */ 123fe877779SCaesar Wang unsigned char bk; 124fe877779SCaesar Wang /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ 125fe877779SCaesar Wang unsigned char bw; 126fe877779SCaesar Wang /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ 127fe877779SCaesar Wang unsigned char dbw; 128fe877779SCaesar Wang /* row_3_4 = 1: 6Gb or 12Gb die 129fe877779SCaesar Wang * row_3_4 = 0: normal die, power of 2 130fe877779SCaesar Wang */ 131fe877779SCaesar Wang unsigned char row_3_4; 132fe877779SCaesar Wang unsigned char cs0_row; 133fe877779SCaesar Wang unsigned char cs1_row; 134fe877779SCaesar Wang uint32_t ddrconfig; 135fe877779SCaesar Wang struct rk3399_msch_timings noc_timings; 136fe877779SCaesar Wang }; 137fe877779SCaesar Wang 138fe877779SCaesar Wang struct rk3399_sdram_params { 139fe877779SCaesar Wang struct rk3399_sdram_channel ch[2]; 140fe877779SCaesar Wang uint32_t ddr_freq; 141fe877779SCaesar Wang unsigned char dramtype; 142fe877779SCaesar Wang unsigned char num_channels; 143fe877779SCaesar Wang unsigned char stride; 144fe877779SCaesar Wang unsigned char odt; 145fe877779SCaesar Wang struct rk3399_ddr_pctl_regs pctl_regs; 146fe877779SCaesar Wang struct rk3399_ddr_pi_regs pi_regs; 147fe877779SCaesar Wang struct rk3399_ddr_publ_regs phy_regs; 148951752ddSDerek Basehore uint32_t rx_cal_dqs[2][4]; 149fe877779SCaesar Wang }; 150fe877779SCaesar Wang 151613038bcSCaesar Wang extern __sramdata struct rk3399_sdram_params sdram_config; 152fe877779SCaesar Wang 153613038bcSCaesar Wang void dram_init(void); 154fe877779SCaesar Wang 155fe877779SCaesar Wang #endif 156