1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <debug.h> 32 #include <mmio.h> 33 #include <plat_private.h> 34 #include "dram.h" 35 #include "dram_spec_timing.h" 36 #include "string.h" 37 #include "soc.h" 38 #include "pmu.h" 39 40 #include <delay_timer.h> 41 42 #define CTL_TRAINING (1) 43 #define PI_TRAINING (!CTL_TRAINING) 44 45 #define EN_READ_GATE_TRAINING (1) 46 #define EN_CA_TRAINING (0) 47 #define EN_WRITE_LEVELING (0) 48 #define EN_READ_LEVELING (0) 49 #define EN_WDQ_LEVELING (0) 50 51 #define ENPER_CS_TRAINING_FREQ (933) 52 53 struct pll_div { 54 unsigned int mhz; 55 unsigned int refdiv; 56 unsigned int fbdiv; 57 unsigned int postdiv1; 58 unsigned int postdiv2; 59 unsigned int frac; 60 unsigned int freq; 61 }; 62 63 static const struct pll_div dpll_rates_table[] = { 64 65 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2 */ 66 {.mhz = 933, .refdiv = 3, .fbdiv = 350, .postdiv1 = 3, .postdiv2 = 1}, 67 {.mhz = 800, .refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}, 68 {.mhz = 732, .refdiv = 1, .fbdiv = 61, .postdiv1 = 2, .postdiv2 = 1}, 69 {.mhz = 666, .refdiv = 1, .fbdiv = 111, .postdiv1 = 4, .postdiv2 = 1}, 70 {.mhz = 600, .refdiv = 1, .fbdiv = 50, .postdiv1 = 2, .postdiv2 = 1}, 71 {.mhz = 528, .refdiv = 1, .fbdiv = 66, .postdiv1 = 3, .postdiv2 = 1}, 72 {.mhz = 400, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}, 73 {.mhz = 300, .refdiv = 1, .fbdiv = 50, .postdiv1 = 4, .postdiv2 = 1}, 74 {.mhz = 200, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 2}, 75 }; 76 77 static struct rk3399_ddr_cic_regs *const rk3399_ddr_cic = (void *)CIC_BASE; 78 static struct rk3399_ddr_pctl_regs *const rk3399_ddr_pctl[2] = { 79 (void *)DDRC0_BASE, (void *)DDRC1_BASE 80 }; 81 82 static struct rk3399_ddr_pi_regs *const rk3399_ddr_pi[2] = { 83 (void *)DDRC0_PI_BASE, (void *)DDRC1_PI_BASE 84 }; 85 86 static struct rk3399_ddr_publ_regs *const rk3399_ddr_publ[2] = { 87 (void *)DDRC0_PHY_BASE, (void *)DDRC1_PHY_BASE 88 }; 89 90 struct rk3399_dram_status { 91 uint32_t current_index; 92 uint32_t index_freq[2]; 93 struct timing_related_config timing_config; 94 struct drv_odt_lp_config drv_odt_lp_cfg; 95 }; 96 97 static struct rk3399_dram_status rk3399_dram_status; 98 static struct ddr_dts_config_timing dts_parameter = { 99 .available = 0 100 }; 101 102 static struct rk3399_sdram_default_config ddr3_default_config = { 103 .bl = 8, 104 .ap = 0, 105 .dramds = 40, 106 .dramodt = 120, 107 .burst_ref_cnt = 1, 108 .zqcsi = 0 109 }; 110 111 static struct drv_odt_lp_config ddr3_drv_odt_default_config = { 112 .ddr3_speed_bin = DDR3_DEFAULT, 113 .pd_idle = 0, 114 .sr_idle = 0, 115 .sr_mc_gate_idle = 0, 116 .srpd_lite_idle = 0, 117 .standby_idle = 0, 118 119 .ddr3_dll_dis_freq = 300, 120 .phy_dll_dis_freq = 125, 121 .odt_dis_freq = 933, 122 123 .dram_side_drv = 40, 124 .dram_side_dq_odt = 120, 125 .dram_side_ca_odt = 120, 126 127 .phy_side_ca_drv = 40, 128 .phy_side_ck_cs_drv = 40, 129 .phy_side_dq_drv = 40, 130 .phy_side_odt = 240, 131 }; 132 133 static struct rk3399_sdram_default_config lpddr3_default_config = { 134 .bl = 8, 135 .ap = 0, 136 .dramds = 34, 137 .dramodt = 240, 138 .burst_ref_cnt = 1, 139 .zqcsi = 0 140 }; 141 142 static struct drv_odt_lp_config lpddr3_drv_odt_default_config = { 143 .ddr3_speed_bin = DDR3_DEFAULT, 144 .pd_idle = 0, 145 .sr_idle = 0, 146 .sr_mc_gate_idle = 0, 147 .srpd_lite_idle = 0, 148 .standby_idle = 0, 149 150 .ddr3_dll_dis_freq = 300, 151 .phy_dll_dis_freq = 125, 152 .odt_dis_freq = 666, 153 154 .dram_side_drv = 40, 155 .dram_side_dq_odt = 120, 156 .dram_side_ca_odt = 120, 157 158 .phy_side_ca_drv = 40, 159 .phy_side_ck_cs_drv = 40, 160 .phy_side_dq_drv = 40, 161 .phy_side_odt = 240, 162 }; 163 164 static struct rk3399_sdram_default_config lpddr4_default_config = { 165 .bl = 16, 166 .ap = 0, 167 .dramds = 40, 168 .dramodt = 240, 169 .caodt = 240, 170 .burst_ref_cnt = 1, 171 .zqcsi = 0 172 }; 173 174 static struct drv_odt_lp_config lpddr4_drv_odt_default_config = { 175 .ddr3_speed_bin = DDR3_DEFAULT, 176 .pd_idle = 0, 177 .sr_idle = 0, 178 .sr_mc_gate_idle = 0, 179 .srpd_lite_idle = 0, 180 .standby_idle = 0, 181 182 .ddr3_dll_dis_freq = 300, 183 .phy_dll_dis_freq = 125, 184 .odt_dis_freq = 933, 185 186 .dram_side_drv = 60, 187 .dram_side_dq_odt = 40, 188 .dram_side_ca_odt = 40, 189 190 .phy_side_ca_drv = 40, 191 .phy_side_ck_cs_drv = 80, 192 .phy_side_dq_drv = 80, 193 .phy_side_odt = 60, 194 }; 195 196 uint32_t dcf_code[] = { 197 #include "dcf_code.inc" 198 }; 199 200 201 #define write_32(addr, value)\ 202 mmio_write_32((uintptr_t)(addr), (uint32_t)(value)) 203 204 #define read_32(addr) \ 205 mmio_read_32((uintptr_t)(addr)) 206 #define clrbits_32(addr, clear)\ 207 mmio_clrbits_32((uintptr_t)(addr), (uint32_t)(clear)) 208 #define setbits_32(addr, set)\ 209 mmio_setbits_32((uintptr_t)(addr), (uint32_t)(set)) 210 #define clrsetbits_32(addr, clear, set)\ 211 mmio_clrsetbits_32((uintptr_t)(addr), (uint32_t)(clear),\ 212 (uint32_t)(set)) 213 214 #define DCF_START_ADDR (SRAM_BASE + 0x1400) 215 #define DCF_PARAM_ADDR (SRAM_BASE + 0x1000) 216 217 /* DCF_PAMET */ 218 #define PARAM_DRAM_FREQ (0) 219 #define PARAM_DPLL_CON0 (4) 220 #define PARAM_DPLL_CON1 (8) 221 #define PARAM_DPLL_CON2 (0xc) 222 #define PARAM_DPLL_CON3 (0x10) 223 #define PARAM_DPLL_CON4 (0x14) 224 #define PARAM_DPLL_CON5 (0x18) 225 /* equal to fn<<4 */ 226 #define PARAM_FREQ_SELECT (0x1c) 227 228 static unsigned int get_cs_die_capability(struct rk3399_sdram_config 229 *psdram_config, unsigned int channel, 230 unsigned int cs) 231 { 232 unsigned int die; 233 unsigned int cs_cap; 234 unsigned int row[2]; 235 236 row[0] = psdram_config->ch[channel].cs0_row; 237 row[1] = psdram_config->ch[channel].cs1_row; 238 die = psdram_config->ch[channel].bus_width / 239 psdram_config->ch[channel].each_die_bus_width; 240 cs_cap = (1 << (row[cs] + 241 (psdram_config->ch[channel].bank / 4 + 1) + 242 psdram_config->ch[channel].col + 243 (psdram_config->ch[channel].bus_width / 16))); 244 if (psdram_config->ch[channel].each_die_6gb_or_12gb) 245 cs_cap = cs_cap * 3 / 4; 246 247 return (cs_cap / die); 248 } 249 250 static void sdram_config_init(struct rk3399_sdram_config *psdram_config) 251 { 252 uint32_t os_reg2_val, i; 253 254 os_reg2_val = read_32(PMUGRF_BASE + PMUGRF_OSREG(2)); 255 256 for (i = 0; i < READ_CH_CNT(os_reg2_val); i++) { 257 psdram_config->ch[i].bank = 1 << READ_BK_INFO(os_reg2_val, i); 258 psdram_config->ch[i].bus_width = 259 8 * (1 << READ_BW_INFO(os_reg2_val, i)); 260 psdram_config->ch[i].col = READ_COL_INFO(os_reg2_val, i); 261 psdram_config->ch[i].cs0_row = 262 READ_CS0_ROW_INFO(os_reg2_val, i); 263 psdram_config->ch[i].cs1_row = 264 READ_CS1_ROW_INFO(os_reg2_val, i); 265 psdram_config->ch[i].cs_cnt = READ_CS_INFO(os_reg2_val, i); 266 psdram_config->ch[i].each_die_6gb_or_12gb = 267 READ_CH_ROW_INFO(os_reg2_val, i); 268 psdram_config->ch[i].each_die_bus_width = 269 8 * (1 << READ_DIE_BW_INFO(os_reg2_val, i)); 270 } 271 psdram_config->dramtype = READ_DRAMTYPE_INFO(os_reg2_val); 272 psdram_config->channal_num = READ_CH_CNT(os_reg2_val); 273 } 274 275 static void drv_odt_lp_cfg_init(uint32_t dram_type, 276 struct ddr_dts_config_timing *dts_timing, 277 struct drv_odt_lp_config *drv_config) 278 { 279 if ((dts_timing) && (dts_timing->available)) { 280 drv_config->ddr3_speed_bin = dts_timing->ddr3_speed_bin; 281 drv_config->pd_idle = dts_timing->pd_idle; 282 drv_config->sr_idle = dts_timing->sr_idle; 283 drv_config->sr_mc_gate_idle = dts_timing->sr_mc_gate_idle; 284 drv_config->srpd_lite_idle = dts_timing->srpd_lite_idle; 285 drv_config->standby_idle = dts_timing->standby_idle; 286 drv_config->ddr3_dll_dis_freq = dts_timing->ddr3_dll_dis_freq; 287 drv_config->phy_dll_dis_freq = dts_timing->phy_dll_dis_freq; 288 } 289 290 switch (dram_type) { 291 case DDR3: 292 if ((dts_timing) && (dts_timing->available)) { 293 drv_config->odt_dis_freq = 294 dts_timing->ddr3_odt_dis_freq; 295 drv_config->dram_side_drv = dts_timing->ddr3_drv; 296 drv_config->dram_side_dq_odt = dts_timing->ddr3_odt; 297 drv_config->phy_side_ca_drv = 298 dts_timing->phy_ddr3_ca_drv; 299 drv_config->phy_side_ck_cs_drv = 300 dts_timing->phy_ddr3_ca_drv; 301 drv_config->phy_side_dq_drv = 302 dts_timing->phy_ddr3_dq_drv; 303 drv_config->phy_side_odt = dts_timing->phy_ddr3_odt; 304 } else { 305 memcpy(drv_config, &ddr3_drv_odt_default_config, 306 sizeof(struct drv_odt_lp_config)); 307 } 308 break; 309 case LPDDR3: 310 if ((dts_timing) && (dts_timing->available)) { 311 drv_config->odt_dis_freq = 312 dts_timing->lpddr3_odt_dis_freq; 313 drv_config->dram_side_drv = dts_timing->lpddr3_drv; 314 drv_config->dram_side_dq_odt = dts_timing->lpddr3_odt; 315 drv_config->phy_side_ca_drv = 316 dts_timing->phy_lpddr3_ca_drv; 317 drv_config->phy_side_ck_cs_drv = 318 dts_timing->phy_lpddr3_ca_drv; 319 drv_config->phy_side_dq_drv = 320 dts_timing->phy_lpddr3_dq_drv; 321 drv_config->phy_side_odt = dts_timing->phy_lpddr3_odt; 322 323 } else { 324 memcpy(drv_config, &lpddr3_drv_odt_default_config, 325 sizeof(struct drv_odt_lp_config)); 326 } 327 break; 328 case LPDDR4: 329 default: 330 if ((dts_timing) && (dts_timing->available)) { 331 drv_config->odt_dis_freq = 332 dts_timing->lpddr4_odt_dis_freq; 333 drv_config->dram_side_drv = dts_timing->lpddr4_drv; 334 drv_config->dram_side_dq_odt = 335 dts_timing->lpddr4_dq_odt; 336 drv_config->dram_side_ca_odt = 337 dts_timing->lpddr4_ca_odt; 338 drv_config->phy_side_ca_drv = 339 dts_timing->phy_lpddr4_ca_drv; 340 drv_config->phy_side_ck_cs_drv = 341 dts_timing->phy_lpddr4_ck_cs_drv; 342 drv_config->phy_side_dq_drv = 343 dts_timing->phy_lpddr4_dq_drv; 344 drv_config->phy_side_odt = dts_timing->phy_lpddr4_odt; 345 } else { 346 memcpy(drv_config, &lpddr4_drv_odt_default_config, 347 sizeof(struct drv_odt_lp_config)); 348 } 349 break; 350 } 351 352 switch (drv_config->phy_side_ca_drv) { 353 case 240: 354 drv_config->phy_side_ca_drv = PHY_DRV_ODT_240; 355 break; 356 case 120: 357 drv_config->phy_side_ca_drv = PHY_DRV_ODT_120; 358 break; 359 case 80: 360 drv_config->phy_side_ca_drv = PHY_DRV_ODT_80; 361 break; 362 case 60: 363 drv_config->phy_side_ca_drv = PHY_DRV_ODT_60; 364 break; 365 case 48: 366 drv_config->phy_side_ca_drv = PHY_DRV_ODT_48; 367 break; 368 case 40: 369 drv_config->phy_side_ca_drv = PHY_DRV_ODT_40; 370 break; 371 default: 372 drv_config->phy_side_ca_drv = PHY_DRV_ODT_34_3; 373 break; 374 }; 375 376 switch (drv_config->phy_side_ck_cs_drv) { 377 case 240: 378 drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_240; 379 break; 380 case 120: 381 drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_120; 382 break; 383 case 80: 384 drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_80; 385 break; 386 case 60: 387 drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_60; 388 break; 389 case 48: 390 drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_48; 391 break; 392 case 40: 393 drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_40; 394 break; 395 default: 396 drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_34_3; 397 break; 398 } 399 400 switch (drv_config->phy_side_dq_drv) { 401 case 240: 402 drv_config->phy_side_dq_drv = PHY_DRV_ODT_240; 403 break; 404 case 120: 405 drv_config->phy_side_dq_drv = PHY_DRV_ODT_120; 406 break; 407 case 80: 408 drv_config->phy_side_dq_drv = PHY_DRV_ODT_80; 409 break; 410 case 60: 411 drv_config->phy_side_dq_drv = PHY_DRV_ODT_60; 412 break; 413 case 48: 414 drv_config->phy_side_dq_drv = PHY_DRV_ODT_48; 415 break; 416 case 40: 417 drv_config->phy_side_dq_drv = PHY_DRV_ODT_40; 418 break; 419 default: 420 drv_config->phy_side_dq_drv = PHY_DRV_ODT_34_3; 421 break; 422 } 423 424 switch (drv_config->phy_side_odt) { 425 case 240: 426 drv_config->phy_side_odt = PHY_DRV_ODT_240; 427 break; 428 case 120: 429 drv_config->phy_side_odt = PHY_DRV_ODT_120; 430 break; 431 case 80: 432 drv_config->phy_side_odt = PHY_DRV_ODT_80; 433 break; 434 case 60: 435 drv_config->phy_side_odt = PHY_DRV_ODT_60; 436 break; 437 case 48: 438 drv_config->phy_side_odt = PHY_DRV_ODT_48; 439 break; 440 case 40: 441 drv_config->phy_side_odt = PHY_DRV_ODT_40; 442 break; 443 default: 444 drv_config->phy_side_odt = PHY_DRV_ODT_34_3; 445 break; 446 } 447 } 448 449 static void sdram_timing_cfg_init(struct timing_related_config *ptiming_config, 450 struct rk3399_sdram_config *psdram_config, 451 struct drv_odt_lp_config *drv_config) 452 { 453 uint32_t i, j; 454 455 for (i = 0; i < psdram_config->channal_num; i++) { 456 ptiming_config->dram_info[i].speed_rate = 457 drv_config->ddr3_speed_bin; 458 ptiming_config->dram_info[i].cs_cnt = 459 psdram_config->ch[i].cs_cnt; 460 for (j = 0; j < psdram_config->ch[i].cs_cnt; j++) { 461 ptiming_config->dram_info[i].per_die_capability[j] = 462 get_cs_die_capability(psdram_config, i, j); 463 } 464 } 465 ptiming_config->dram_type = psdram_config->dramtype; 466 ptiming_config->ch_cnt = psdram_config->channal_num; 467 switch (psdram_config->dramtype) { 468 case DDR3: 469 ptiming_config->bl = ddr3_default_config.bl; 470 ptiming_config->ap = ddr3_default_config.ap; 471 break; 472 case LPDDR3: 473 ptiming_config->bl = lpddr3_default_config.bl; 474 ptiming_config->ap = lpddr3_default_config.ap; 475 break; 476 case LPDDR4: 477 ptiming_config->bl = lpddr4_default_config.bl; 478 ptiming_config->ap = lpddr4_default_config.ap; 479 ptiming_config->rdbi = 0; 480 ptiming_config->wdbi = 0; 481 break; 482 } 483 ptiming_config->dramds = drv_config->dram_side_drv; 484 ptiming_config->dramodt = drv_config->dram_side_dq_odt; 485 ptiming_config->caodt = drv_config->dram_side_ca_odt; 486 } 487 488 struct lat_adj_pair { 489 uint32_t cl; 490 uint32_t rdlat_adj; 491 uint32_t cwl; 492 uint32_t wrlat_adj; 493 }; 494 495 const struct lat_adj_pair ddr3_lat_adj[] = { 496 {6, 5, 5, 4}, 497 {8, 7, 6, 5}, 498 {10, 9, 7, 6}, 499 {11, 9, 8, 7}, 500 {13, 0xb, 9, 8}, 501 {14, 0xb, 0xa, 9} 502 }; 503 504 const struct lat_adj_pair lpddr3_lat_adj[] = { 505 {3, 2, 1, 0}, 506 {6, 5, 3, 2}, 507 {8, 7, 4, 3}, 508 {9, 8, 5, 4}, 509 {10, 9, 6, 5}, 510 {11, 9, 6, 5}, 511 {12, 0xa, 6, 5}, 512 {14, 0xc, 8, 7}, 513 {16, 0xd, 8, 7} 514 }; 515 516 const struct lat_adj_pair lpddr4_lat_adj[] = { 517 {6, 5, 4, 2}, 518 {10, 9, 6, 4}, 519 {14, 0xc, 8, 6}, 520 {20, 0x11, 0xa, 8}, 521 {24, 0x15, 0xc, 0xa}, 522 {28, 0x18, 0xe, 0xc}, 523 {32, 0x1b, 0x10, 0xe}, 524 {36, 0x1e, 0x12, 0x10} 525 }; 526 527 static uint32_t get_rdlat_adj(uint32_t dram_type, uint32_t cl) 528 { 529 const struct lat_adj_pair *p; 530 uint32_t cnt; 531 uint32_t i; 532 533 if (dram_type == DDR3) { 534 p = ddr3_lat_adj; 535 cnt = ARRAY_SIZE(ddr3_lat_adj); 536 } else if (dram_type == LPDDR3) { 537 p = lpddr3_lat_adj; 538 cnt = ARRAY_SIZE(lpddr3_lat_adj); 539 } else { 540 p = lpddr4_lat_adj; 541 cnt = ARRAY_SIZE(lpddr4_lat_adj); 542 } 543 544 for (i = 0; i < cnt; i++) { 545 if (cl == p[i].cl) 546 return p[i].rdlat_adj; 547 } 548 /* fail */ 549 return 0xff; 550 } 551 552 static uint32_t get_wrlat_adj(uint32_t dram_type, uint32_t cwl) 553 { 554 const struct lat_adj_pair *p; 555 uint32_t cnt; 556 uint32_t i; 557 558 if (dram_type == DDR3) { 559 p = ddr3_lat_adj; 560 cnt = ARRAY_SIZE(ddr3_lat_adj); 561 } else if (dram_type == LPDDR3) { 562 p = lpddr3_lat_adj; 563 cnt = ARRAY_SIZE(lpddr3_lat_adj); 564 } else { 565 p = lpddr4_lat_adj; 566 cnt = ARRAY_SIZE(lpddr4_lat_adj); 567 } 568 569 for (i = 0; i < cnt; i++) { 570 if (cwl == p[i].cwl) 571 return p[i].wrlat_adj; 572 } 573 /* fail */ 574 return 0xff; 575 } 576 577 #define PI_REGS_DIMM_SUPPORT (0) 578 #define PI_ADD_LATENCY (0) 579 #define PI_DOUBLEFREEK (1) 580 581 #define PI_PAD_DELAY_PS_VALUE (1000) 582 #define PI_IE_ENABLE_VALUE (3000) 583 #define PI_TSEL_ENABLE_VALUE (700) 584 585 static uint32_t get_pi_rdlat_adj(struct dram_timing_t *pdram_timing) 586 { 587 /*[DLLSUBTYPE2] == "STD_DENALI_HS" */ 588 uint32_t rdlat, delay_adder, ie_enable, hs_offset, tsel_adder, 589 extra_adder, tsel_enable; 590 591 ie_enable = PI_IE_ENABLE_VALUE; 592 tsel_enable = PI_TSEL_ENABLE_VALUE; 593 594 rdlat = pdram_timing->cl + PI_ADD_LATENCY; 595 delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 596 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 597 delay_adder++; 598 hs_offset = 0; 599 tsel_adder = 0; 600 extra_adder = 0; 601 /* rdlat = rdlat - (PREAMBLE_SUPPORT & 0x1); */ 602 tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz); 603 if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0) 604 tsel_adder++; 605 delay_adder = delay_adder - 1; 606 if (tsel_adder > delay_adder) 607 extra_adder = tsel_adder - delay_adder; 608 else 609 extra_adder = 0; 610 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 611 hs_offset = 2; 612 else 613 hs_offset = 1; 614 615 if (delay_adder > (rdlat - 1 - hs_offset)) { 616 rdlat = rdlat - tsel_adder; 617 } else { 618 if ((rdlat - delay_adder) < 2) 619 rdlat = 2; 620 else 621 rdlat = rdlat - delay_adder - extra_adder; 622 } 623 624 return rdlat; 625 } 626 627 static uint32_t get_pi_wrlat(struct dram_timing_t *pdram_timing, 628 struct timing_related_config *timing_config) 629 { 630 uint32_t tmp; 631 632 if (timing_config->dram_type == LPDDR3) { 633 tmp = pdram_timing->cl; 634 if (tmp >= 14) 635 tmp = 8; 636 else if (tmp >= 10) 637 tmp = 6; 638 else if (tmp == 9) 639 tmp = 5; 640 else if (tmp == 8) 641 tmp = 4; 642 else if (tmp == 6) 643 tmp = 3; 644 else 645 tmp = 1; 646 } else { 647 tmp = 1; 648 } 649 650 return tmp; 651 } 652 653 static uint32_t get_pi_wrlat_adj(struct dram_timing_t *pdram_timing, 654 struct timing_related_config *timing_config) 655 { 656 return get_pi_wrlat(pdram_timing, timing_config) + PI_ADD_LATENCY - 1; 657 } 658 659 static uint32_t get_pi_tdfi_phy_rdlat(struct dram_timing_t *pdram_timing, 660 struct timing_related_config *timing_config) 661 { 662 /* [DLLSUBTYPE2] == "STD_DENALI_HS" */ 663 uint32_t cas_lat, delay_adder, ie_enable, hs_offset, ie_delay_adder; 664 uint32_t mem_delay_ps, round_trip_ps; 665 uint32_t phy_internal_delay, lpddr_adder, dfi_adder, rdlat_delay; 666 667 ie_enable = PI_IE_ENABLE_VALUE; 668 669 delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 670 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 671 delay_adder++; 672 delay_adder = delay_adder - 1; 673 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 674 hs_offset = 2; 675 else 676 hs_offset = 1; 677 678 cas_lat = pdram_timing->cl + PI_ADD_LATENCY; 679 680 if (delay_adder > (cas_lat - 1 - hs_offset)) { 681 ie_delay_adder = 0; 682 } else { 683 ie_delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 684 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 685 ie_delay_adder++; 686 } 687 688 if (timing_config->dram_type == DDR3) { 689 mem_delay_ps = 0; 690 } else if (timing_config->dram_type == LPDDR4) { 691 mem_delay_ps = 3600; 692 } else if (timing_config->dram_type == LPDDR3) { 693 mem_delay_ps = 5500; 694 } else { 695 printf("get_pi_tdfi_phy_rdlat:dramtype unsupport\n"); 696 return 0; 697 } 698 round_trip_ps = 1100 + 500 + mem_delay_ps + 500 + 600; 699 delay_adder = round_trip_ps / (1000000 / pdram_timing->mhz); 700 if ((round_trip_ps % (1000000 / pdram_timing->mhz)) != 0) 701 delay_adder++; 702 703 phy_internal_delay = 5 + 2 + 4; 704 lpddr_adder = mem_delay_ps / (1000000 / pdram_timing->mhz); 705 if ((mem_delay_ps % (1000000 / pdram_timing->mhz)) != 0) 706 lpddr_adder++; 707 dfi_adder = 0; 708 phy_internal_delay = phy_internal_delay + 2; 709 rdlat_delay = delay_adder + phy_internal_delay + 710 ie_delay_adder + lpddr_adder + dfi_adder; 711 712 rdlat_delay = rdlat_delay + 2; 713 return rdlat_delay; 714 } 715 716 static uint32_t get_pi_todtoff_min(struct dram_timing_t *pdram_timing, 717 struct timing_related_config *timing_config) 718 { 719 uint32_t tmp, todtoff_min_ps; 720 721 if (timing_config->dram_type == LPDDR3) 722 todtoff_min_ps = 2500; 723 else if (timing_config->dram_type == LPDDR4) 724 todtoff_min_ps = 1500; 725 else 726 todtoff_min_ps = 0; 727 /* todtoff_min */ 728 tmp = todtoff_min_ps / (1000000 / pdram_timing->mhz); 729 if ((todtoff_min_ps % (1000000 / pdram_timing->mhz)) != 0) 730 tmp++; 731 return tmp; 732 } 733 734 static uint32_t get_pi_todtoff_max(struct dram_timing_t *pdram_timing, 735 struct timing_related_config *timing_config) 736 { 737 uint32_t tmp, todtoff_max_ps; 738 739 if ((timing_config->dram_type == LPDDR4) 740 || (timing_config->dram_type == LPDDR3)) 741 todtoff_max_ps = 3500; 742 else 743 todtoff_max_ps = 0; 744 745 /* todtoff_max */ 746 tmp = todtoff_max_ps / (1000000 / pdram_timing->mhz); 747 if ((todtoff_max_ps % (1000000 / pdram_timing->mhz)) != 0) 748 tmp++; 749 return tmp; 750 } 751 752 static void gen_rk3399_ctl_params_f0(struct timing_related_config 753 *timing_config, 754 struct dram_timing_t *pdram_timing) 755 { 756 uint32_t i; 757 uint32_t tmp, tmp1; 758 759 for (i = 0; i < timing_config->ch_cnt; i++) { 760 if (timing_config->dram_type == DDR3) { 761 tmp = ((700000 + 10) * timing_config->freq + 762 999) / 1000; 763 tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) + 764 pdram_timing->tmod + pdram_timing->tzqinit; 765 write_32(&rk3399_ddr_pctl[i]->denali_ctl[5], tmp); 766 767 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[22], 768 0xffff, pdram_timing->tdllk); 769 770 write_32(&rk3399_ddr_pctl[i]->denali_ctl[32], 771 (pdram_timing->tmod << 8) | 772 pdram_timing->tmrd); 773 774 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[59], 775 0xffff << 16, 776 (pdram_timing->txsr - 777 pdram_timing->trcd) << 16); 778 } else if (timing_config->dram_type == LPDDR4) { 779 write_32(&rk3399_ddr_pctl[i]->denali_ctl[5], 780 pdram_timing->tinit1 + pdram_timing->tinit3); 781 write_32(&rk3399_ddr_pctl[i]->denali_ctl[32], 782 (pdram_timing->tmrd << 8) | 783 pdram_timing->tmrd); 784 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[59], 785 0xffff << 16, pdram_timing->txsr << 16); 786 } else { 787 write_32(&rk3399_ddr_pctl[i]->denali_ctl[5], 788 pdram_timing->tinit1); 789 write_32(&rk3399_ddr_pctl[i]->denali_ctl[7], 790 pdram_timing->tinit4); 791 write_32(&rk3399_ddr_pctl[i]->denali_ctl[32], 792 (pdram_timing->tmrd << 8) | 793 pdram_timing->tmrd); 794 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[59], 795 0xffff << 16, pdram_timing->txsr << 16); 796 } 797 write_32(&rk3399_ddr_pctl[i]->denali_ctl[6], 798 pdram_timing->tinit3); 799 write_32(&rk3399_ddr_pctl[i]->denali_ctl[8], 800 pdram_timing->tinit5); 801 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[23], (0x7f << 16), 802 ((pdram_timing->cl * 2) << 16)); 803 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[23], (0x1f << 24), 804 (pdram_timing->cwl << 24)); 805 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[24], 0x3f, 806 pdram_timing->al); 807 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[26], 0xffff << 16, 808 (pdram_timing->trc << 24) | 809 (pdram_timing->trrd << 16)); 810 write_32(&rk3399_ddr_pctl[i]->denali_ctl[27], 811 (pdram_timing->tfaw << 24) | 812 (pdram_timing->trppb << 16) | 813 (pdram_timing->twtr << 8) | pdram_timing->tras_min); 814 815 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[31], 0xff << 24, 816 max(4, pdram_timing->trtp) << 24); 817 write_32(&rk3399_ddr_pctl[i]->denali_ctl[33], 818 (pdram_timing->tcke << 24) | pdram_timing->tras_max); 819 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[34], 0xff, 820 max(1, pdram_timing->tckesr)); 821 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[39], 822 (0x3f << 16) | (0xff << 8), 823 (pdram_timing->twr << 16) | 824 (pdram_timing->trcd << 8)); 825 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[42], 0x1f << 16, 826 pdram_timing->tmrz << 16); 827 tmp = pdram_timing->tdal ? pdram_timing->tdal : 828 (pdram_timing->twr + pdram_timing->trp); 829 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[44], 0xff, tmp); 830 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[45], 0xff, 831 pdram_timing->trp); 832 write_32(&rk3399_ddr_pctl[i]->denali_ctl[48], 833 ((pdram_timing->trefi - 8) << 16) | 834 pdram_timing->trfc); 835 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[52], 0xffff, 836 pdram_timing->txp); 837 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[53], 0xffff << 16, 838 pdram_timing->txpdll << 16); 839 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[55], 0xf << 24, 840 pdram_timing->tcscke << 24); 841 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[55], 0xff, 842 pdram_timing->tmrri); 843 write_32(&rk3399_ddr_pctl[i]->denali_ctl[56], 844 (pdram_timing->tzqcke << 24) | 845 (pdram_timing->tmrwckel << 16) | 846 (pdram_timing->tckehcs << 8) | pdram_timing->tckelcs); 847 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[60], 0xffff, 848 pdram_timing->txsnr); 849 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[62], 0xffff << 16, 850 (pdram_timing->tckehcmd << 24) | 851 (pdram_timing->tckelcmd << 16)); 852 write_32(&rk3399_ddr_pctl[i]->denali_ctl[63], 853 (pdram_timing->tckelpd << 24) | 854 (pdram_timing->tescke << 16) | 855 (pdram_timing->tsr << 8) | pdram_timing->tckckel); 856 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[64], 0xfff, 857 (pdram_timing->tcmdcke << 8) | 858 pdram_timing->tcsckeh); 859 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[92], 860 (0xffff << 8), 861 (pdram_timing->tcksrx << 16) | 862 (pdram_timing->tcksre << 8)); 863 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[108], (0x1 << 24), 864 (timing_config->dllbp << 24)); 865 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[122], 866 (0x3FF << 16), 867 (pdram_timing->tvrcg_enable << 16)); 868 write_32(&rk3399_ddr_pctl[i]->denali_ctl[123], 869 (pdram_timing->tfc_long << 16) | 870 pdram_timing->tvrcg_disable); 871 write_32(&rk3399_ddr_pctl[i]->denali_ctl[124], 872 (pdram_timing->tvref_long << 16) | 873 (pdram_timing->tckfspx << 8) | 874 pdram_timing->tckfspe); 875 write_32(&rk3399_ddr_pctl[i]->denali_ctl[133], 876 (pdram_timing->mr[1] << 16) | pdram_timing->mr[0]); 877 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[134], 0xffff, 878 pdram_timing->mr[2]); 879 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[138], 0xffff, 880 pdram_timing->mr[3]); 881 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[139], 0xff << 24, 882 pdram_timing->mr11 << 24); 883 write_32(&rk3399_ddr_pctl[i]->denali_ctl[147], 884 (pdram_timing->mr[1] << 16) | pdram_timing->mr[0]); 885 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[148], 0xffff, 886 pdram_timing->mr[2]); 887 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[152], 0xffff, 888 pdram_timing->mr[3]); 889 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[153], 0xff << 24, 890 pdram_timing->mr11 << 24); 891 if (timing_config->dram_type == LPDDR4) { 892 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[140], 893 0xffff << 16, pdram_timing->mr12 << 16); 894 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[142], 895 0xffff << 16, pdram_timing->mr14 << 16); 896 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[145], 897 0xffff << 16, pdram_timing->mr22 << 16); 898 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[154], 899 0xffff << 16, pdram_timing->mr12 << 16); 900 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[156], 901 0xffff << 16, pdram_timing->mr14 << 16); 902 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[159], 903 0xffff << 16, pdram_timing->mr22 << 16); 904 } 905 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[179], 0xfff << 8, 906 pdram_timing->tzqinit << 8); 907 write_32(&rk3399_ddr_pctl[i]->denali_ctl[180], 908 (pdram_timing->tzqcs << 16) | 909 (pdram_timing->tzqinit / 2)); 910 write_32(&rk3399_ddr_pctl[i]->denali_ctl[181], 911 (pdram_timing->tzqlat << 16) | pdram_timing->tzqcal); 912 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[212], 0xff << 8, 913 pdram_timing->todton << 8); 914 915 if (timing_config->odt) { 916 setbits_32(&rk3399_ddr_pctl[i]->denali_ctl[213], 917 1 << 16); 918 if (timing_config->freq < 400) 919 tmp = 4 << 24; 920 else 921 tmp = 8 << 24; 922 } else { 923 clrbits_32(&rk3399_ddr_pctl[i]->denali_ctl[213], 924 1 << 16); 925 tmp = 2 << 24; 926 } 927 928 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[216], 929 0x1f << 24, tmp); 930 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[221], 931 (0x3 << 16) | (0xf << 8), 932 (pdram_timing->tdqsck << 16) | 933 (pdram_timing->tdqsck_max << 8)); 934 tmp = 935 (get_wrlat_adj(timing_config->dram_type, pdram_timing->cwl) 936 << 8) | get_rdlat_adj(timing_config->dram_type, 937 pdram_timing->cl); 938 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[284], 0xffff, 939 tmp); 940 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[82], 0xffff << 16, 941 (4 * pdram_timing->trefi) << 16); 942 943 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[83], 0xffff, 944 (2 * pdram_timing->trefi) & 0xffff); 945 946 if ((timing_config->dram_type == LPDDR3) || 947 (timing_config->dram_type == LPDDR4)) { 948 tmp = get_pi_wrlat(pdram_timing, timing_config); 949 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 950 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 951 } else { 952 tmp = 0; 953 } 954 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[214], 0x3f << 16, 955 (tmp & 0x3f) << 16); 956 957 if ((timing_config->dram_type == LPDDR3) || 958 (timing_config->dram_type == LPDDR4)) { 959 /* min_rl_preamble= cl+TDQSCK_MIN-1 */ 960 tmp = pdram_timing->cl + 961 get_pi_todtoff_min(pdram_timing, timing_config) - 1; 962 /* todtoff_max */ 963 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 964 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 965 } else { 966 tmp = pdram_timing->cl - pdram_timing->cwl; 967 } 968 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[215], 0x3f << 8, 969 (tmp & 0x3f) << 8); 970 971 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[275], 0xff << 16, 972 (get_pi_tdfi_phy_rdlat 973 (pdram_timing, timing_config) 974 & 0xff) << 16); 975 976 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[277], 0xffff, 977 (2 * pdram_timing->trefi) & 0xffff); 978 979 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[282], 0xffff, 980 (2 * pdram_timing->trefi) & 0xffff); 981 982 write_32(&rk3399_ddr_pctl[i]->denali_ctl[283], 983 20 * pdram_timing->trefi); 984 985 /* CTL_308 TDFI_CALVL_CAPTURE_F0:RW:16:10 */ 986 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 987 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 988 tmp1++; 989 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 990 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[308], 0x3ff << 16, 991 tmp << 16); 992 993 /* CTL_308 TDFI_CALVL_CC_F0:RW:0:10 */ 994 tmp = tmp + 18; 995 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[308], 0x3ff, 996 tmp); 997 998 /* CTL_314 TDFI_WRCSLAT_F0:RW:8:8 */ 999 tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config); 1000 if (timing_config->freq <= ENPER_CS_TRAINING_FREQ) { 1001 if (tmp1 < 5) { 1002 if (tmp1 == 0) 1003 tmp = 0; 1004 else 1005 tmp = tmp1 - 1; 1006 } else { 1007 tmp = tmp1 - 5; 1008 } 1009 } else { 1010 tmp = tmp1 - 2; 1011 } 1012 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[314], 0xff << 8, 1013 tmp << 8); 1014 1015 /* CTL_314 TDFI_RDCSLAT_F0:RW:0:8 */ 1016 if ((timing_config->freq <= ENPER_CS_TRAINING_FREQ) && 1017 (pdram_timing->cl >= 5)) 1018 tmp = pdram_timing->cl - 5; 1019 else 1020 tmp = pdram_timing->cl - 2; 1021 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[314], 0xff, 1022 tmp); 1023 } 1024 } 1025 1026 static void gen_rk3399_ctl_params_f1(struct timing_related_config 1027 *timing_config, 1028 struct dram_timing_t *pdram_timing) 1029 { 1030 uint32_t i; 1031 uint32_t tmp, tmp1; 1032 1033 for (i = 0; i < timing_config->ch_cnt; i++) { 1034 if (timing_config->dram_type == DDR3) { 1035 tmp = 1036 ((700000 + 10) * timing_config->freq + 1037 999) / 1000; 1038 tmp += 1039 pdram_timing->txsnr + (pdram_timing->tmrd * 3) + 1040 pdram_timing->tmod + pdram_timing->tzqinit; 1041 write_32(&rk3399_ddr_pctl[i]->denali_ctl[9], tmp); 1042 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[22], 1043 0xffff << 16, pdram_timing->tdllk << 16); 1044 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[34], 1045 0xffffff00, 1046 (pdram_timing->tmod << 24) | 1047 (pdram_timing->tmrd << 16) | 1048 (pdram_timing->trtp << 8)); 1049 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[60], 1050 0xffff << 16, 1051 (pdram_timing->txsr - 1052 pdram_timing->trcd) << 16); 1053 } else if (timing_config->dram_type == LPDDR4) { 1054 write_32(&rk3399_ddr_pctl[i]->denali_ctl[9], 1055 pdram_timing->tinit1 + pdram_timing->tinit3); 1056 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[34], 1057 0xffffff00, 1058 (pdram_timing->tmrd << 24) | 1059 (pdram_timing->tmrd << 16) | 1060 (pdram_timing->trtp << 8)); 1061 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[60], 1062 0xffff << 16, pdram_timing->txsr << 16); 1063 } else { 1064 write_32(&rk3399_ddr_pctl[i]->denali_ctl[9], 1065 pdram_timing->tinit1); 1066 write_32(&rk3399_ddr_pctl[i]->denali_ctl[11], 1067 pdram_timing->tinit4); 1068 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[34], 1069 0xffffff00, 1070 (pdram_timing->tmrd << 24) | 1071 (pdram_timing->tmrd << 16) | 1072 (pdram_timing->trtp << 8)); 1073 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[60], 1074 0xffff << 16, pdram_timing->txsr << 16); 1075 } 1076 write_32(&rk3399_ddr_pctl[i]->denali_ctl[10], 1077 pdram_timing->tinit3); 1078 write_32(&rk3399_ddr_pctl[i]->denali_ctl[12], 1079 pdram_timing->tinit5); 1080 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[24], (0x7f << 8), 1081 ((pdram_timing->cl * 2) << 8)); 1082 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[24], (0x1f << 16), 1083 (pdram_timing->cwl << 16)); 1084 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[24], 0x3f << 24, 1085 pdram_timing->al << 24); 1086 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[28], 0xffffff00, 1087 (pdram_timing->tras_min << 24) | 1088 (pdram_timing->trc << 16) | 1089 (pdram_timing->trrd << 8)); 1090 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[29], 0xffffff, 1091 (pdram_timing->tfaw << 16) | 1092 (pdram_timing->trppb << 8) | pdram_timing->twtr); 1093 write_32(&rk3399_ddr_pctl[i]->denali_ctl[35], 1094 (pdram_timing->tcke << 24) | pdram_timing->tras_max); 1095 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[36], 0xff, 1096 max(1, pdram_timing->tckesr)); 1097 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[39], 1098 (0xff << 24), (pdram_timing->trcd << 24)); 1099 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[40], 1100 0x3f, pdram_timing->twr); 1101 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[42], 0x1f << 24, 1102 pdram_timing->tmrz << 24); 1103 tmp = pdram_timing->tdal ? pdram_timing->tdal : 1104 (pdram_timing->twr + pdram_timing->trp); 1105 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[44], 0xff << 8, 1106 tmp << 8); 1107 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[45], 0xff << 8, 1108 pdram_timing->trp << 8); 1109 write_32(&rk3399_ddr_pctl[i]->denali_ctl[49], 1110 ((pdram_timing->trefi - 8) << 16) | 1111 pdram_timing->trfc); 1112 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[52], 0xffff << 16, 1113 pdram_timing->txp << 16); 1114 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[54], 0xffff, 1115 pdram_timing->txpdll); 1116 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[55], 0xff << 8, 1117 pdram_timing->tmrri << 8); 1118 write_32(&rk3399_ddr_pctl[i]->denali_ctl[57], 1119 (pdram_timing->tmrwckel << 24) | 1120 (pdram_timing->tckehcs << 16) | 1121 (pdram_timing->tckelcs << 8) | pdram_timing->tcscke); 1122 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[58], 0xf, 1123 pdram_timing->tzqcke); 1124 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[61], 0xffff, 1125 pdram_timing->txsnr); 1126 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[64], 0xffff << 16, 1127 (pdram_timing->tckehcmd << 24) | 1128 (pdram_timing->tckelcmd << 16)); 1129 write_32(&rk3399_ddr_pctl[i]->denali_ctl[65], 1130 (pdram_timing->tckelpd << 24) | 1131 (pdram_timing->tescke << 16) | 1132 (pdram_timing->tsr << 8) | pdram_timing->tckckel); 1133 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[66], 0xfff, 1134 (pdram_timing->tcmdcke << 8) | 1135 pdram_timing->tcsckeh); 1136 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[92], (0xff << 24), 1137 (pdram_timing->tcksre << 24)); 1138 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[93], 0xff, 1139 pdram_timing->tcksrx); 1140 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[108], (0x1 << 25), 1141 (timing_config->dllbp << 25)); 1142 write_32(&rk3399_ddr_pctl[i]->denali_ctl[125], 1143 (pdram_timing->tvrcg_disable << 16) | 1144 pdram_timing->tvrcg_enable); 1145 write_32(&rk3399_ddr_pctl[i]->denali_ctl[126], 1146 (pdram_timing->tckfspx << 24) | 1147 (pdram_timing->tckfspe << 16) | 1148 pdram_timing->tfc_long); 1149 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[127], 0xffff, 1150 pdram_timing->tvref_long); 1151 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[134], 1152 0xffff << 16, pdram_timing->mr[0] << 16); 1153 write_32(&rk3399_ddr_pctl[i]->denali_ctl[135], 1154 (pdram_timing->mr[2] << 16) | pdram_timing->mr[1]); 1155 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[138], 1156 0xffff << 16, pdram_timing->mr[3] << 16); 1157 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[140], 0xff, 1158 pdram_timing->mr11); 1159 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[148], 1160 0xffff << 16, pdram_timing->mr[0] << 16); 1161 write_32(&rk3399_ddr_pctl[i]->denali_ctl[149], 1162 (pdram_timing->mr[2] << 16) | pdram_timing->mr[1]); 1163 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[152], 1164 0xffff << 16, pdram_timing->mr[3] << 16); 1165 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[154], 0xff, 1166 pdram_timing->mr11); 1167 if (timing_config->dram_type == LPDDR4) { 1168 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[141], 1169 0xffff, pdram_timing->mr12); 1170 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[143], 1171 0xffff, pdram_timing->mr14); 1172 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[146], 1173 0xffff, pdram_timing->mr22); 1174 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[155], 1175 0xffff, pdram_timing->mr12); 1176 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[157], 1177 0xffff, pdram_timing->mr14); 1178 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[160], 1179 0xffff, pdram_timing->mr22); 1180 } 1181 write_32(&rk3399_ddr_pctl[i]->denali_ctl[182], 1182 ((pdram_timing->tzqinit / 2) << 16) | 1183 pdram_timing->tzqinit); 1184 write_32(&rk3399_ddr_pctl[i]->denali_ctl[183], 1185 (pdram_timing->tzqcal << 16) | pdram_timing->tzqcs); 1186 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[184], 0x3f, 1187 pdram_timing->tzqlat); 1188 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[188], 0xfff, 1189 pdram_timing->tzqreset); 1190 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[212], 0xff << 16, 1191 pdram_timing->todton << 16); 1192 1193 if (timing_config->odt) { 1194 setbits_32(&rk3399_ddr_pctl[i]->denali_ctl[213], 1195 (1 << 24)); 1196 if (timing_config->freq < 400) 1197 tmp = 4 << 24; 1198 else 1199 tmp = 8 << 24; 1200 } else { 1201 clrbits_32(&rk3399_ddr_pctl[i]->denali_ctl[213], 1202 (1 << 24)); 1203 tmp = 2 << 24; 1204 } 1205 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[217], 0x1f << 24, 1206 tmp); 1207 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[221], 0xf << 24, 1208 (pdram_timing->tdqsck_max << 24)); 1209 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[222], 0x3, 1210 pdram_timing->tdqsck); 1211 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[291], 0xffff, 1212 (get_wrlat_adj(timing_config->dram_type, 1213 pdram_timing->cwl) << 8) | 1214 get_rdlat_adj(timing_config->dram_type, 1215 pdram_timing->cl)); 1216 1217 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[84], 0xffff, 1218 (4 * pdram_timing->trefi) & 0xffff); 1219 1220 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[84], 0xffff << 16, 1221 ((2 * pdram_timing->trefi) & 0xffff) << 16); 1222 1223 if ((timing_config->dram_type == LPDDR3) || 1224 (timing_config->dram_type == LPDDR4)) { 1225 tmp = get_pi_wrlat(pdram_timing, timing_config); 1226 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 1227 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 1228 } else { 1229 tmp = 0; 1230 } 1231 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[214], 0x3f << 24, 1232 (tmp & 0x3f) << 24); 1233 1234 if ((timing_config->dram_type == LPDDR3) || 1235 (timing_config->dram_type == LPDDR4)) { 1236 /* min_rl_preamble= cl+TDQSCK_MIN-1 */ 1237 tmp = pdram_timing->cl + 1238 get_pi_todtoff_min(pdram_timing, timing_config) - 1; 1239 /* todtoff_max */ 1240 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 1241 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 1242 } else { 1243 tmp = pdram_timing->cl - pdram_timing->cwl; 1244 } 1245 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[215], 0x3f << 16, 1246 (tmp & 0x3f) << 16); 1247 1248 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[275], 0xff << 24, 1249 (get_pi_tdfi_phy_rdlat 1250 (pdram_timing, timing_config) 1251 & 0xff) << 24); 1252 1253 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[284], 1254 0xffff << 16, 1255 ((2 * pdram_timing->trefi) & 0xffff) << 16); 1256 1257 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[289], 0xffff, 1258 (2 * pdram_timing->trefi) & 0xffff); 1259 1260 write_32(&rk3399_ddr_pctl[i]->denali_ctl[290], 1261 20 * pdram_timing->trefi); 1262 1263 /* CTL_309 TDFI_CALVL_CAPTURE_F1:RW:16:10 */ 1264 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 1265 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 1266 tmp1++; 1267 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 1268 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[309], 0x3ff << 16, 1269 tmp << 16); 1270 1271 /* CTL_309 TDFI_CALVL_CC_F1:RW:0:10 */ 1272 tmp = tmp + 18; 1273 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[309], 0x3ff, 1274 tmp); 1275 1276 /* CTL_314 TDFI_WRCSLAT_F1:RW:24:8 */ 1277 tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config); 1278 if (timing_config->freq <= ENPER_CS_TRAINING_FREQ) { 1279 if (tmp1 < 5) { 1280 if (tmp1 == 0) 1281 tmp = 0; 1282 else 1283 tmp = tmp1 - 1; 1284 } else { 1285 tmp = tmp1 - 5; 1286 } 1287 } else { 1288 tmp = tmp1 - 2; 1289 } 1290 1291 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[314], 0xff << 24, 1292 tmp << 24); 1293 1294 /* CTL_314 TDFI_RDCSLAT_F1:RW:16:8 */ 1295 if ((timing_config->freq <= ENPER_CS_TRAINING_FREQ) && 1296 (pdram_timing->cl >= 5)) 1297 tmp = pdram_timing->cl - 5; 1298 else 1299 tmp = pdram_timing->cl - 2; 1300 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[314], 0xff << 16, 1301 tmp << 16); 1302 } 1303 } 1304 1305 static void gen_rk3399_ctl_params(struct timing_related_config *timing_config, 1306 struct dram_timing_t *pdram_timing, 1307 uint32_t fn) 1308 { 1309 if (fn == 0) 1310 gen_rk3399_ctl_params_f0(timing_config, pdram_timing); 1311 else 1312 gen_rk3399_ctl_params_f1(timing_config, pdram_timing); 1313 1314 #if CTL_TRAINING 1315 uint32_t i, tmp0, tmp1; 1316 1317 tmp0 = tmp1 = 0; 1318 #if EN_READ_GATE_TRAINING 1319 tmp1 = 1; 1320 #endif 1321 1322 #if EN_CA_TRAINING 1323 tmp0 |= (1 << 8); 1324 #endif 1325 1326 #if EN_WRITE_LEVELING 1327 tmp0 |= (1 << 16); 1328 #endif 1329 1330 #if EN_READ_LEVELING 1331 tmp0 |= (1 << 24); 1332 #endif 1333 for (i = 0; i < timing_config->ch_cnt; i++) { 1334 if (tmp0 | tmp1) 1335 setbits_32(&rk3399_ddr_pctl[i]->denali_ctl[305], 1336 1 << 16); 1337 if (tmp0) 1338 setbits_32(&rk3399_ddr_pctl[i]->denali_ctl[70], tmp0); 1339 if (tmp1) 1340 setbits_32(&rk3399_ddr_pctl[i]->denali_ctl[71], tmp1); 1341 } 1342 #endif 1343 } 1344 1345 static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config, 1346 struct dram_timing_t *pdram_timing) 1347 { 1348 uint32_t tmp, tmp1, tmp2; 1349 uint32_t i; 1350 1351 for (i = 0; i < timing_config->ch_cnt; i++) { 1352 /* PI_02 PI_TDFI_PHYMSTR_MAX_F0:RW:0:32 */ 1353 tmp = 4 * pdram_timing->trefi; 1354 write_32(&rk3399_ddr_pi[i]->denali_pi[2], tmp); 1355 /* PI_03 PI_TDFI_PHYMSTR_RESP_F0:RW:0:16 */ 1356 tmp = 2 * pdram_timing->trefi; 1357 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[3], 0xffff, tmp); 1358 /* PI_07 PI_TDFI_PHYUPD_RESP_F0:RW:16:16 */ 1359 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[7], 0xffff << 16, 1360 tmp << 16); 1361 1362 /* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F0:RW:0:8 */ 1363 if (timing_config->dram_type == LPDDR4) 1364 tmp = 2; 1365 else 1366 tmp = 0; 1367 tmp = (pdram_timing->bl / 2) + 4 + 1368 (get_pi_rdlat_adj(pdram_timing) - 2) + tmp + 1369 get_pi_tdfi_phy_rdlat(pdram_timing, timing_config); 1370 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[42], 0xff, tmp); 1371 /* PI_43 PI_WRLAT_F0:RW:0:5 */ 1372 if (timing_config->dram_type == LPDDR3) { 1373 tmp = get_pi_wrlat(pdram_timing, timing_config); 1374 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[43], 0x1f, 1375 tmp); 1376 } 1377 /* PI_43 PI_ADDITIVE_LAT_F0:RW:8:6 */ 1378 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[43], 0x3f << 8, 1379 PI_ADD_LATENCY << 8); 1380 1381 /* PI_43 PI_CASLAT_LIN_F0:RW:16:7 */ 1382 tmp = pdram_timing->cl * 2; 1383 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[43], 0x7f << 16, 1384 tmp << 16); 1385 /* PI_46 PI_TREF_F0:RW:16:16 */ 1386 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[46], 0xffff << 16, 1387 pdram_timing->trefi << 16); 1388 /* PI_46 PI_TRFC_F0:RW:0:10 */ 1389 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[46], 0x3ff, 1390 pdram_timing->trfc); 1391 /* PI_66 PI_TODTL_2CMD_F0:RW:24:8 */ 1392 if (timing_config->dram_type == LPDDR3) { 1393 tmp = get_pi_todtoff_max(pdram_timing, timing_config); 1394 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[66], 1395 0xff << 24, tmp << 24); 1396 } 1397 /* PI_72 PI_WR_TO_ODTH_F0:RW:16:6 */ 1398 if ((timing_config->dram_type == LPDDR3) || 1399 (timing_config->dram_type == LPDDR4)) { 1400 tmp1 = get_pi_wrlat(pdram_timing, timing_config); 1401 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1402 if (tmp1 > tmp2) 1403 tmp = tmp1 - tmp2; 1404 else 1405 tmp = 0; 1406 } else if (timing_config->dram_type == DDR3) { 1407 tmp = 0; 1408 } 1409 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[72], 0x3f << 16, 1410 tmp << 16); 1411 /* PI_73 PI_RD_TO_ODTH_F0:RW:8:6 */ 1412 if ((timing_config->dram_type == LPDDR3) || 1413 (timing_config->dram_type == LPDDR4)) { 1414 /* min_rl_preamble= cl+TDQSCK_MIN-1 */ 1415 tmp1 = pdram_timing->cl + 1416 get_pi_todtoff_min(pdram_timing, timing_config) - 1; 1417 /* todtoff_max */ 1418 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1419 if (tmp1 > tmp2) 1420 tmp = tmp1 - tmp2; 1421 else 1422 tmp = 0; 1423 } else if (timing_config->dram_type == DDR3) { 1424 tmp = pdram_timing->cl - pdram_timing->cwl; 1425 } 1426 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[73], 0x3f << 8, 1427 tmp << 8); 1428 /* PI_89 PI_RDLAT_ADJ_F0:RW:16:8 */ 1429 tmp = get_pi_rdlat_adj(pdram_timing); 1430 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[89], 0xff << 16, 1431 tmp << 16); 1432 /* PI_90 PI_WRLAT_ADJ_F0:RW:16:8 */ 1433 tmp = get_pi_wrlat_adj(pdram_timing, timing_config); 1434 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[90], 0xff << 16, 1435 tmp << 16); 1436 /* PI_91 PI_TDFI_WRCSLAT_F0:RW:16:8 */ 1437 tmp1 = tmp; 1438 if (tmp1 < 5) { 1439 if (tmp1 == 0) 1440 tmp = 0; 1441 else 1442 tmp = tmp1 - 1; 1443 } else { 1444 tmp = tmp1 - 5; 1445 } 1446 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[91], 0xff << 16, 1447 tmp << 16); 1448 /* PI_95 PI_TDFI_CALVL_CAPTURE_F0:RW:16:10 */ 1449 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 1450 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 1451 tmp1++; 1452 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 1453 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[95], 0x3ff << 16, 1454 tmp << 16); 1455 /* PI_95 PI_TDFI_CALVL_CC_F0:RW:0:10 */ 1456 tmp = tmp + 18; 1457 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[95], 0x3ff, tmp); 1458 /* PI_102 PI_TMRZ_F0:RW:8:5 */ 1459 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[102], 0x1f << 8, 1460 pdram_timing->tmrz << 8); 1461 /* PI_111 PI_TDFI_CALVL_STROBE_F0:RW:8:4 */ 1462 tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz); 1463 if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0) 1464 tmp1++; 1465 /* pi_tdfi_calvl_strobe=tds_train+5 */ 1466 tmp = tmp1 + 5; 1467 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[111], 0xf << 8, 1468 tmp << 8); 1469 /* PI_116 PI_TCKEHDQS_F0:RW:16:6 */ 1470 tmp = 10000 / (1000000 / pdram_timing->mhz); 1471 if ((10000 % (1000000 / pdram_timing->mhz)) != 0) 1472 tmp++; 1473 if (pdram_timing->mhz <= 100) 1474 tmp = tmp + 1; 1475 else 1476 tmp = tmp + 8; 1477 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[116], 0x3f << 16, 1478 tmp << 16); 1479 /* PI_125 PI_MR1_DATA_F0_0:RW+:8:16 */ 1480 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[125], 0xffff << 8, 1481 pdram_timing->mr[1] << 8); 1482 /* PI_133 PI_MR1_DATA_F0_1:RW+:0:16 */ 1483 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[133], 0xffff, 1484 pdram_timing->mr[1]); 1485 /* PI_140 PI_MR1_DATA_F0_2:RW+:16:16 */ 1486 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[140], 0xffff << 16, 1487 pdram_timing->mr[1] << 16); 1488 /* PI_148 PI_MR1_DATA_F0_3:RW+:0:16 */ 1489 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[148], 0xffff, 1490 pdram_timing->mr[1]); 1491 /* PI_126 PI_MR2_DATA_F0_0:RW+:0:16 */ 1492 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[126], 0xffff, 1493 pdram_timing->mr[2]); 1494 /* PI_133 PI_MR2_DATA_F0_1:RW+:16:16 */ 1495 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[133], 0xffff << 16, 1496 pdram_timing->mr[2] << 16); 1497 /* PI_141 PI_MR2_DATA_F0_2:RW+:0:16 */ 1498 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[141], 0xffff, 1499 pdram_timing->mr[2]); 1500 /* PI_148 PI_MR2_DATA_F0_3:RW+:16:16 */ 1501 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[148], 0xffff << 16, 1502 pdram_timing->mr[2] << 16); 1503 /* PI_156 PI_TFC_F0:RW:0:10 */ 1504 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[156], 0x3ff, 1505 pdram_timing->trfc); 1506 /* PI_158 PI_TWR_F0:RW:24:6 */ 1507 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[158], 0x3f << 24, 1508 pdram_timing->twr << 24); 1509 /* PI_158 PI_TWTR_F0:RW:16:6 */ 1510 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[158], 0x3f << 16, 1511 pdram_timing->twtr << 16); 1512 /* PI_158 PI_TRCD_F0:RW:8:8 */ 1513 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[158], 0xff << 8, 1514 pdram_timing->trcd << 8); 1515 /* PI_158 PI_TRP_F0:RW:0:8 */ 1516 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[158], 0xff, 1517 pdram_timing->trp); 1518 /* PI_157 PI_TRTP_F0:RW:24:8 */ 1519 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[157], 0xff << 24, 1520 pdram_timing->trtp << 24); 1521 /* PI_159 PI_TRAS_MIN_F0:RW:24:8 */ 1522 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[159], 0xff << 24, 1523 pdram_timing->tras_min << 24); 1524 /* PI_159 PI_TRAS_MAX_F0:RW:0:17 */ 1525 tmp = pdram_timing->tras_max * 99 / 100; 1526 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[159], 0x1ffff, tmp); 1527 /* PI_160 PI_TMRD_F0:RW:16:6 */ 1528 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[160], 0x3f << 16, 1529 pdram_timing->tmrd << 16); 1530 /*PI_160 PI_TDQSCK_MAX_F0:RW:0:4 */ 1531 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[160], 0xf, 1532 pdram_timing->tdqsck_max); 1533 /* PI_187 PI_TDFI_CTRLUPD_MAX_F0:RW:8:16 */ 1534 tmp = 2 * pdram_timing->trefi; 1535 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[187], 0xffff << 8, 1536 tmp << 8); 1537 /* PI_188 PI_TDFI_CTRLUPD_INTERVAL_F0:RW:0:32 */ 1538 tmp = 20 * pdram_timing->trefi; 1539 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[188], 0xffffffff, 1540 tmp); 1541 } 1542 } 1543 1544 static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config, 1545 struct dram_timing_t *pdram_timing) 1546 { 1547 uint32_t tmp, tmp1, tmp2; 1548 uint32_t i; 1549 1550 for (i = 0; i < timing_config->ch_cnt; i++) { 1551 /* PI_04 PI_TDFI_PHYMSTR_MAX_F1:RW:0:32 */ 1552 tmp = 4 * pdram_timing->trefi; 1553 write_32(&rk3399_ddr_pi[i]->denali_pi[4], tmp); 1554 /* PI_05 PI_TDFI_PHYMSTR_RESP_F1:RW:0:16 */ 1555 tmp = 2 * pdram_timing->trefi; 1556 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[5], 0xffff, tmp); 1557 /* PI_12 PI_TDFI_PHYUPD_RESP_F1:RW:0:16 */ 1558 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[12], 0xffff, tmp); 1559 1560 /* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F1:RW:8:8 */ 1561 if (timing_config->dram_type == LPDDR4) 1562 tmp = 2; 1563 else 1564 tmp = 0; 1565 tmp = (pdram_timing->bl / 2) + 4 + 1566 (get_pi_rdlat_adj(pdram_timing) - 2) + tmp + 1567 get_pi_tdfi_phy_rdlat(pdram_timing, timing_config); 1568 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[42], 0xff << 8, 1569 tmp << 8); 1570 /* PI_43 PI_WRLAT_F1:RW:24:5 */ 1571 if (timing_config->dram_type == LPDDR3) { 1572 tmp = get_pi_wrlat(pdram_timing, timing_config); 1573 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[43], 1574 0x1f << 24, tmp << 24); 1575 } 1576 /* PI_44 PI_ADDITIVE_LAT_F1:RW:0:6 */ 1577 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[44], 0x3f, 1578 PI_ADD_LATENCY); 1579 /* PI_44 PI_CASLAT_LIN_F1:RW:8:7:=0x18 */ 1580 tmp = pdram_timing->cl * 2; 1581 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[44], 0x7f << 8, 1582 tmp << 8); 1583 /* PI_47 PI_TREF_F1:RW:16:16 */ 1584 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[47], 0xffff << 16, 1585 pdram_timing->trefi << 16); 1586 /* PI_47 PI_TRFC_F1:RW:0:10 */ 1587 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[47], 0x3ff, 1588 pdram_timing->trfc); 1589 /* PI_67 PI_TODTL_2CMD_F1:RW:8:8 */ 1590 if (timing_config->dram_type == LPDDR3) { 1591 tmp = get_pi_todtoff_max(pdram_timing, timing_config); 1592 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[67], 1593 0xff << 8, tmp << 8); 1594 } 1595 /* PI_72 PI_WR_TO_ODTH_F1:RW:24:6 */ 1596 if ((timing_config->dram_type == LPDDR3) 1597 || (timing_config->dram_type == LPDDR4)) { 1598 tmp1 = get_pi_wrlat(pdram_timing, timing_config); 1599 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1600 if (tmp1 > tmp2) 1601 tmp = tmp1 - tmp2; 1602 else 1603 tmp = 0; 1604 } else if (timing_config->dram_type == DDR3) { 1605 tmp = 0; 1606 } 1607 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[72], 0x3f << 24, 1608 tmp << 24); 1609 /* PI_73 PI_RD_TO_ODTH_F1:RW:16:6 */ 1610 if ((timing_config->dram_type == LPDDR3) 1611 || (timing_config->dram_type == LPDDR4)) { 1612 /* min_rl_preamble= cl+TDQSCK_MIN-1 */ 1613 tmp1 = 1614 pdram_timing->cl + get_pi_todtoff_min(pdram_timing, 1615 timing_config) 1616 - 1; 1617 /* todtoff_max */ 1618 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1619 if (tmp1 > tmp2) 1620 tmp = tmp1 - tmp2; 1621 else 1622 tmp = 0; 1623 } else if (timing_config->dram_type == DDR3) { 1624 tmp = pdram_timing->cl - pdram_timing->cwl; 1625 } 1626 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[73], 0x3f << 16, 1627 tmp << 16); 1628 /*P I_89 PI_RDLAT_ADJ_F1:RW:24:8 */ 1629 tmp = get_pi_rdlat_adj(pdram_timing); 1630 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[89], 0xff << 24, 1631 tmp << 24); 1632 /* PI_90 PI_WRLAT_ADJ_F1:RW:24:8 */ 1633 tmp = get_pi_wrlat_adj(pdram_timing, timing_config); 1634 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[90], 0xff << 24, 1635 tmp << 24); 1636 /* PI_91 PI_TDFI_WRCSLAT_F1:RW:24:8 */ 1637 tmp1 = tmp; 1638 if (tmp1 < 5) { 1639 if (tmp1 == 0) 1640 tmp = 0; 1641 else 1642 tmp = tmp1 - 1; 1643 } else { 1644 tmp = tmp1 - 5; 1645 } 1646 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[91], 0xff << 24, 1647 tmp << 24); 1648 /*PI_96 PI_TDFI_CALVL_CAPTURE_F1:RW:16:10 */ 1649 /* tadr=20ns */ 1650 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 1651 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 1652 tmp1++; 1653 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 1654 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[96], 0x3ff << 16, 1655 tmp << 16); 1656 /* PI_96 PI_TDFI_CALVL_CC_F1:RW:0:10 */ 1657 tmp = tmp + 18; 1658 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[96], 0x3ff, tmp); 1659 /*PI_103 PI_TMRZ_F1:RW:0:5 */ 1660 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[103], 0x1f, 1661 pdram_timing->tmrz); 1662 /*PI_111 PI_TDFI_CALVL_STROBE_F1:RW:16:4 */ 1663 /* tds_train=ceil(2/ns) */ 1664 tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz); 1665 if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0) 1666 tmp1++; 1667 /* pi_tdfi_calvl_strobe=tds_train+5 */ 1668 tmp = tmp1 + 5; 1669 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[111], 0xf << 16, 1670 tmp << 16); 1671 /* PI_116 PI_TCKEHDQS_F1:RW:24:6 */ 1672 tmp = 10000 / (1000000 / pdram_timing->mhz); 1673 if ((10000 % (1000000 / pdram_timing->mhz)) != 0) 1674 tmp++; 1675 if (pdram_timing->mhz <= 100) 1676 tmp = tmp + 1; 1677 else 1678 tmp = tmp + 8; 1679 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[116], 0x3f << 24, 1680 tmp << 24); 1681 /* PI_128 PI_MR1_DATA_F1_0:RW+:0:16 */ 1682 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[128], 0xffff, 1683 pdram_timing->mr[1]); 1684 /* PI_135 PI_MR1_DATA_F1_1:RW+:8:16 */ 1685 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[135], 0xffff << 8, 1686 pdram_timing->mr[1] << 8); 1687 /* PI_143 PI_MR1_DATA_F1_2:RW+:0:16 */ 1688 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[143], 0xffff, 1689 pdram_timing->mr[1]); 1690 /* PI_150 PI_MR1_DATA_F1_3:RW+:8:16 */ 1691 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[150], 0xffff << 8, 1692 pdram_timing->mr[1] << 8); 1693 /* PI_128 PI_MR2_DATA_F1_0:RW+:16:16 */ 1694 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[128], 0xffff << 16, 1695 pdram_timing->mr[2] << 16); 1696 /* PI_136 PI_MR2_DATA_F1_1:RW+:0:16 */ 1697 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[136], 0xffff, 1698 pdram_timing->mr[2]); 1699 /* PI_143 PI_MR2_DATA_F1_2:RW+:16:16 */ 1700 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[143], 0xffff << 16, 1701 pdram_timing->mr[2] << 16); 1702 /* PI_151 PI_MR2_DATA_F1_3:RW+:0:16 */ 1703 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[151], 0xffff, 1704 pdram_timing->mr[2]); 1705 /* PI_156 PI_TFC_F1:RW:16:10 */ 1706 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[156], 0x3ff << 16, 1707 pdram_timing->trfc << 16); 1708 /* PI_162 PI_TWR_F1:RW:8:6 */ 1709 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[162], 0x3f << 8, 1710 pdram_timing->twr << 8); 1711 /* PI_162 PI_TWTR_F1:RW:0:6 */ 1712 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[162], 0x3f, 1713 pdram_timing->twtr); 1714 /* PI_161 PI_TRCD_F1:RW:24:8 */ 1715 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[161], 0xff << 24, 1716 pdram_timing->trcd << 24); 1717 /* PI_161 PI_TRP_F1:RW:16:8 */ 1718 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[161], 0xff << 16, 1719 pdram_timing->trp << 16); 1720 /* PI_161 PI_TRTP_F1:RW:8:8 */ 1721 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[161], 0xff << 8, 1722 pdram_timing->trtp << 8); 1723 /* PI_163 PI_TRAS_MIN_F1:RW:24:8 */ 1724 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[163], 0xff << 24, 1725 pdram_timing->tras_min << 24); 1726 /* PI_163 PI_TRAS_MAX_F1:RW:0:17 */ 1727 tmp = pdram_timing->tras_max * 99 / 100; 1728 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[163], 0x1ffff, tmp); 1729 /* PI_164 PI_TMRD_F1:RW:16:6 */ 1730 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[164], 0x3f << 16, 1731 pdram_timing->tmrd << 16); 1732 /* PI_164 PI_TDQSCK_MAX_F1:RW:0:4 */ 1733 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[164], 0xf, 1734 pdram_timing->tdqsck_max); 1735 /* PI_189 PI_TDFI_CTRLUPD_MAX_F1:RW:0:16 */ 1736 tmp = 2 * pdram_timing->trefi; 1737 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[189], 0xffff, tmp); 1738 /* PI_190 PI_TDFI_CTRLUPD_INTERVAL_F1:RW:0:32 */ 1739 tmp = 20 * pdram_timing->trefi; 1740 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[190], 0xffffffff, 1741 tmp); 1742 } 1743 } 1744 1745 static void gen_rk3399_pi_params(struct timing_related_config *timing_config, 1746 struct dram_timing_t *pdram_timing, 1747 uint32_t fn) 1748 { 1749 if (fn == 0) 1750 gen_rk3399_pi_params_f0(timing_config, pdram_timing); 1751 else 1752 gen_rk3399_pi_params_f1(timing_config, pdram_timing); 1753 1754 #if PI_TRAINING 1755 uint32_t i; 1756 1757 for (i = 0; i < timing_config->ch_cnt; i++) { 1758 #if EN_READ_GATE_TRAINING 1759 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[80], 3 << 24, 1760 2 << 24); 1761 #endif 1762 1763 #if EN_CA_TRAINING 1764 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[100], 3 << 8, 1765 2 << 8); 1766 #endif 1767 1768 #if EN_WRITE_LEVELING 1769 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[60], 3 << 8, 1770 2 << 8); 1771 #endif 1772 1773 #if EN_READ_LEVELING 1774 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[80], 3 << 16, 1775 2 << 16); 1776 #endif 1777 1778 #if EN_WDQ_LEVELING 1779 clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[124], 3 << 16, 1780 2 << 16); 1781 #endif 1782 } 1783 #endif 1784 } 1785 1786 static void gen_rk3399_set_odt(uint32_t odt_en) 1787 { 1788 uint32_t drv_odt_val; 1789 uint32_t i; 1790 1791 for (i = 0; i < rk3399_dram_status.timing_config.ch_cnt; i++) { 1792 drv_odt_val = (odt_en | (0 << 1) | (0 << 2)) << 16; 1793 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[5], 1794 0x7 << 16, drv_odt_val); 1795 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[133], 1796 0x7 << 16, drv_odt_val); 1797 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[261], 1798 0x7 << 16, drv_odt_val); 1799 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[389], 1800 0x7 << 16, drv_odt_val); 1801 drv_odt_val = (odt_en | (0 << 1) | (0 << 2)) << 24; 1802 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[6], 1803 0x7 << 24, drv_odt_val); 1804 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[134], 1805 0x7 << 24, drv_odt_val); 1806 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[262], 1807 0x7 << 24, drv_odt_val); 1808 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[390], 1809 0x7 << 24, drv_odt_val); 1810 } 1811 } 1812 1813 static void gen_rk3399_set_ds_odt(struct timing_related_config *timing_config, 1814 struct drv_odt_lp_config *drv_config) 1815 { 1816 uint32_t i, drv_odt_val; 1817 1818 for (i = 0; i < timing_config->ch_cnt; i++) { 1819 if (timing_config->dram_type == LPDDR4) 1820 drv_odt_val = drv_config->phy_side_odt | 1821 (PHY_DRV_ODT_Hi_Z << 4) | 1822 (drv_config->phy_side_dq_drv << 8) | 1823 (drv_config->phy_side_dq_drv << 12); 1824 else if (timing_config->dram_type == LPDDR3) 1825 drv_odt_val = PHY_DRV_ODT_Hi_Z | 1826 (drv_config->phy_side_odt << 4) | 1827 (drv_config->phy_side_dq_drv << 8) | 1828 (drv_config->phy_side_dq_drv << 12); 1829 else 1830 drv_odt_val = drv_config->phy_side_odt | 1831 (drv_config->phy_side_odt << 4) | 1832 (drv_config->phy_side_dq_drv << 8) | 1833 (drv_config->phy_side_dq_drv << 12); 1834 1835 /* DQ drv odt set */ 1836 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[6], 0xffffff, 1837 drv_odt_val); 1838 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[134], 0xffffff, 1839 drv_odt_val); 1840 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[262], 0xffffff, 1841 drv_odt_val); 1842 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[390], 0xffffff, 1843 drv_odt_val); 1844 /* DQS drv odt set */ 1845 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[7], 0xffffff, 1846 drv_odt_val); 1847 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[135], 0xffffff, 1848 drv_odt_val); 1849 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[263], 0xffffff, 1850 drv_odt_val); 1851 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[391], 0xffffff, 1852 drv_odt_val); 1853 1854 gen_rk3399_set_odt(timing_config->odt); 1855 1856 /* CA drv set */ 1857 drv_odt_val = drv_config->phy_side_ca_drv | 1858 (drv_config->phy_side_ca_drv << 4); 1859 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[544], 0xff, 1860 drv_odt_val); 1861 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[672], 0xff, 1862 drv_odt_val); 1863 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[800], 0xff, 1864 drv_odt_val); 1865 1866 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[928], 0xff, 1867 drv_odt_val); 1868 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[937], 0xff, 1869 drv_odt_val); 1870 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[935], 0xff, 1871 drv_odt_val); 1872 1873 drv_odt_val = drv_config->phy_side_ck_cs_drv | 1874 (drv_config->phy_side_ck_cs_drv << 4); 1875 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[929], 0xff, 1876 drv_odt_val); 1877 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[939], 0xff, 1878 drv_odt_val); 1879 } 1880 } 1881 1882 static void gen_rk3399_phy_params(struct timing_related_config *timing_config, 1883 struct drv_odt_lp_config *drv_config, 1884 struct dram_timing_t *pdram_timing, 1885 uint32_t fn) 1886 { 1887 uint32_t tmp, i, div, j; 1888 uint32_t mem_delay_ps, pad_delay_ps, total_delay_ps, delay_frac_ps; 1889 uint32_t trpre_min_ps, gate_delay_ps, gate_delay_frac_ps; 1890 uint32_t ie_enable, tsel_enable, cas_lat, rddata_en_ie_dly, tsel_adder; 1891 uint32_t extra_adder, delta, hs_offset; 1892 1893 for (i = 0; i < timing_config->ch_cnt; i++) { 1894 1895 pad_delay_ps = PI_PAD_DELAY_PS_VALUE; 1896 ie_enable = PI_IE_ENABLE_VALUE; 1897 tsel_enable = PI_TSEL_ENABLE_VALUE; 1898 1899 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[896], 1900 (0x3 << 8) | 1, fn << 8); 1901 1902 /* PHY_LOW_FREQ_SEL */ 1903 /* DENALI_PHY_913 1bit offset_0 */ 1904 if (timing_config->freq > 400) 1905 clrbits_32(&rk3399_ddr_publ[i]->denali_phy[913], 1); 1906 else 1907 setbits_32(&rk3399_ddr_publ[i]->denali_phy[913], 1); 1908 1909 /* PHY_RPTR_UPDATE_x */ 1910 /* DENALI_PHY_87/215/343/471 4bit offset_16 */ 1911 tmp = 2500 / (1000000 / pdram_timing->mhz) + 3; 1912 if ((2500 % (1000000 / pdram_timing->mhz)) != 0) 1913 tmp++; 1914 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[87], 0xf << 16, 1915 tmp << 16); 1916 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[215], 0xf << 16, 1917 tmp << 16); 1918 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[343], 0xf << 16, 1919 tmp << 16); 1920 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[471], 0xf << 16, 1921 tmp << 16); 1922 1923 /* PHY_PLL_CTRL */ 1924 /* DENALI_PHY_911 13bits offset_0 */ 1925 /* PHY_LP4_BOOT_PLL_CTRL */ 1926 /* DENALI_PHY_919 13bits offset_0 */ 1927 if (pdram_timing->mhz <= 150) 1928 tmp = 3; 1929 else if (pdram_timing->mhz <= 300) 1930 tmp = 2; 1931 else if (pdram_timing->mhz <= 600) 1932 tmp = 1; 1933 else 1934 tmp = 0; 1935 tmp = (1 << 12) | (tmp << 9) | (2 << 7) | (1 << 1); 1936 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[911], 0x1fff, 1937 tmp); 1938 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[919], 0x1fff, 1939 tmp); 1940 1941 /* PHY_PLL_CTRL_CA */ 1942 /* DENALI_PHY_911 13bits offset_16 */ 1943 /* PHY_LP4_BOOT_PLL_CTRL_CA */ 1944 /* DENALI_PHY_919 13bits offset_16 */ 1945 if (pdram_timing->mhz <= 150) 1946 tmp = 3; 1947 else if (pdram_timing->mhz <= 300) 1948 tmp = 2; 1949 else if (pdram_timing->mhz <= 600) 1950 tmp = 1; 1951 else 1952 tmp = 0; 1953 tmp = (tmp << 9) | (2 << 7) | (1 << 5) | (1 << 1); 1954 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[911], 1955 0x1fff << 16, tmp << 16); 1956 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[919], 1957 0x1fff << 16, tmp << 16); 1958 1959 /* PHY_TCKSRE_WAIT */ 1960 /* DENALI_PHY_922 4bits offset_24 */ 1961 if (pdram_timing->mhz <= 400) 1962 tmp = 1; 1963 else if (pdram_timing->mhz <= 800) 1964 tmp = 3; 1965 else if (pdram_timing->mhz <= 1000) 1966 tmp = 4; 1967 else 1968 tmp = 5; 1969 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[922], 0xf << 24, 1970 tmp << 24); 1971 /* PHY_CAL_CLK_SELECT_0:RW8:3 */ 1972 div = pdram_timing->mhz / (2 * 20); 1973 for (j = 2, tmp = 1; j <= 128; j <<= 1, tmp++) { 1974 if (div < j) 1975 break; 1976 } 1977 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[947], 0x7 << 8, 1978 tmp << 8); 1979 setbits_32(&rk3399_ddr_publ[i]->denali_phy[927], (1 << 22)); 1980 1981 if (timing_config->dram_type == DDR3) { 1982 mem_delay_ps = 0; 1983 trpre_min_ps = 1000; 1984 } else if (timing_config->dram_type == LPDDR4) { 1985 mem_delay_ps = 1500; 1986 trpre_min_ps = 900; 1987 } else if (timing_config->dram_type == LPDDR3) { 1988 mem_delay_ps = 2500; 1989 trpre_min_ps = 900; 1990 } else { 1991 ERROR("gen_rk3399_phy_params:dramtype unsupport\n"); 1992 return; 1993 } 1994 total_delay_ps = mem_delay_ps + pad_delay_ps; 1995 delay_frac_ps = 1996 1000 * total_delay_ps / (1000000 / pdram_timing->mhz); 1997 gate_delay_ps = delay_frac_ps + 1000 - (trpre_min_ps / 2); 1998 gate_delay_frac_ps = 1999 gate_delay_ps - gate_delay_ps / 1000 * 1000; 2000 tmp = gate_delay_frac_ps * 0x200 / 1000; 2001 /* PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY */ 2002 /* DENALI_PHY_2/130/258/386 10bits offset_0 */ 2003 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[2], 0x2ff, tmp); 2004 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[130], 0x2ff, tmp); 2005 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[258], 0x2ff, tmp); 2006 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[386], 0x2ff, tmp); 2007 /* PHY_RDDQS_GATE_SLAVE_DELAY */ 2008 /* DENALI_PHY_77/205/333/461 10bits offset_16 */ 2009 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[77], 0x2ff << 16, 2010 tmp << 16); 2011 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[205], 0x2ff << 16, 2012 tmp << 16); 2013 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[333], 0x2ff << 16, 2014 tmp << 16); 2015 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[461], 0x2ff << 16, 2016 tmp << 16); 2017 2018 tmp = gate_delay_ps / 1000; 2019 /* PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST */ 2020 /* DENALI_PHY_10/138/266/394 4bit offset_0 */ 2021 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[10], 0xf, tmp); 2022 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[138], 0xf, tmp); 2023 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[266], 0xf, tmp); 2024 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[394], 0xf, tmp); 2025 /* PHY_RDDQS_LATENCY_ADJUST */ 2026 /* DENALI_PHY_78/206/334/462 4bits offset_0 */ 2027 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[78], 0xf, tmp); 2028 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[206], 0xf, tmp); 2029 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[334], 0xf, tmp); 2030 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[462], 0xf, tmp); 2031 /* PHY_GTLVL_LAT_ADJ_START */ 2032 /* DENALI_PHY_80/208/336/464 4bits offset_16 */ 2033 tmp = delay_frac_ps / 1000; 2034 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[80], 0xf << 16, 2035 tmp << 16); 2036 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[208], 0xf << 16, 2037 tmp << 16); 2038 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[336], 0xf << 16, 2039 tmp << 16); 2040 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[464], 0xf << 16, 2041 tmp << 16); 2042 2043 cas_lat = pdram_timing->cl + PI_ADD_LATENCY; 2044 rddata_en_ie_dly = ie_enable / (1000000 / pdram_timing->mhz); 2045 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 2046 rddata_en_ie_dly++; 2047 rddata_en_ie_dly = rddata_en_ie_dly - 1; 2048 tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz); 2049 if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0) 2050 tsel_adder++; 2051 if (rddata_en_ie_dly > tsel_adder) 2052 extra_adder = rddata_en_ie_dly - tsel_adder; 2053 else 2054 extra_adder = 0; 2055 delta = cas_lat - rddata_en_ie_dly; 2056 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 2057 hs_offset = 2; 2058 else 2059 hs_offset = 1; 2060 if (rddata_en_ie_dly > (cas_lat - 1 - hs_offset)) { 2061 tmp = 0; 2062 } else { 2063 if ((delta == 2) || (delta == 1)) 2064 tmp = rddata_en_ie_dly - 0 - extra_adder; 2065 else 2066 tmp = extra_adder; 2067 } 2068 /* PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY */ 2069 /* DENALI_PHY_9/137/265/393 4bit offset_16 */ 2070 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[9], 0xf << 16, 2071 tmp << 16); 2072 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[137], 0xf << 16, 2073 tmp << 16); 2074 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[265], 0xf << 16, 2075 tmp << 16); 2076 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[393], 0xf << 16, 2077 tmp << 16); 2078 /* PHY_RDDATA_EN_TSEL_DLY */ 2079 /* DENALI_PHY_86/214/342/470 4bit offset_0 */ 2080 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[86], 0xf, tmp); 2081 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[214], 0xf, tmp); 2082 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[342], 0xf, tmp); 2083 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[470], 0xf, tmp); 2084 2085 if (tsel_adder > rddata_en_ie_dly) 2086 extra_adder = tsel_adder - rddata_en_ie_dly; 2087 else 2088 extra_adder = 0; 2089 if (rddata_en_ie_dly > (cas_lat - 1 - hs_offset)) 2090 tmp = tsel_adder; 2091 else 2092 tmp = rddata_en_ie_dly - 0 + extra_adder; 2093 /* PHY_LP4_BOOT_RDDATA_EN_DLY */ 2094 /* DENALI_PHY_9/137/265/393 4bit offset_8 */ 2095 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[9], 0xf << 8, 2096 tmp << 8); 2097 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[137], 0xf << 8, 2098 tmp << 8); 2099 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[265], 0xf << 8, 2100 tmp << 8); 2101 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[393], 0xf << 8, 2102 tmp << 8); 2103 /* PHY_RDDATA_EN_DLY */ 2104 /* DENALI_PHY_85/213/341/469 4bit offset_24 */ 2105 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[85], 0xf << 24, 2106 tmp << 24); 2107 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[213], 0xf << 24, 2108 tmp << 24); 2109 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[341], 0xf << 24, 2110 tmp << 24); 2111 clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[469], 0xf << 24, 2112 tmp << 24); 2113 2114 if (pdram_timing->mhz <= ENPER_CS_TRAINING_FREQ) { 2115 2116 /* 2117 * Note:Per-CS Training is not compatible at speeds 2118 * under 533 MHz. If the PHY is running at a speed 2119 * less than 533MHz, all phy_per_cs_training_en_X 2120 * parameters must be cleared to 0. 2121 */ 2122 2123 /*DENALI_PHY_84/212/340/468 1bit offset_16 */ 2124 clrbits_32(&rk3399_ddr_publ[i]->denali_phy[84], 2125 0x1 << 16); 2126 clrbits_32(&rk3399_ddr_publ[i]->denali_phy[212], 2127 0x1 << 16); 2128 clrbits_32(&rk3399_ddr_publ[i]->denali_phy[340], 2129 0x1 << 16); 2130 clrbits_32(&rk3399_ddr_publ[i]->denali_phy[468], 2131 0x1 << 16); 2132 } else { 2133 setbits_32(&rk3399_ddr_publ[i]->denali_phy[84], 2134 0x1 << 16); 2135 setbits_32(&rk3399_ddr_publ[i]->denali_phy[212], 2136 0x1 << 16); 2137 setbits_32(&rk3399_ddr_publ[i]->denali_phy[340], 2138 0x1 << 16); 2139 setbits_32(&rk3399_ddr_publ[i]->denali_phy[468], 2140 0x1 << 16); 2141 } 2142 } 2143 } 2144 2145 static int to_get_clk_index(unsigned int mhz) 2146 { 2147 int pll_cnt, i; 2148 2149 pll_cnt = sizeof(dpll_rates_table) / sizeof(struct pll_div); 2150 2151 /* Assumming rate_table is in descending order */ 2152 for (i = 0; i < pll_cnt; i++) { 2153 if (mhz >= dpll_rates_table[i].mhz) 2154 break; 2155 } 2156 2157 return i; 2158 } 2159 2160 uint32_t rkclk_prepare_pll_timing(unsigned int mhz) 2161 { 2162 unsigned int refdiv, postdiv1, fbdiv, postdiv2; 2163 int index; 2164 2165 index = to_get_clk_index(mhz); 2166 refdiv = dpll_rates_table[index].refdiv; 2167 fbdiv = dpll_rates_table[index].fbdiv; 2168 postdiv1 = dpll_rates_table[index].postdiv1; 2169 postdiv2 = dpll_rates_table[index].postdiv2; 2170 write_32(DCF_PARAM_ADDR + PARAM_DPLL_CON0, FBDIV(fbdiv)); 2171 write_32(DCF_PARAM_ADDR + PARAM_DPLL_CON1, POSTDIV2(postdiv2) | 2172 POSTDIV1(postdiv1) | REFDIV(refdiv)); 2173 return (24 * fbdiv) / refdiv / postdiv1 / postdiv2; 2174 } 2175 2176 uint64_t ddr_get_rate(void) 2177 { 2178 uint32_t refdiv, postdiv1, fbdiv, postdiv2; 2179 2180 refdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) & 0x3f; 2181 fbdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 0)) & 0xfff; 2182 postdiv1 = 2183 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 8) & 0x7; 2184 postdiv2 = 2185 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 12) & 0x7; 2186 2187 return (24 / refdiv * fbdiv / postdiv1 / postdiv2) * 1000 * 1000; 2188 } 2189 2190 /* 2191 * return: bit12: channel 1, external self-refresh 2192 * bit11: channel 1, stdby_mode 2193 * bit10: channel 1, self-refresh with controller and memory clock gate 2194 * bit9: channel 1, self-refresh 2195 * bit8: channel 1, power-down 2196 * 2197 * bit4: channel 1, external self-refresh 2198 * bit3: channel 0, stdby_mode 2199 * bit2: channel 0, self-refresh with controller and memory clock gate 2200 * bit1: channel 0, self-refresh 2201 * bit0: channel 0, power-down 2202 */ 2203 uint32_t exit_low_power(void) 2204 { 2205 struct rk3399_ddr_pctl_regs *ddr_pctl_regs; 2206 uint32_t low_power = 0; 2207 uint32_t channel_mask; 2208 uint32_t channel; 2209 uint32_t tmp; 2210 2211 channel_mask = (read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & 0x3; 2212 for (channel = 0; channel < 2; channel++) { 2213 ddr_pctl_regs = rk3399_ddr_pctl[channel]; 2214 if (!(channel_mask & (1 << channel))) 2215 continue; 2216 2217 /* exit stdby mode */ 2218 low_power |= 2219 ((read_32(&rk3399_ddr_cic->cic_ctrl1) >> 2220 channel) & 0x1) << (3 + 8 * channel); 2221 write_32(&rk3399_ddr_cic->cic_ctrl1, 2222 (1 << (channel + 16)) | (0 << channel)); 2223 /* exit external self-refresh */ 2224 tmp = channel ? 12 : 8; 2225 low_power |= ((read_32(PMU_BASE + PMU_SFT_CON) >> tmp) & 0x1) 2226 << (4 + 8 * channel); 2227 clrbits_32(PMU_BASE + PMU_SFT_CON, 1 << tmp); 2228 while (!(read_32(PMU_BASE + PMU_DDR_SREF_ST) & 2229 (1 << channel))) 2230 ; 2231 /* exit auto low-power */ 2232 low_power |= (read_32(&ddr_pctl_regs->denali_ctl[101]) & 2233 0xf) << (8 * channel); 2234 clrbits_32(&ddr_pctl_regs->denali_ctl[101], 0xf); 2235 /* lp_cmd to exit */ 2236 if (((read_32(&ddr_pctl_regs->denali_ctl[100]) >> 24) & 2237 0x7f) != 0x40) { 2238 while (read_32(&ddr_pctl_regs->denali_ctl[200]) & 0x1) 2239 ; 2240 clrsetbits_32(&ddr_pctl_regs->denali_ctl[93], 2241 0xff << 24, 0x69 << 24); 2242 while (((read_32(&ddr_pctl_regs->denali_ctl[100]) >> 2243 24) & 0x7f) != 0x40) 2244 ; 2245 } 2246 } 2247 return low_power; 2248 } 2249 2250 void resume_low_power(uint32_t low_power) 2251 { 2252 struct rk3399_ddr_pctl_regs *ddr_pctl_regs; 2253 uint32_t channel_mask; 2254 uint32_t channel; 2255 uint32_t tmp; 2256 uint32_t val; 2257 2258 channel_mask = (read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & 0x3; 2259 for (channel = 0; channel < 2; channel++) { 2260 ddr_pctl_regs = rk3399_ddr_pctl[channel]; 2261 if (!(channel_mask & (1 << channel))) 2262 continue; 2263 2264 /* resume external self-refresh */ 2265 tmp = channel ? 12 : 8; 2266 val = (low_power >> (4 + 8 * channel)) & 0x1; 2267 setbits_32(PMU_BASE + PMU_SFT_CON, val << tmp); 2268 /* resume auto low-power */ 2269 val = (low_power >> (8 * channel)) & 0xf; 2270 setbits_32(&ddr_pctl_regs->denali_ctl[101], val); 2271 /* resume stdby mode */ 2272 val = (low_power >> (3 + 8 * channel)) & 0x1; 2273 write_32(&rk3399_ddr_cic->cic_ctrl1, 2274 (1 << (channel + 16)) | (val << channel)); 2275 } 2276 } 2277 2278 static void wait_dcf_done(void) 2279 { 2280 while ((read_32(DCF_BASE + DCF_DCF_ISR) & (DCF_DONE)) == 0) 2281 continue; 2282 } 2283 2284 void clr_dcf_irq(void) 2285 { 2286 /* clear dcf irq status */ 2287 mmio_write_32(DCF_BASE + DCF_DCF_ISR, DCF_TIMEOUT | DCF_ERR | DCF_DONE); 2288 } 2289 2290 static void enable_dcf(uint32_t dcf_addr) 2291 { 2292 /* config DCF start addr */ 2293 write_32(DCF_BASE + DCF_DCF_ADDR, dcf_addr); 2294 /* wait dcf done */ 2295 while (read_32(DCF_BASE + DCF_DCF_CTRL) & 1) 2296 continue; 2297 /* clear dcf irq status */ 2298 write_32(DCF_BASE + DCF_DCF_ISR, DCF_TIMEOUT | DCF_ERR | DCF_DONE); 2299 /* DCF start */ 2300 setbits_32(DCF_BASE + DCF_DCF_CTRL, DCF_START); 2301 } 2302 2303 void dcf_code_init(void) 2304 { 2305 memcpy((void *)DCF_START_ADDR, (void *)dcf_code, sizeof(dcf_code)); 2306 /* set dcf master secure */ 2307 write_32(SGRF_BASE + 0xe01c, ((0x3 << 0) << 16) | (0 << 0)); 2308 write_32(DCF_BASE + DCF_DCF_TOSET, 0x80000000); 2309 } 2310 2311 static void dcf_start(uint32_t freq, uint32_t index) 2312 { 2313 write_32(CRU_BASE + CRU_SOFTRST_CON(10), (0x1 << (1 + 16)) | (1 << 1)); 2314 write_32(CRU_BASE + CRU_SOFTRST_CON(11), (0x1 << (0 + 16)) | (1 << 0)); 2315 write_32(DCF_PARAM_ADDR + PARAM_FREQ_SELECT, index << 4); 2316 2317 write_32(DCF_PARAM_ADDR + PARAM_DRAM_FREQ, freq); 2318 2319 rkclk_prepare_pll_timing(freq); 2320 udelay(10); 2321 write_32(CRU_BASE + CRU_SOFTRST_CON(10), (0x1 << (1 + 16)) | (0 << 1)); 2322 write_32(CRU_BASE + CRU_SOFTRST_CON(11), (0x1 << (0 + 16)) | (0 << 0)); 2323 udelay(10); 2324 enable_dcf(DCF_START_ADDR); 2325 } 2326 2327 static void dram_low_power_config(struct drv_odt_lp_config *lp_config) 2328 { 2329 uint32_t tmp, tmp1, i; 2330 uint32_t ch_cnt = rk3399_dram_status.timing_config.ch_cnt; 2331 uint32_t dram_type = rk3399_dram_status.timing_config.dram_type; 2332 2333 if (dram_type == LPDDR4) 2334 tmp = (lp_config->srpd_lite_idle << 16) | 2335 lp_config->pd_idle; 2336 else 2337 tmp = lp_config->pd_idle; 2338 2339 if (dram_type == DDR3) 2340 tmp1 = (2 << 16) | (0x7 << 8) | 7; 2341 else 2342 tmp1 = (3 << 16) | (0x7 << 8) | 7; 2343 2344 for (i = 0; i < ch_cnt; i++) { 2345 write_32(&rk3399_ddr_pctl[i]->denali_ctl[102], tmp); 2346 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[103], 0xffff, 2347 (lp_config->sr_mc_gate_idle << 8) | 2348 lp_config->sr_idle); 2349 clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[101], 2350 0x70f0f, tmp1); 2351 } 2352 2353 /* standby idle */ 2354 write_32(&rk3399_ddr_cic->cic_idle_th, lp_config->standby_idle); 2355 write_32(&rk3399_ddr_cic->cic_cg_wait_th, 0x640008); 2356 2357 if (ch_cnt == 2) { 2358 write_32(GRF_BASE + GRF_DDRC1_CON1, 2359 (((0x1<<4) | (0x1<<5) | (0x1<<6) | (0x1<<7)) << 16) | 2360 ((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7))); 2361 if (lp_config->standby_idle) 2362 tmp = 0x002a002a; 2363 else 2364 tmp = 0; 2365 write_32(&rk3399_ddr_cic->cic_ctrl1, tmp); 2366 } 2367 2368 write_32(GRF_BASE + GRF_DDRC0_CON1, 2369 (((0x1<<4) | (0x1<<5) | (0x1<<6) | (0x1<<7)) << 16) | 2370 ((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7))); 2371 if (lp_config->standby_idle) 2372 tmp = 0x00150015; 2373 else 2374 tmp = 0; 2375 write_32(&rk3399_ddr_cic->cic_ctrl1, tmp); 2376 } 2377 2378 2379 static void dram_related_init(struct ddr_dts_config_timing *dts_timing) 2380 { 2381 uint32_t trefi0, trefi1; 2382 uint32_t i; 2383 struct rk3399_sdram_config sdram_config; 2384 2385 dcf_code_init(); 2386 2387 /* get sdram config for os reg */ 2388 sdram_config_init(&sdram_config); 2389 drv_odt_lp_cfg_init(sdram_config.dramtype, dts_timing, 2390 &rk3399_dram_status.drv_odt_lp_cfg); 2391 sdram_timing_cfg_init(&rk3399_dram_status.timing_config, 2392 &sdram_config, 2393 &rk3399_dram_status.drv_odt_lp_cfg); 2394 2395 trefi0 = ((read_32(&rk3399_ddr_pctl[0]->denali_ctl[48]) >> 2396 16) & 0xffff) + 8; 2397 trefi1 = ((read_32(&rk3399_ddr_pctl[0]->denali_ctl[49]) >> 2398 16) & 0xffff) + 8; 2399 2400 rk3399_dram_status.index_freq[0] = trefi0 * 10 / 39; 2401 rk3399_dram_status.index_freq[1] = trefi1 * 10 / 39; 2402 rk3399_dram_status.current_index = 2403 (read_32(&rk3399_ddr_pctl[0]->denali_ctl[111]) 2404 >> 16) & 0x3; 2405 if (rk3399_dram_status.timing_config.dram_type == DDR3) { 2406 rk3399_dram_status.index_freq[0] /= 2; 2407 rk3399_dram_status.index_freq[1] /= 2; 2408 } 2409 rk3399_dram_status.index_freq[(rk3399_dram_status.current_index + 1) 2410 & 0x1] = 0; 2411 2412 /* disable all training by ctl and pi */ 2413 for (i = 0; i < rk3399_dram_status.timing_config.ch_cnt; i++) { 2414 clrbits_32(&rk3399_ddr_pctl[i]->denali_ctl[70], (1 << 24) | 2415 (1 << 16) | (1 << 8) | 1); 2416 clrbits_32(&rk3399_ddr_pctl[i]->denali_ctl[71], 1); 2417 2418 clrbits_32(&rk3399_ddr_pi[i]->denali_pi[60], 0x3 << 8); 2419 clrbits_32(&rk3399_ddr_pi[i]->denali_pi[80], (0x3 << 24) | 2420 (0x3 << 16)); 2421 clrbits_32(&rk3399_ddr_pi[i]->denali_pi[100], 0x3 << 8); 2422 clrbits_32(&rk3399_ddr_pi[i]->denali_pi[124], 0x3 << 16); 2423 } 2424 2425 /* init drv odt */ 2426 if (rk3399_dram_status.index_freq[rk3399_dram_status.current_index] < 2427 rk3399_dram_status.drv_odt_lp_cfg.odt_dis_freq) 2428 rk3399_dram_status.timing_config.odt = 0; 2429 else 2430 rk3399_dram_status.timing_config.odt = 1; 2431 gen_rk3399_set_ds_odt(&rk3399_dram_status.timing_config, 2432 &rk3399_dram_status.drv_odt_lp_cfg); 2433 dram_low_power_config(&rk3399_dram_status.drv_odt_lp_cfg); 2434 } 2435 2436 static uint32_t prepare_ddr_timing(uint32_t mhz) 2437 { 2438 uint32_t index; 2439 struct dram_timing_t dram_timing; 2440 2441 rk3399_dram_status.timing_config.freq = mhz; 2442 2443 if (mhz < rk3399_dram_status.drv_odt_lp_cfg.ddr3_dll_dis_freq) 2444 rk3399_dram_status.timing_config.dllbp = 1; 2445 else 2446 rk3399_dram_status.timing_config.dllbp = 0; 2447 if (mhz < rk3399_dram_status.drv_odt_lp_cfg.odt_dis_freq) { 2448 rk3399_dram_status.timing_config.odt = 0; 2449 } else { 2450 rk3399_dram_status.timing_config.odt = 1; 2451 gen_rk3399_set_odt(1); 2452 } 2453 2454 index = (rk3399_dram_status.current_index + 1) & 0x1; 2455 if (rk3399_dram_status.index_freq[index] == mhz) 2456 goto out; 2457 2458 /* 2459 * checking if having available gate traiing timing for 2460 * target freq. 2461 */ 2462 dram_get_parameter(&rk3399_dram_status.timing_config, &dram_timing); 2463 2464 gen_rk3399_ctl_params(&rk3399_dram_status.timing_config, 2465 &dram_timing, index); 2466 gen_rk3399_pi_params(&rk3399_dram_status.timing_config, 2467 &dram_timing, index); 2468 gen_rk3399_phy_params(&rk3399_dram_status.timing_config, 2469 &rk3399_dram_status.drv_odt_lp_cfg, 2470 &dram_timing, index); 2471 rk3399_dram_status.index_freq[index] = mhz; 2472 2473 2474 out: 2475 return index; 2476 } 2477 2478 void print_dram_status_info(void) 2479 { 2480 uint32_t *p; 2481 uint32_t i; 2482 2483 p = (uint32_t *) &rk3399_dram_status.timing_config; 2484 INFO("rk3399_dram_status.timing_config:\n"); 2485 for (i = 0; i < sizeof(struct timing_related_config) / 4; i++) 2486 tf_printf("%u\n", p[i]); 2487 p = (uint32_t *) &rk3399_dram_status.drv_odt_lp_cfg; 2488 INFO("rk3399_dram_status.drv_odt_lp_cfg:\n"); 2489 for (i = 0; i < sizeof(struct drv_odt_lp_config) / 4; i++) 2490 tf_printf("%u\n", p[i]); 2491 } 2492 2493 uint64_t ddr_set_rate(uint64_t hz) 2494 { 2495 uint32_t low_power, index; 2496 uint32_t mhz = hz / (1000 * 1000); 2497 2498 if (mhz == 2499 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]) 2500 goto out; 2501 2502 low_power = exit_low_power(); 2503 index = prepare_ddr_timing(mhz); 2504 if (index > 1) { 2505 /* set timing error, quit */ 2506 mhz = 0; 2507 goto out; 2508 } 2509 2510 dcf_start(mhz, index); 2511 wait_dcf_done(); 2512 if (rk3399_dram_status.timing_config.odt == 0) 2513 gen_rk3399_set_odt(0); 2514 2515 rk3399_dram_status.current_index = index; 2516 resume_low_power(low_power); 2517 out: 2518 return mhz; 2519 } 2520 2521 uint64_t ddr_round_rate(uint64_t hz) 2522 { 2523 int index; 2524 uint32_t mhz = hz / (1000 * 1000); 2525 2526 index = to_get_clk_index(mhz); 2527 2528 return dpll_rates_table[index].mhz * 1000 * 1000; 2529 } 2530 2531 uint64_t dts_timing_receive(uint64_t timing, uint64_t index) 2532 { 2533 uint32_t *p = (uint32_t *) &dts_parameter; 2534 static uint32_t receive_nums; 2535 2536 if (index < (sizeof(dts_parameter) / sizeof(uint32_t) - 1)) { 2537 p[index] = (uint32_t)timing; 2538 receive_nums++; 2539 } else { 2540 dts_parameter.available = 0; 2541 return -1; 2542 } 2543 2544 /* receive all parameter */ 2545 if (receive_nums == (sizeof(dts_parameter) / sizeof(uint32_t) - 1)) { 2546 dts_parameter.available = 1; 2547 receive_nums = 0; 2548 } 2549 2550 return index; 2551 } 2552 2553 void ddr_init(void) 2554 { 2555 dram_related_init(&dts_parameter); 2556 } 2557