1fe877779SCaesar Wang /* 2fe877779SCaesar Wang * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3fe877779SCaesar Wang * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5fe877779SCaesar Wang */ 6fe877779SCaesar Wang 7613038bcSCaesar Wang #include <dram.h> 8fe877779SCaesar Wang #include <plat_private.h> 9e3525114SXing Zheng #include <secure.h> 10613038bcSCaesar Wang #include <soc.h> 11613038bcSCaesar Wang #include <rk3399_def.h> 12fe877779SCaesar Wang 13*af27fb89SDerek Basehore __pmusramdata struct rk3399_sdram_params sdram_config; 14fe877779SCaesar Wang 15613038bcSCaesar Wang void dram_init(void) 16fe877779SCaesar Wang { 17fe877779SCaesar Wang uint32_t os_reg2_val, i; 18fe877779SCaesar Wang 19613038bcSCaesar Wang os_reg2_val = mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)); 20613038bcSCaesar Wang sdram_config.dramtype = SYS_REG_DEC_DDRTYPE(os_reg2_val); 21613038bcSCaesar Wang sdram_config.num_channels = SYS_REG_DEC_NUM_CH(os_reg2_val); 22613038bcSCaesar Wang sdram_config.stride = (mmio_read_32(SGRF_BASE + SGRF_SOC_CON3_7(4)) >> 23613038bcSCaesar Wang 10) & 0x1f; 24fe877779SCaesar Wang 25613038bcSCaesar Wang for (i = 0; i < 2; i++) { 26613038bcSCaesar Wang struct rk3399_sdram_channel *ch = &sdram_config.ch[i]; 27613038bcSCaesar Wang struct rk3399_msch_timings *noc = &ch->noc_timings; 28fe877779SCaesar Wang 29613038bcSCaesar Wang if (!(SYS_REG_DEC_CHINFO(os_reg2_val, i))) 30fe877779SCaesar Wang continue; 31fe877779SCaesar Wang 32613038bcSCaesar Wang ch->rank = SYS_REG_DEC_RANK(os_reg2_val, i); 33613038bcSCaesar Wang ch->col = SYS_REG_DEC_COL(os_reg2_val, i); 34613038bcSCaesar Wang ch->bk = SYS_REG_DEC_BK(os_reg2_val, i); 35613038bcSCaesar Wang ch->bw = SYS_REG_DEC_BW(os_reg2_val, i); 36613038bcSCaesar Wang ch->dbw = SYS_REG_DEC_DBW(os_reg2_val, i); 37613038bcSCaesar Wang ch->row_3_4 = SYS_REG_DEC_ROW_3_4(os_reg2_val, i); 38613038bcSCaesar Wang ch->cs0_row = SYS_REG_DEC_CS0_ROW(os_reg2_val, i); 39613038bcSCaesar Wang ch->cs1_row = SYS_REG_DEC_CS1_ROW(os_reg2_val, i); 40613038bcSCaesar Wang ch->ddrconfig = mmio_read_32(MSCH_BASE(i) + MSCH_DEVICECONF); 41613038bcSCaesar Wang 42613038bcSCaesar Wang noc->ddrtiminga0.d32 = mmio_read_32(MSCH_BASE(i) + 43613038bcSCaesar Wang MSCH_DDRTIMINGA0); 44613038bcSCaesar Wang noc->ddrtimingb0.d32 = mmio_read_32(MSCH_BASE(i) + 45613038bcSCaesar Wang MSCH_DDRTIMINGB0); 46613038bcSCaesar Wang noc->ddrtimingc0.d32 = mmio_read_32(MSCH_BASE(i) + 47613038bcSCaesar Wang MSCH_DDRTIMINGC0); 48613038bcSCaesar Wang noc->devtodev0.d32 = mmio_read_32(MSCH_BASE(i) + 49613038bcSCaesar Wang MSCH_DEVTODEV0); 50613038bcSCaesar Wang noc->ddrmode.d32 = mmio_read_32(MSCH_BASE(i) + MSCH_DDRMODE); 51613038bcSCaesar Wang noc->agingx0 = mmio_read_32(MSCH_BASE(i) + MSCH_AGINGX0); 52fe877779SCaesar Wang } 53fe877779SCaesar Wang } 54