1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __SOC_ROCKCHIP_RK3399_DFS_H__ 32 #define __SOC_ROCKCHIP_RK3399_DFS_H__ 33 34 struct rk3399_sdram_default_config { 35 unsigned char bl; 36 /* 1:auto precharge, 0:never auto precharge */ 37 unsigned char ap; 38 /* dram driver strength */ 39 unsigned char dramds; 40 /* dram ODT, if odt=0, this parameter invalid */ 41 unsigned char dramodt; 42 /* ca ODT, if odt=0, this parameter invalid 43 * only used by LPDDR4 44 */ 45 unsigned char caodt; 46 unsigned char burst_ref_cnt; 47 /* zqcs period, unit(s) */ 48 unsigned char zqcsi; 49 }; 50 51 struct ddr_dts_config_timing { 52 unsigned int ddr3_speed_bin; 53 unsigned int pd_idle; 54 unsigned int sr_idle; 55 unsigned int sr_mc_gate_idle; 56 unsigned int srpd_lite_idle; 57 unsigned int standby_idle; 58 unsigned int auto_pd_dis_freq; 59 unsigned int ddr3_dll_dis_freq; 60 unsigned int phy_dll_dis_freq; 61 unsigned int ddr3_odt_dis_freq; 62 unsigned int ddr3_drv; 63 unsigned int ddr3_odt; 64 unsigned int phy_ddr3_ca_drv; 65 unsigned int phy_ddr3_dq_drv; 66 unsigned int phy_ddr3_odt; 67 unsigned int lpddr3_odt_dis_freq; 68 unsigned int lpddr3_drv; 69 unsigned int lpddr3_odt; 70 unsigned int phy_lpddr3_ca_drv; 71 unsigned int phy_lpddr3_dq_drv; 72 unsigned int phy_lpddr3_odt; 73 unsigned int lpddr4_odt_dis_freq; 74 unsigned int lpddr4_drv; 75 unsigned int lpddr4_dq_odt; 76 unsigned int lpddr4_ca_odt; 77 unsigned int phy_lpddr4_ca_drv; 78 unsigned int phy_lpddr4_ck_cs_drv; 79 unsigned int phy_lpddr4_dq_drv; 80 unsigned int phy_lpddr4_odt; 81 uint32_t available; 82 }; 83 84 struct drv_odt_lp_config { 85 uint32_t ddr3_speed_bin; 86 uint32_t pd_idle; 87 uint32_t sr_idle; 88 uint32_t sr_mc_gate_idle; 89 uint32_t srpd_lite_idle; 90 uint32_t standby_idle; 91 92 uint32_t ddr3_dll_dis_freq;/* for ddr3 only */ 93 uint32_t phy_dll_dis_freq; 94 uint32_t odt_dis_freq; 95 96 uint32_t dram_side_drv; 97 uint32_t dram_side_dq_odt; 98 uint32_t dram_side_ca_odt; 99 100 uint32_t phy_side_ca_drv; 101 uint32_t phy_side_ck_cs_drv; 102 uint32_t phy_side_dq_drv; 103 uint32_t phy_side_odt; 104 }; 105 106 void ddr_dfs_init(void); 107 uint32_t ddr_set_rate(uint32_t hz); 108 uint32_t ddr_round_rate(uint32_t hz); 109 uint32_t ddr_get_rate(void); 110 void clr_dcf_irq(void); 111 uint32_t dts_timing_receive(uint32_t timing, uint32_t index); 112 #endif 113