1*613038bcSCaesar Wang /* 2*613038bcSCaesar Wang * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3*613038bcSCaesar Wang * 4*613038bcSCaesar Wang * Redistribution and use in source and binary forms, with or without 5*613038bcSCaesar Wang * modification, are permitted provided that the following conditions are met: 6*613038bcSCaesar Wang * 7*613038bcSCaesar Wang * Redistributions of source code must retain the above copyright notice, this 8*613038bcSCaesar Wang * list of conditions and the following disclaimer. 9*613038bcSCaesar Wang * 10*613038bcSCaesar Wang * Redistributions in binary form must reproduce the above copyright notice, 11*613038bcSCaesar Wang * this list of conditions and the following disclaimer in the documentation 12*613038bcSCaesar Wang * and/or other materials provided with the distribution. 13*613038bcSCaesar Wang * 14*613038bcSCaesar Wang * Neither the name of ARM nor the names of its contributors may be used 15*613038bcSCaesar Wang * to endorse or promote products derived from this software without specific 16*613038bcSCaesar Wang * prior written permission. 17*613038bcSCaesar Wang * 18*613038bcSCaesar Wang * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*613038bcSCaesar Wang * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*613038bcSCaesar Wang * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*613038bcSCaesar Wang * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*613038bcSCaesar Wang * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*613038bcSCaesar Wang * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*613038bcSCaesar Wang * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*613038bcSCaesar Wang * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*613038bcSCaesar Wang * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*613038bcSCaesar Wang * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*613038bcSCaesar Wang * POSSIBILITY OF SUCH DAMAGE. 29*613038bcSCaesar Wang */ 30*613038bcSCaesar Wang 31*613038bcSCaesar Wang #ifndef __SOC_ROCKCHIP_RK3399_DFS_H__ 32*613038bcSCaesar Wang #define __SOC_ROCKCHIP_RK3399_DFS_H__ 33*613038bcSCaesar Wang 34*613038bcSCaesar Wang struct rk3399_sdram_default_config { 35*613038bcSCaesar Wang unsigned char bl; 36*613038bcSCaesar Wang /* 1:auto precharge, 0:never auto precharge */ 37*613038bcSCaesar Wang unsigned char ap; 38*613038bcSCaesar Wang /* dram driver strength */ 39*613038bcSCaesar Wang unsigned char dramds; 40*613038bcSCaesar Wang /* dram ODT, if odt=0, this parameter invalid */ 41*613038bcSCaesar Wang unsigned char dramodt; 42*613038bcSCaesar Wang /* ca ODT, if odt=0, this parameter invalid 43*613038bcSCaesar Wang * only used by LPDDR4 44*613038bcSCaesar Wang */ 45*613038bcSCaesar Wang unsigned char caodt; 46*613038bcSCaesar Wang unsigned char burst_ref_cnt; 47*613038bcSCaesar Wang /* zqcs period, unit(s) */ 48*613038bcSCaesar Wang unsigned char zqcsi; 49*613038bcSCaesar Wang }; 50*613038bcSCaesar Wang 51*613038bcSCaesar Wang struct ddr_dts_config_timing { 52*613038bcSCaesar Wang unsigned int ddr3_speed_bin; 53*613038bcSCaesar Wang unsigned int pd_idle; 54*613038bcSCaesar Wang unsigned int sr_idle; 55*613038bcSCaesar Wang unsigned int sr_mc_gate_idle; 56*613038bcSCaesar Wang unsigned int srpd_lite_idle; 57*613038bcSCaesar Wang unsigned int standby_idle; 58*613038bcSCaesar Wang unsigned int auto_pd_dis_freq; 59*613038bcSCaesar Wang unsigned int ddr3_dll_dis_freq; 60*613038bcSCaesar Wang unsigned int phy_dll_dis_freq; 61*613038bcSCaesar Wang unsigned int ddr3_odt_dis_freq; 62*613038bcSCaesar Wang unsigned int ddr3_drv; 63*613038bcSCaesar Wang unsigned int ddr3_odt; 64*613038bcSCaesar Wang unsigned int phy_ddr3_ca_drv; 65*613038bcSCaesar Wang unsigned int phy_ddr3_dq_drv; 66*613038bcSCaesar Wang unsigned int phy_ddr3_odt; 67*613038bcSCaesar Wang unsigned int lpddr3_odt_dis_freq; 68*613038bcSCaesar Wang unsigned int lpddr3_drv; 69*613038bcSCaesar Wang unsigned int lpddr3_odt; 70*613038bcSCaesar Wang unsigned int phy_lpddr3_ca_drv; 71*613038bcSCaesar Wang unsigned int phy_lpddr3_dq_drv; 72*613038bcSCaesar Wang unsigned int phy_lpddr3_odt; 73*613038bcSCaesar Wang unsigned int lpddr4_odt_dis_freq; 74*613038bcSCaesar Wang unsigned int lpddr4_drv; 75*613038bcSCaesar Wang unsigned int lpddr4_dq_odt; 76*613038bcSCaesar Wang unsigned int lpddr4_ca_odt; 77*613038bcSCaesar Wang unsigned int phy_lpddr4_ca_drv; 78*613038bcSCaesar Wang unsigned int phy_lpddr4_ck_cs_drv; 79*613038bcSCaesar Wang unsigned int phy_lpddr4_dq_drv; 80*613038bcSCaesar Wang unsigned int phy_lpddr4_odt; 81*613038bcSCaesar Wang uint32_t available; 82*613038bcSCaesar Wang }; 83*613038bcSCaesar Wang 84*613038bcSCaesar Wang struct drv_odt_lp_config { 85*613038bcSCaesar Wang uint32_t ddr3_speed_bin; 86*613038bcSCaesar Wang uint32_t pd_idle; 87*613038bcSCaesar Wang uint32_t sr_idle; 88*613038bcSCaesar Wang uint32_t sr_mc_gate_idle; 89*613038bcSCaesar Wang uint32_t srpd_lite_idle; 90*613038bcSCaesar Wang uint32_t standby_idle; 91*613038bcSCaesar Wang 92*613038bcSCaesar Wang uint32_t ddr3_dll_dis_freq;/* for ddr3 only */ 93*613038bcSCaesar Wang uint32_t phy_dll_dis_freq; 94*613038bcSCaesar Wang uint32_t odt_dis_freq; 95*613038bcSCaesar Wang 96*613038bcSCaesar Wang uint32_t dram_side_drv; 97*613038bcSCaesar Wang uint32_t dram_side_dq_odt; 98*613038bcSCaesar Wang uint32_t dram_side_ca_odt; 99*613038bcSCaesar Wang 100*613038bcSCaesar Wang uint32_t phy_side_ca_drv; 101*613038bcSCaesar Wang uint32_t phy_side_ck_cs_drv; 102*613038bcSCaesar Wang uint32_t phy_side_dq_drv; 103*613038bcSCaesar Wang uint32_t phy_side_odt; 104*613038bcSCaesar Wang }; 105*613038bcSCaesar Wang 106*613038bcSCaesar Wang void ddr_dfs_init(void); 107*613038bcSCaesar Wang uint32_t ddr_set_rate(uint32_t hz); 108*613038bcSCaesar Wang uint32_t ddr_round_rate(uint32_t hz); 109*613038bcSCaesar Wang uint32_t ddr_get_rate(void); 110*613038bcSCaesar Wang void clr_dcf_irq(void); 111*613038bcSCaesar Wang uint32_t dts_timing_receive(uint32_t timing, uint32_t index); 112*613038bcSCaesar Wang #endif 113