1 /* 2 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <common/debug.h> 9 #include <drivers/delay_timer.h> 10 #include <lib/mmio.h> 11 12 #include <m0_ctl.h> 13 #include <plat_private.h> 14 #include "dfs.h" 15 #include "dram.h" 16 #include "dram_spec_timing.h" 17 #include "pmu.h" 18 #include "soc.h" 19 #include "string.h" 20 21 #define ENPER_CS_TRAINING_FREQ (666) 22 #define TDFI_LAT_THRESHOLD_FREQ (928) 23 #define PHY_DLL_BYPASS_FREQ (260) 24 25 static const struct pll_div dpll_rates_table[] = { 26 27 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2 */ 28 {.mhz = 928, .refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}, 29 {.mhz = 800, .refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}, 30 {.mhz = 732, .refdiv = 1, .fbdiv = 61, .postdiv1 = 2, .postdiv2 = 1}, 31 {.mhz = 666, .refdiv = 1, .fbdiv = 111, .postdiv1 = 4, .postdiv2 = 1}, 32 {.mhz = 600, .refdiv = 1, .fbdiv = 50, .postdiv1 = 2, .postdiv2 = 1}, 33 {.mhz = 528, .refdiv = 1, .fbdiv = 66, .postdiv1 = 3, .postdiv2 = 1}, 34 {.mhz = 400, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}, 35 {.mhz = 300, .refdiv = 1, .fbdiv = 50, .postdiv1 = 4, .postdiv2 = 1}, 36 {.mhz = 200, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 2}, 37 }; 38 39 struct rk3399_dram_status { 40 uint32_t current_index; 41 uint32_t index_freq[2]; 42 uint32_t boot_freq; 43 uint32_t low_power_stat; 44 struct timing_related_config timing_config; 45 struct drv_odt_lp_config drv_odt_lp_cfg; 46 }; 47 48 struct rk3399_saved_status { 49 uint32_t freq; 50 uint32_t low_power_stat; 51 uint32_t odt; 52 }; 53 54 static struct rk3399_dram_status rk3399_dram_status; 55 static struct rk3399_saved_status rk3399_suspend_status; 56 static uint32_t wrdqs_delay_val[2][2][4]; 57 static uint32_t rddqs_delay_ps; 58 59 static struct rk3399_sdram_default_config ddr3_default_config = { 60 .bl = 8, 61 .ap = 0, 62 .burst_ref_cnt = 1, 63 .zqcsi = 0 64 }; 65 66 static struct rk3399_sdram_default_config lpddr3_default_config = { 67 .bl = 8, 68 .ap = 0, 69 .burst_ref_cnt = 1, 70 .zqcsi = 0 71 }; 72 73 static struct rk3399_sdram_default_config lpddr4_default_config = { 74 .bl = 16, 75 .ap = 0, 76 .caodt = 240, 77 .burst_ref_cnt = 1, 78 .zqcsi = 0 79 }; 80 81 static uint32_t get_cs_die_capability(struct rk3399_sdram_params *ram_config, 82 uint8_t channel, uint8_t cs) 83 { 84 struct rk3399_sdram_channel *ch = &ram_config->ch[channel]; 85 uint32_t bandwidth; 86 uint32_t die_bandwidth; 87 uint32_t die; 88 uint32_t cs_cap; 89 uint32_t row; 90 91 row = cs == 0 ? ch->cs0_row : ch->cs1_row; 92 bandwidth = 8 * (1 << ch->bw); 93 die_bandwidth = 8 * (1 << ch->dbw); 94 die = bandwidth / die_bandwidth; 95 cs_cap = (1 << (row + ((1 << ch->bk) / 4 + 1) + ch->col + 96 (bandwidth / 16))); 97 if (ch->row_3_4) 98 cs_cap = cs_cap * 3 / 4; 99 100 return (cs_cap / die); 101 } 102 103 static void get_dram_drv_odt_val(uint32_t dram_type, 104 struct drv_odt_lp_config *drv_config) 105 { 106 uint32_t tmp; 107 uint32_t mr1_val, mr3_val, mr11_val; 108 109 switch (dram_type) { 110 case DDR3: 111 mr1_val = (mmio_read_32(CTL_REG(0, 133)) >> 16) & 0xffff; 112 tmp = ((mr1_val >> 1) & 1) | ((mr1_val >> 4) & 1); 113 if (tmp) 114 drv_config->dram_side_drv = 34; 115 else 116 drv_config->dram_side_drv = 40; 117 tmp = ((mr1_val >> 2) & 1) | ((mr1_val >> 5) & 1) | 118 ((mr1_val >> 7) & 1); 119 if (tmp == 0) 120 drv_config->dram_side_dq_odt = 0; 121 else if (tmp == 1) 122 drv_config->dram_side_dq_odt = 60; 123 else if (tmp == 3) 124 drv_config->dram_side_dq_odt = 40; 125 else 126 drv_config->dram_side_dq_odt = 120; 127 break; 128 case LPDDR3: 129 mr3_val = mmio_read_32(CTL_REG(0, 138)) & 0xf; 130 mr11_val = (mmio_read_32(CTL_REG(0, 139)) >> 24) & 0x3; 131 if (mr3_val == 0xb) 132 drv_config->dram_side_drv = 3448; 133 else if (mr3_val == 0xa) 134 drv_config->dram_side_drv = 4048; 135 else if (mr3_val == 0x9) 136 drv_config->dram_side_drv = 3440; 137 else if (mr3_val == 0x4) 138 drv_config->dram_side_drv = 60; 139 else if (mr3_val == 0x3) 140 drv_config->dram_side_drv = 48; 141 else if (mr3_val == 0x2) 142 drv_config->dram_side_drv = 40; 143 else 144 drv_config->dram_side_drv = 34; 145 146 if (mr11_val == 1) 147 drv_config->dram_side_dq_odt = 60; 148 else if (mr11_val == 2) 149 drv_config->dram_side_dq_odt = 120; 150 else if (mr11_val == 0) 151 drv_config->dram_side_dq_odt = 0; 152 else 153 drv_config->dram_side_dq_odt = 240; 154 break; 155 case LPDDR4: 156 default: 157 mr3_val = (mmio_read_32(CTL_REG(0, 138)) >> 3) & 0x7; 158 mr11_val = (mmio_read_32(CTL_REG(0, 139)) >> 24) & 0xff; 159 160 if ((mr3_val == 0) || (mr3_val == 7)) 161 drv_config->dram_side_drv = 40; 162 else 163 drv_config->dram_side_drv = 240 / mr3_val; 164 165 tmp = mr11_val & 0x7; 166 if ((tmp == 7) || (tmp == 0)) 167 drv_config->dram_side_dq_odt = 0; 168 else 169 drv_config->dram_side_dq_odt = 240 / tmp; 170 171 tmp = (mr11_val >> 4) & 0x7; 172 if ((tmp == 7) || (tmp == 0)) 173 drv_config->dram_side_ca_odt = 0; 174 else 175 drv_config->dram_side_ca_odt = 240 / tmp; 176 break; 177 } 178 } 179 180 static void sdram_timing_cfg_init(struct timing_related_config *ptiming_config, 181 struct rk3399_sdram_params *sdram_params, 182 struct drv_odt_lp_config *drv_config) 183 { 184 uint32_t i, j; 185 186 for (i = 0; i < sdram_params->num_channels; i++) { 187 ptiming_config->dram_info[i].speed_rate = DDR3_DEFAULT; 188 ptiming_config->dram_info[i].cs_cnt = sdram_params->ch[i].rank; 189 for (j = 0; j < sdram_params->ch[i].rank; j++) { 190 ptiming_config->dram_info[i].per_die_capability[j] = 191 get_cs_die_capability(sdram_params, i, j); 192 } 193 } 194 ptiming_config->dram_type = sdram_params->dramtype; 195 ptiming_config->ch_cnt = sdram_params->num_channels; 196 switch (sdram_params->dramtype) { 197 case DDR3: 198 ptiming_config->bl = ddr3_default_config.bl; 199 ptiming_config->ap = ddr3_default_config.ap; 200 break; 201 case LPDDR3: 202 ptiming_config->bl = lpddr3_default_config.bl; 203 ptiming_config->ap = lpddr3_default_config.ap; 204 break; 205 case LPDDR4: 206 ptiming_config->bl = lpddr4_default_config.bl; 207 ptiming_config->ap = lpddr4_default_config.ap; 208 ptiming_config->rdbi = 0; 209 ptiming_config->wdbi = 0; 210 break; 211 default: 212 /* Do nothing in default case */ 213 break; 214 } 215 ptiming_config->dramds = drv_config->dram_side_drv; 216 ptiming_config->dramodt = drv_config->dram_side_dq_odt; 217 ptiming_config->caodt = drv_config->dram_side_ca_odt; 218 ptiming_config->odt = (mmio_read_32(PHY_REG(0, 5)) >> 16) & 0x1; 219 } 220 221 struct lat_adj_pair { 222 uint32_t cl; 223 uint32_t rdlat_adj; 224 uint32_t cwl; 225 uint32_t wrlat_adj; 226 }; 227 228 const struct lat_adj_pair ddr3_lat_adj[] = { 229 {6, 5, 5, 4}, 230 {8, 7, 6, 5}, 231 {10, 9, 7, 6}, 232 {11, 9, 8, 7}, 233 {13, 0xb, 9, 8}, 234 {14, 0xb, 0xa, 9} 235 }; 236 237 const struct lat_adj_pair lpddr3_lat_adj[] = { 238 {3, 2, 1, 0}, 239 {6, 5, 3, 2}, 240 {8, 7, 4, 3}, 241 {9, 8, 5, 4}, 242 {10, 9, 6, 5}, 243 {11, 9, 6, 5}, 244 {12, 0xa, 6, 5}, 245 {14, 0xc, 8, 7}, 246 {16, 0xd, 8, 7} 247 }; 248 249 const struct lat_adj_pair lpddr4_lat_adj[] = { 250 {6, 5, 4, 2}, 251 {10, 9, 6, 4}, 252 {14, 0xc, 8, 6}, 253 {20, 0x11, 0xa, 8}, 254 {24, 0x15, 0xc, 0xa}, 255 {28, 0x18, 0xe, 0xc}, 256 {32, 0x1b, 0x10, 0xe}, 257 {36, 0x1e, 0x12, 0x10} 258 }; 259 260 static uint32_t get_rdlat_adj(uint32_t dram_type, uint32_t cl) 261 { 262 const struct lat_adj_pair *p; 263 uint32_t cnt; 264 uint32_t i; 265 266 if (dram_type == DDR3) { 267 p = ddr3_lat_adj; 268 cnt = ARRAY_SIZE(ddr3_lat_adj); 269 } else if (dram_type == LPDDR3) { 270 p = lpddr3_lat_adj; 271 cnt = ARRAY_SIZE(lpddr3_lat_adj); 272 } else { 273 p = lpddr4_lat_adj; 274 cnt = ARRAY_SIZE(lpddr4_lat_adj); 275 } 276 277 for (i = 0; i < cnt; i++) { 278 if (cl == p[i].cl) 279 return p[i].rdlat_adj; 280 } 281 /* fail */ 282 return 0xff; 283 } 284 285 static uint32_t get_wrlat_adj(uint32_t dram_type, uint32_t cwl) 286 { 287 const struct lat_adj_pair *p; 288 uint32_t cnt; 289 uint32_t i; 290 291 if (dram_type == DDR3) { 292 p = ddr3_lat_adj; 293 cnt = ARRAY_SIZE(ddr3_lat_adj); 294 } else if (dram_type == LPDDR3) { 295 p = lpddr3_lat_adj; 296 cnt = ARRAY_SIZE(lpddr3_lat_adj); 297 } else { 298 p = lpddr4_lat_adj; 299 cnt = ARRAY_SIZE(lpddr4_lat_adj); 300 } 301 302 for (i = 0; i < cnt; i++) { 303 if (cwl == p[i].cwl) 304 return p[i].wrlat_adj; 305 } 306 /* fail */ 307 return 0xff; 308 } 309 310 #define PI_REGS_DIMM_SUPPORT (0) 311 #define PI_ADD_LATENCY (0) 312 #define PI_DOUBLEFREEK (1) 313 314 #define PI_PAD_DELAY_PS_VALUE (1000) 315 #define PI_IE_ENABLE_VALUE (3000) 316 #define PI_TSEL_ENABLE_VALUE (700) 317 318 static uint32_t get_pi_rdlat_adj(struct dram_timing_t *pdram_timing) 319 { 320 /*[DLLSUBTYPE2] == "STD_DENALI_HS" */ 321 uint32_t rdlat, delay_adder, ie_enable, hs_offset, tsel_adder, 322 extra_adder, tsel_enable; 323 324 ie_enable = PI_IE_ENABLE_VALUE; 325 tsel_enable = PI_TSEL_ENABLE_VALUE; 326 327 rdlat = pdram_timing->cl + PI_ADD_LATENCY; 328 delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 329 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 330 delay_adder++; 331 hs_offset = 0; 332 tsel_adder = 0; 333 extra_adder = 0; 334 /* rdlat = rdlat - (PREAMBLE_SUPPORT & 0x1); */ 335 tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz); 336 if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0) 337 tsel_adder++; 338 delay_adder = delay_adder - 1; 339 if (tsel_adder > delay_adder) 340 extra_adder = tsel_adder - delay_adder; 341 else 342 extra_adder = 0; 343 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 344 hs_offset = 2; 345 else 346 hs_offset = 1; 347 348 if (delay_adder > (rdlat - 1 - hs_offset)) { 349 rdlat = rdlat - tsel_adder; 350 } else { 351 if ((rdlat - delay_adder) < 2) 352 rdlat = 2; 353 else 354 rdlat = rdlat - delay_adder - extra_adder; 355 } 356 357 return rdlat; 358 } 359 360 static uint32_t get_pi_wrlat(struct dram_timing_t *pdram_timing, 361 struct timing_related_config *timing_config) 362 { 363 uint32_t tmp; 364 365 if (timing_config->dram_type == LPDDR3) { 366 tmp = pdram_timing->cl; 367 if (tmp >= 14) 368 tmp = 8; 369 else if (tmp >= 10) 370 tmp = 6; 371 else if (tmp == 9) 372 tmp = 5; 373 else if (tmp == 8) 374 tmp = 4; 375 else if (tmp == 6) 376 tmp = 3; 377 else 378 tmp = 1; 379 } else { 380 tmp = 1; 381 } 382 383 return tmp; 384 } 385 386 static uint32_t get_pi_wrlat_adj(struct dram_timing_t *pdram_timing, 387 struct timing_related_config *timing_config) 388 { 389 return get_pi_wrlat(pdram_timing, timing_config) + PI_ADD_LATENCY - 1; 390 } 391 392 static uint32_t get_pi_tdfi_phy_rdlat(struct dram_timing_t *pdram_timing, 393 struct timing_related_config *timing_config) 394 { 395 /* [DLLSUBTYPE2] == "STD_DENALI_HS" */ 396 uint32_t cas_lat, delay_adder, ie_enable, hs_offset, ie_delay_adder; 397 uint32_t mem_delay_ps, round_trip_ps; 398 uint32_t phy_internal_delay, lpddr_adder, dfi_adder, rdlat_delay; 399 400 ie_enable = PI_IE_ENABLE_VALUE; 401 402 delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 403 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 404 delay_adder++; 405 delay_adder = delay_adder - 1; 406 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 407 hs_offset = 2; 408 else 409 hs_offset = 1; 410 411 cas_lat = pdram_timing->cl + PI_ADD_LATENCY; 412 413 if (delay_adder > (cas_lat - 1 - hs_offset)) { 414 ie_delay_adder = 0; 415 } else { 416 ie_delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 417 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 418 ie_delay_adder++; 419 } 420 421 if (timing_config->dram_type == DDR3) { 422 mem_delay_ps = 0; 423 } else if (timing_config->dram_type == LPDDR4) { 424 mem_delay_ps = 3600; 425 } else if (timing_config->dram_type == LPDDR3) { 426 mem_delay_ps = 5500; 427 } else { 428 NOTICE("get_pi_tdfi_phy_rdlat:dramtype unsupport\n"); 429 return 0; 430 } 431 round_trip_ps = 1100 + 500 + mem_delay_ps + 500 + 600; 432 delay_adder = round_trip_ps / (1000000 / pdram_timing->mhz); 433 if ((round_trip_ps % (1000000 / pdram_timing->mhz)) != 0) 434 delay_adder++; 435 436 phy_internal_delay = 5 + 2 + 4; 437 lpddr_adder = mem_delay_ps / (1000000 / pdram_timing->mhz); 438 if ((mem_delay_ps % (1000000 / pdram_timing->mhz)) != 0) 439 lpddr_adder++; 440 dfi_adder = 0; 441 phy_internal_delay = phy_internal_delay + 2; 442 rdlat_delay = delay_adder + phy_internal_delay + 443 ie_delay_adder + lpddr_adder + dfi_adder; 444 445 rdlat_delay = rdlat_delay + 2; 446 return rdlat_delay; 447 } 448 449 static uint32_t get_pi_todtoff_min(struct dram_timing_t *pdram_timing, 450 struct timing_related_config *timing_config) 451 { 452 uint32_t tmp, todtoff_min_ps; 453 454 if (timing_config->dram_type == LPDDR3) 455 todtoff_min_ps = 2500; 456 else if (timing_config->dram_type == LPDDR4) 457 todtoff_min_ps = 1500; 458 else 459 todtoff_min_ps = 0; 460 /* todtoff_min */ 461 tmp = todtoff_min_ps / (1000000 / pdram_timing->mhz); 462 if ((todtoff_min_ps % (1000000 / pdram_timing->mhz)) != 0) 463 tmp++; 464 return tmp; 465 } 466 467 static uint32_t get_pi_todtoff_max(struct dram_timing_t *pdram_timing, 468 struct timing_related_config *timing_config) 469 { 470 uint32_t tmp, todtoff_max_ps; 471 472 if ((timing_config->dram_type == LPDDR4) 473 || (timing_config->dram_type == LPDDR3)) 474 todtoff_max_ps = 3500; 475 else 476 todtoff_max_ps = 0; 477 478 /* todtoff_max */ 479 tmp = todtoff_max_ps / (1000000 / pdram_timing->mhz); 480 if ((todtoff_max_ps % (1000000 / pdram_timing->mhz)) != 0) 481 tmp++; 482 return tmp; 483 } 484 485 static void gen_rk3399_ctl_params_f0(struct timing_related_config 486 *timing_config, 487 struct dram_timing_t *pdram_timing) 488 { 489 uint32_t i; 490 uint32_t tmp, tmp1; 491 492 for (i = 0; i < timing_config->ch_cnt; i++) { 493 if (timing_config->dram_type == DDR3) { 494 tmp = ((700000 + 10) * timing_config->freq + 495 999) / 1000; 496 tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) + 497 pdram_timing->tmod + pdram_timing->tzqinit; 498 mmio_write_32(CTL_REG(i, 5), tmp); 499 500 mmio_clrsetbits_32(CTL_REG(i, 22), 0xffff, 501 pdram_timing->tdllk); 502 503 mmio_write_32(CTL_REG(i, 32), 504 (pdram_timing->tmod << 8) | 505 pdram_timing->tmrd); 506 507 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16, 508 (pdram_timing->txsr - 509 pdram_timing->trcd) << 16); 510 } else if (timing_config->dram_type == LPDDR4) { 511 mmio_write_32(CTL_REG(i, 5), pdram_timing->tinit1 + 512 pdram_timing->tinit3); 513 mmio_write_32(CTL_REG(i, 32), 514 (pdram_timing->tmrd << 8) | 515 pdram_timing->tmrd); 516 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16, 517 pdram_timing->txsr << 16); 518 } else { 519 mmio_write_32(CTL_REG(i, 5), pdram_timing->tinit1); 520 mmio_write_32(CTL_REG(i, 7), pdram_timing->tinit4); 521 mmio_write_32(CTL_REG(i, 32), 522 (pdram_timing->tmrd << 8) | 523 pdram_timing->tmrd); 524 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16, 525 pdram_timing->txsr << 16); 526 } 527 mmio_write_32(CTL_REG(i, 6), pdram_timing->tinit3); 528 mmio_write_32(CTL_REG(i, 8), pdram_timing->tinit5); 529 mmio_clrsetbits_32(CTL_REG(i, 23), (0x7f << 16), 530 ((pdram_timing->cl * 2) << 16)); 531 mmio_clrsetbits_32(CTL_REG(i, 23), (0x1f << 24), 532 (pdram_timing->cwl << 24)); 533 mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f, pdram_timing->al); 534 mmio_clrsetbits_32(CTL_REG(i, 26), 0xffffu << 16, 535 (pdram_timing->trc << 24) | 536 (pdram_timing->trrd << 16)); 537 mmio_write_32(CTL_REG(i, 27), 538 (pdram_timing->tfaw << 24) | 539 (pdram_timing->trppb << 16) | 540 (pdram_timing->twtr << 8) | 541 pdram_timing->tras_min); 542 543 mmio_clrsetbits_32(CTL_REG(i, 31), 0xffu << 24, 544 max(4, pdram_timing->trtp) << 24); 545 mmio_write_32(CTL_REG(i, 33), (pdram_timing->tcke << 24) | 546 pdram_timing->tras_max); 547 mmio_clrsetbits_32(CTL_REG(i, 34), 0xff, 548 max(1, pdram_timing->tckesr)); 549 mmio_clrsetbits_32(CTL_REG(i, 39), 550 (0x3f << 16) | (0xff << 8), 551 (pdram_timing->twr << 16) | 552 (pdram_timing->trcd << 8)); 553 mmio_clrsetbits_32(CTL_REG(i, 42), 0x1f << 16, 554 pdram_timing->tmrz << 16); 555 tmp = pdram_timing->tdal ? pdram_timing->tdal : 556 (pdram_timing->twr + pdram_timing->trp); 557 mmio_clrsetbits_32(CTL_REG(i, 44), 0xff, tmp); 558 mmio_clrsetbits_32(CTL_REG(i, 45), 0xff, pdram_timing->trp); 559 mmio_write_32(CTL_REG(i, 48), 560 ((pdram_timing->trefi - 8) << 16) | 561 pdram_timing->trfc); 562 mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff, pdram_timing->txp); 563 mmio_clrsetbits_32(CTL_REG(i, 53), 0xffffu << 16, 564 pdram_timing->txpdll << 16); 565 mmio_clrsetbits_32(CTL_REG(i, 55), 0xf << 24, 566 pdram_timing->tcscke << 24); 567 mmio_clrsetbits_32(CTL_REG(i, 55), 0xff, pdram_timing->tmrri); 568 mmio_write_32(CTL_REG(i, 56), 569 (pdram_timing->tzqcke << 24) | 570 (pdram_timing->tmrwckel << 16) | 571 (pdram_timing->tckehcs << 8) | 572 pdram_timing->tckelcs); 573 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff, pdram_timing->txsnr); 574 mmio_clrsetbits_32(CTL_REG(i, 62), 0xffffu << 16, 575 (pdram_timing->tckehcmd << 24) | 576 (pdram_timing->tckelcmd << 16)); 577 mmio_write_32(CTL_REG(i, 63), 578 (pdram_timing->tckelpd << 24) | 579 (pdram_timing->tescke << 16) | 580 (pdram_timing->tsr << 8) | 581 pdram_timing->tckckel); 582 mmio_clrsetbits_32(CTL_REG(i, 64), 0xfff, 583 (pdram_timing->tcmdcke << 8) | 584 pdram_timing->tcsckeh); 585 mmio_clrsetbits_32(CTL_REG(i, 92), 0xffff << 8, 586 (pdram_timing->tcksrx << 16) | 587 (pdram_timing->tcksre << 8)); 588 mmio_clrsetbits_32(CTL_REG(i, 108), 0x1 << 24, 589 (timing_config->dllbp << 24)); 590 mmio_clrsetbits_32(CTL_REG(i, 122), 0x3ff << 16, 591 (pdram_timing->tvrcg_enable << 16)); 592 mmio_write_32(CTL_REG(i, 123), (pdram_timing->tfc_long << 16) | 593 pdram_timing->tvrcg_disable); 594 mmio_write_32(CTL_REG(i, 124), 595 (pdram_timing->tvref_long << 16) | 596 (pdram_timing->tckfspx << 8) | 597 pdram_timing->tckfspe); 598 mmio_write_32(CTL_REG(i, 133), (pdram_timing->mr[1] << 16) | 599 pdram_timing->mr[0]); 600 mmio_clrsetbits_32(CTL_REG(i, 134), 0xffff, 601 pdram_timing->mr[2]); 602 mmio_clrsetbits_32(CTL_REG(i, 138), 0xffff, 603 pdram_timing->mr[3]); 604 mmio_clrsetbits_32(CTL_REG(i, 139), 0xffu << 24, 605 pdram_timing->mr11 << 24); 606 mmio_write_32(CTL_REG(i, 147), 607 (pdram_timing->mr[1] << 16) | 608 pdram_timing->mr[0]); 609 mmio_clrsetbits_32(CTL_REG(i, 148), 0xffff, 610 pdram_timing->mr[2]); 611 mmio_clrsetbits_32(CTL_REG(i, 152), 0xffff, 612 pdram_timing->mr[3]); 613 mmio_clrsetbits_32(CTL_REG(i, 153), 0xffu << 24, 614 pdram_timing->mr11 << 24); 615 if (timing_config->dram_type == LPDDR4) { 616 mmio_clrsetbits_32(CTL_REG(i, 140), 0xffffu << 16, 617 pdram_timing->mr12 << 16); 618 mmio_clrsetbits_32(CTL_REG(i, 142), 0xffffu << 16, 619 pdram_timing->mr14 << 16); 620 mmio_clrsetbits_32(CTL_REG(i, 145), 0xffffu << 16, 621 pdram_timing->mr22 << 16); 622 mmio_clrsetbits_32(CTL_REG(i, 154), 0xffffu << 16, 623 pdram_timing->mr12 << 16); 624 mmio_clrsetbits_32(CTL_REG(i, 156), 0xffffu << 16, 625 pdram_timing->mr14 << 16); 626 mmio_clrsetbits_32(CTL_REG(i, 159), 0xffffu << 16, 627 pdram_timing->mr22 << 16); 628 } 629 mmio_clrsetbits_32(CTL_REG(i, 179), 0xfff << 8, 630 pdram_timing->tzqinit << 8); 631 mmio_write_32(CTL_REG(i, 180), (pdram_timing->tzqcs << 16) | 632 (pdram_timing->tzqinit / 2)); 633 mmio_write_32(CTL_REG(i, 181), (pdram_timing->tzqlat << 16) | 634 pdram_timing->tzqcal); 635 mmio_clrsetbits_32(CTL_REG(i, 212), 0xff << 8, 636 pdram_timing->todton << 8); 637 638 if (timing_config->odt) { 639 mmio_setbits_32(CTL_REG(i, 213), 1 << 16); 640 if (timing_config->freq < 400) 641 tmp = 4 << 24; 642 else 643 tmp = 8 << 24; 644 } else { 645 mmio_clrbits_32(CTL_REG(i, 213), 1 << 16); 646 tmp = 2 << 24; 647 } 648 649 mmio_clrsetbits_32(CTL_REG(i, 216), 0x1f << 24, tmp); 650 mmio_clrsetbits_32(CTL_REG(i, 221), (0x3 << 16) | (0xf << 8), 651 (pdram_timing->tdqsck << 16) | 652 (pdram_timing->tdqsck_max << 8)); 653 tmp = 654 (get_wrlat_adj(timing_config->dram_type, pdram_timing->cwl) 655 << 8) | get_rdlat_adj(timing_config->dram_type, 656 pdram_timing->cl); 657 mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff, tmp); 658 mmio_clrsetbits_32(CTL_REG(i, 82), 0xffffu << 16, 659 (4 * pdram_timing->trefi) << 16); 660 661 mmio_clrsetbits_32(CTL_REG(i, 83), 0xffff, 662 (2 * pdram_timing->trefi) & 0xffff); 663 664 if ((timing_config->dram_type == LPDDR3) || 665 (timing_config->dram_type == LPDDR4)) { 666 tmp = get_pi_wrlat(pdram_timing, timing_config); 667 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 668 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 669 } else { 670 tmp = 0; 671 } 672 mmio_clrsetbits_32(CTL_REG(i, 214), 0x3f << 16, 673 (tmp & 0x3f) << 16); 674 675 if ((timing_config->dram_type == LPDDR3) || 676 (timing_config->dram_type == LPDDR4)) { 677 /* min_rl_preamble = cl+TDQSCK_MIN -1 */ 678 tmp = pdram_timing->cl + 679 get_pi_todtoff_min(pdram_timing, timing_config) - 1; 680 /* todtoff_max */ 681 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 682 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 683 } else { 684 tmp = pdram_timing->cl - pdram_timing->cwl; 685 } 686 mmio_clrsetbits_32(CTL_REG(i, 215), 0x3f << 8, 687 (tmp & 0x3f) << 8); 688 689 mmio_clrsetbits_32(CTL_REG(i, 275), 0xff << 16, 690 (get_pi_tdfi_phy_rdlat(pdram_timing, 691 timing_config) & 692 0xff) << 16); 693 694 mmio_clrsetbits_32(CTL_REG(i, 277), 0xffff, 695 (2 * pdram_timing->trefi) & 0xffff); 696 697 mmio_clrsetbits_32(CTL_REG(i, 282), 0xffff, 698 (2 * pdram_timing->trefi) & 0xffff); 699 700 mmio_write_32(CTL_REG(i, 283), 20 * pdram_timing->trefi); 701 702 /* CTL_308 TDFI_CALVL_CAPTURE_F0:RW:16:10 */ 703 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 704 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 705 tmp1++; 706 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 707 mmio_clrsetbits_32(CTL_REG(i, 308), 0x3ff << 16, tmp << 16); 708 709 /* CTL_308 TDFI_CALVL_CC_F0:RW:0:10 */ 710 tmp = tmp + 18; 711 mmio_clrsetbits_32(CTL_REG(i, 308), 0x3ff, tmp); 712 713 /* CTL_314 TDFI_WRCSLAT_F0:RW:8:8 */ 714 tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config); 715 if (timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) { 716 if (tmp1 == 0) 717 tmp = 0; 718 else if (tmp1 < 5) 719 tmp = tmp1 - 1; 720 else 721 tmp = tmp1 - 5; 722 } else { 723 tmp = tmp1 - 2; 724 } 725 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 8, tmp << 8); 726 727 /* CTL_314 TDFI_RDCSLAT_F0:RW:0:8 */ 728 if ((timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) && 729 (pdram_timing->cl >= 5)) 730 tmp = pdram_timing->cl - 5; 731 else 732 tmp = pdram_timing->cl - 2; 733 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff, tmp); 734 } 735 } 736 737 static void gen_rk3399_ctl_params_f1(struct timing_related_config 738 *timing_config, 739 struct dram_timing_t *pdram_timing) 740 { 741 uint32_t i; 742 uint32_t tmp, tmp1; 743 744 for (i = 0; i < timing_config->ch_cnt; i++) { 745 if (timing_config->dram_type == DDR3) { 746 tmp = 747 ((700000 + 10) * timing_config->freq + 999) / 1000; 748 tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) + 749 pdram_timing->tmod + pdram_timing->tzqinit; 750 mmio_write_32(CTL_REG(i, 9), tmp); 751 mmio_clrsetbits_32(CTL_REG(i, 22), 0xffffu << 16, 752 pdram_timing->tdllk << 16); 753 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, 754 (pdram_timing->tmod << 24) | 755 (pdram_timing->tmrd << 16) | 756 (pdram_timing->trtp << 8)); 757 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffffu << 16, 758 (pdram_timing->txsr - 759 pdram_timing->trcd) << 16); 760 } else if (timing_config->dram_type == LPDDR4) { 761 mmio_write_32(CTL_REG(i, 9), pdram_timing->tinit1 + 762 pdram_timing->tinit3); 763 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, 764 (pdram_timing->tmrd << 24) | 765 (pdram_timing->tmrd << 16) | 766 (pdram_timing->trtp << 8)); 767 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffffu << 16, 768 pdram_timing->txsr << 16); 769 } else { 770 mmio_write_32(CTL_REG(i, 9), pdram_timing->tinit1); 771 mmio_write_32(CTL_REG(i, 11), pdram_timing->tinit4); 772 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, 773 (pdram_timing->tmrd << 24) | 774 (pdram_timing->tmrd << 16) | 775 (pdram_timing->trtp << 8)); 776 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffffu << 16, 777 pdram_timing->txsr << 16); 778 } 779 mmio_write_32(CTL_REG(i, 10), pdram_timing->tinit3); 780 mmio_write_32(CTL_REG(i, 12), pdram_timing->tinit5); 781 mmio_clrsetbits_32(CTL_REG(i, 24), (0x7f << 8), 782 ((pdram_timing->cl * 2) << 8)); 783 mmio_clrsetbits_32(CTL_REG(i, 24), (0x1f << 16), 784 (pdram_timing->cwl << 16)); 785 mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f << 24, 786 pdram_timing->al << 24); 787 mmio_clrsetbits_32(CTL_REG(i, 28), 0xffffff00, 788 (pdram_timing->tras_min << 24) | 789 (pdram_timing->trc << 16) | 790 (pdram_timing->trrd << 8)); 791 mmio_clrsetbits_32(CTL_REG(i, 29), 0xffffff, 792 (pdram_timing->tfaw << 16) | 793 (pdram_timing->trppb << 8) | 794 pdram_timing->twtr); 795 mmio_write_32(CTL_REG(i, 35), (pdram_timing->tcke << 24) | 796 pdram_timing->tras_max); 797 mmio_clrsetbits_32(CTL_REG(i, 36), 0xff, 798 max(1, pdram_timing->tckesr)); 799 mmio_clrsetbits_32(CTL_REG(i, 39), (0xffu << 24), 800 (pdram_timing->trcd << 24)); 801 mmio_clrsetbits_32(CTL_REG(i, 40), 0x3f, pdram_timing->twr); 802 mmio_clrsetbits_32(CTL_REG(i, 42), 0x1f << 24, 803 pdram_timing->tmrz << 24); 804 tmp = pdram_timing->tdal ? pdram_timing->tdal : 805 (pdram_timing->twr + pdram_timing->trp); 806 mmio_clrsetbits_32(CTL_REG(i, 44), 0xff << 8, tmp << 8); 807 mmio_clrsetbits_32(CTL_REG(i, 45), 0xff << 8, 808 pdram_timing->trp << 8); 809 mmio_write_32(CTL_REG(i, 49), 810 ((pdram_timing->trefi - 8) << 16) | 811 pdram_timing->trfc); 812 mmio_clrsetbits_32(CTL_REG(i, 52), 0xffffu << 16, 813 pdram_timing->txp << 16); 814 mmio_clrsetbits_32(CTL_REG(i, 54), 0xffff, 815 pdram_timing->txpdll); 816 mmio_clrsetbits_32(CTL_REG(i, 55), 0xff << 8, 817 pdram_timing->tmrri << 8); 818 mmio_write_32(CTL_REG(i, 57), (pdram_timing->tmrwckel << 24) | 819 (pdram_timing->tckehcs << 16) | 820 (pdram_timing->tckelcs << 8) | 821 pdram_timing->tcscke); 822 mmio_clrsetbits_32(CTL_REG(i, 58), 0xf, pdram_timing->tzqcke); 823 mmio_clrsetbits_32(CTL_REG(i, 61), 0xffff, pdram_timing->txsnr); 824 mmio_clrsetbits_32(CTL_REG(i, 64), 0xffffu << 16, 825 (pdram_timing->tckehcmd << 24) | 826 (pdram_timing->tckelcmd << 16)); 827 mmio_write_32(CTL_REG(i, 65), (pdram_timing->tckelpd << 24) | 828 (pdram_timing->tescke << 16) | 829 (pdram_timing->tsr << 8) | 830 pdram_timing->tckckel); 831 mmio_clrsetbits_32(CTL_REG(i, 66), 0xfff, 832 (pdram_timing->tcmdcke << 8) | 833 pdram_timing->tcsckeh); 834 mmio_clrsetbits_32(CTL_REG(i, 92), (0xffu << 24), 835 (pdram_timing->tcksre << 24)); 836 mmio_clrsetbits_32(CTL_REG(i, 93), 0xff, 837 pdram_timing->tcksrx); 838 mmio_clrsetbits_32(CTL_REG(i, 108), (0x1 << 25), 839 (timing_config->dllbp << 25)); 840 mmio_write_32(CTL_REG(i, 125), 841 (pdram_timing->tvrcg_disable << 16) | 842 pdram_timing->tvrcg_enable); 843 mmio_write_32(CTL_REG(i, 126), (pdram_timing->tckfspx << 24) | 844 (pdram_timing->tckfspe << 16) | 845 pdram_timing->tfc_long); 846 mmio_clrsetbits_32(CTL_REG(i, 127), 0xffff, 847 pdram_timing->tvref_long); 848 mmio_clrsetbits_32(CTL_REG(i, 134), 0xffffu << 16, 849 pdram_timing->mr[0] << 16); 850 mmio_write_32(CTL_REG(i, 135), (pdram_timing->mr[2] << 16) | 851 pdram_timing->mr[1]); 852 mmio_clrsetbits_32(CTL_REG(i, 138), 0xffffu << 16, 853 pdram_timing->mr[3] << 16); 854 mmio_clrsetbits_32(CTL_REG(i, 140), 0xff, pdram_timing->mr11); 855 mmio_clrsetbits_32(CTL_REG(i, 148), 0xffffu << 16, 856 pdram_timing->mr[0] << 16); 857 mmio_write_32(CTL_REG(i, 149), (pdram_timing->mr[2] << 16) | 858 pdram_timing->mr[1]); 859 mmio_clrsetbits_32(CTL_REG(i, 152), 0xffffu << 16, 860 pdram_timing->mr[3] << 16); 861 mmio_clrsetbits_32(CTL_REG(i, 154), 0xff, pdram_timing->mr11); 862 if (timing_config->dram_type == LPDDR4) { 863 mmio_clrsetbits_32(CTL_REG(i, 141), 0xffff, 864 pdram_timing->mr12); 865 mmio_clrsetbits_32(CTL_REG(i, 143), 0xffff, 866 pdram_timing->mr14); 867 mmio_clrsetbits_32(CTL_REG(i, 146), 0xffff, 868 pdram_timing->mr22); 869 mmio_clrsetbits_32(CTL_REG(i, 155), 0xffff, 870 pdram_timing->mr12); 871 mmio_clrsetbits_32(CTL_REG(i, 157), 0xffff, 872 pdram_timing->mr14); 873 mmio_clrsetbits_32(CTL_REG(i, 160), 0xffff, 874 pdram_timing->mr22); 875 } 876 mmio_write_32(CTL_REG(i, 182), 877 ((pdram_timing->tzqinit / 2) << 16) | 878 pdram_timing->tzqinit); 879 mmio_write_32(CTL_REG(i, 183), (pdram_timing->tzqcal << 16) | 880 pdram_timing->tzqcs); 881 mmio_clrsetbits_32(CTL_REG(i, 184), 0x3f, pdram_timing->tzqlat); 882 mmio_clrsetbits_32(CTL_REG(i, 188), 0xfff, 883 pdram_timing->tzqreset); 884 mmio_clrsetbits_32(CTL_REG(i, 212), 0xff << 16, 885 pdram_timing->todton << 16); 886 887 if (timing_config->odt) { 888 mmio_setbits_32(CTL_REG(i, 213), (1 << 24)); 889 if (timing_config->freq < 400) 890 tmp = 4 << 24; 891 else 892 tmp = 8 << 24; 893 } else { 894 mmio_clrbits_32(CTL_REG(i, 213), (1 << 24)); 895 tmp = 2 << 24; 896 } 897 mmio_clrsetbits_32(CTL_REG(i, 217), 0x1f << 24, tmp); 898 mmio_clrsetbits_32(CTL_REG(i, 221), 0xf << 24, 899 (pdram_timing->tdqsck_max << 24)); 900 mmio_clrsetbits_32(CTL_REG(i, 222), 0x3, pdram_timing->tdqsck); 901 mmio_clrsetbits_32(CTL_REG(i, 291), 0xffff, 902 (get_wrlat_adj(timing_config->dram_type, 903 pdram_timing->cwl) << 8) | 904 get_rdlat_adj(timing_config->dram_type, 905 pdram_timing->cl)); 906 907 mmio_clrsetbits_32(CTL_REG(i, 84), 0xffff, 908 (4 * pdram_timing->trefi) & 0xffff); 909 910 mmio_clrsetbits_32(CTL_REG(i, 84), 0xffffu << 16, 911 ((2 * pdram_timing->trefi) & 0xffff) << 16); 912 913 if ((timing_config->dram_type == LPDDR3) || 914 (timing_config->dram_type == LPDDR4)) { 915 tmp = get_pi_wrlat(pdram_timing, timing_config); 916 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 917 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 918 } else { 919 tmp = 0; 920 } 921 mmio_clrsetbits_32(CTL_REG(i, 214), 0x3f << 24, 922 (tmp & 0x3f) << 24); 923 924 if ((timing_config->dram_type == LPDDR3) || 925 (timing_config->dram_type == LPDDR4)) { 926 /* min_rl_preamble = cl + TDQSCK_MIN - 1 */ 927 tmp = pdram_timing->cl + 928 get_pi_todtoff_min(pdram_timing, timing_config); 929 tmp--; 930 /* todtoff_max */ 931 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 932 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 933 } else { 934 tmp = pdram_timing->cl - pdram_timing->cwl; 935 } 936 mmio_clrsetbits_32(CTL_REG(i, 215), 0x3f << 16, 937 (tmp & 0x3f) << 16); 938 939 mmio_clrsetbits_32(CTL_REG(i, 275), 0xffu << 24, 940 (get_pi_tdfi_phy_rdlat(pdram_timing, 941 timing_config) & 942 0xff) << 24); 943 944 mmio_clrsetbits_32(CTL_REG(i, 284), 0xffffu << 16, 945 ((2 * pdram_timing->trefi) & 0xffff) << 16); 946 947 mmio_clrsetbits_32(CTL_REG(i, 289), 0xffff, 948 (2 * pdram_timing->trefi) & 0xffff); 949 950 mmio_write_32(CTL_REG(i, 290), 20 * pdram_timing->trefi); 951 952 /* CTL_309 TDFI_CALVL_CAPTURE_F1:RW:16:10 */ 953 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 954 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 955 tmp1++; 956 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 957 mmio_clrsetbits_32(CTL_REG(i, 309), 0x3ff << 16, tmp << 16); 958 959 /* CTL_309 TDFI_CALVL_CC_F1:RW:0:10 */ 960 tmp = tmp + 18; 961 mmio_clrsetbits_32(CTL_REG(i, 309), 0x3ff, tmp); 962 963 /* CTL_314 TDFI_WRCSLAT_F1:RW:24:8 */ 964 tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config); 965 if (timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) { 966 if (tmp1 == 0) 967 tmp = 0; 968 else if (tmp1 < 5) 969 tmp = tmp1 - 1; 970 else 971 tmp = tmp1 - 5; 972 } else { 973 tmp = tmp1 - 2; 974 } 975 976 mmio_clrsetbits_32(CTL_REG(i, 314), 0xffu << 24, tmp << 24); 977 978 /* CTL_314 TDFI_RDCSLAT_F1:RW:16:8 */ 979 if ((timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) && 980 (pdram_timing->cl >= 5)) 981 tmp = pdram_timing->cl - 5; 982 else 983 tmp = pdram_timing->cl - 2; 984 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 16, tmp << 16); 985 } 986 } 987 988 static void gen_rk3399_enable_training(uint32_t ch_cnt, uint32_t nmhz) 989 { 990 uint32_t i, tmp; 991 992 if (nmhz <= PHY_DLL_BYPASS_FREQ) 993 tmp = 0; 994 else 995 tmp = 1; 996 997 for (i = 0; i < ch_cnt; i++) { 998 mmio_clrsetbits_32(CTL_REG(i, 305), 1 << 16, tmp << 16); 999 mmio_clrsetbits_32(CTL_REG(i, 71), 1, tmp); 1000 mmio_clrsetbits_32(CTL_REG(i, 70), 1 << 8, 1 << 8); 1001 } 1002 } 1003 1004 static void gen_rk3399_disable_training(uint32_t ch_cnt) 1005 { 1006 uint32_t i; 1007 1008 for (i = 0; i < ch_cnt; i++) { 1009 mmio_clrbits_32(CTL_REG(i, 305), 1 << 16); 1010 mmio_clrbits_32(CTL_REG(i, 71), 1); 1011 mmio_clrbits_32(CTL_REG(i, 70), 1 << 8); 1012 } 1013 } 1014 1015 static void gen_rk3399_ctl_params(struct timing_related_config *timing_config, 1016 struct dram_timing_t *pdram_timing, 1017 uint32_t fn) 1018 { 1019 if (fn == 0) 1020 gen_rk3399_ctl_params_f0(timing_config, pdram_timing); 1021 else 1022 gen_rk3399_ctl_params_f1(timing_config, pdram_timing); 1023 } 1024 1025 static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config, 1026 struct dram_timing_t *pdram_timing) 1027 { 1028 uint32_t tmp, tmp1, tmp2; 1029 uint32_t i; 1030 1031 for (i = 0; i < timing_config->ch_cnt; i++) { 1032 /* PI_02 PI_TDFI_PHYMSTR_MAX_F0:RW:0:32 */ 1033 tmp = 4 * pdram_timing->trefi; 1034 mmio_write_32(PI_REG(i, 2), tmp); 1035 /* PI_03 PI_TDFI_PHYMSTR_RESP_F0:RW:0:16 */ 1036 tmp = 2 * pdram_timing->trefi; 1037 mmio_clrsetbits_32(PI_REG(i, 3), 0xffff, tmp); 1038 /* PI_07 PI_TDFI_PHYUPD_RESP_F0:RW:16:16 */ 1039 mmio_clrsetbits_32(PI_REG(i, 7), 0xffffu << 16, tmp << 16); 1040 1041 /* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F0:RW:0:8 */ 1042 if (timing_config->dram_type == LPDDR4) 1043 tmp = 2; 1044 else 1045 tmp = 0; 1046 tmp = (pdram_timing->bl / 2) + 4 + 1047 (get_pi_rdlat_adj(pdram_timing) - 2) + tmp + 1048 get_pi_tdfi_phy_rdlat(pdram_timing, timing_config); 1049 mmio_clrsetbits_32(PI_REG(i, 42), 0xff, tmp); 1050 /* PI_43 PI_WRLAT_F0:RW:0:5 */ 1051 if (timing_config->dram_type == LPDDR3) { 1052 tmp = get_pi_wrlat(pdram_timing, timing_config); 1053 mmio_clrsetbits_32(PI_REG(i, 43), 0x1f, tmp); 1054 } 1055 /* PI_43 PI_ADDITIVE_LAT_F0:RW:8:6 */ 1056 mmio_clrsetbits_32(PI_REG(i, 43), 0x3f << 8, 1057 PI_ADD_LATENCY << 8); 1058 1059 /* PI_43 PI_CASLAT_LIN_F0:RW:16:7 */ 1060 mmio_clrsetbits_32(PI_REG(i, 43), 0x7f << 16, 1061 (pdram_timing->cl * 2) << 16); 1062 /* PI_46 PI_TREF_F0:RW:16:16 */ 1063 mmio_clrsetbits_32(PI_REG(i, 46), 0xffffu << 16, 1064 pdram_timing->trefi << 16); 1065 /* PI_46 PI_TRFC_F0:RW:0:10 */ 1066 mmio_clrsetbits_32(PI_REG(i, 46), 0x3ff, pdram_timing->trfc); 1067 /* PI_66 PI_TODTL_2CMD_F0:RW:24:8 */ 1068 if (timing_config->dram_type == LPDDR3) { 1069 tmp = get_pi_todtoff_max(pdram_timing, timing_config); 1070 mmio_clrsetbits_32(PI_REG(i, 66), 0xffu << 24, 1071 tmp << 24); 1072 } 1073 /* PI_72 PI_WR_TO_ODTH_F0:RW:16:6 */ 1074 if ((timing_config->dram_type == LPDDR3) || 1075 (timing_config->dram_type == LPDDR4)) { 1076 tmp1 = get_pi_wrlat(pdram_timing, timing_config); 1077 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1078 if (tmp1 > tmp2) 1079 tmp = tmp1 - tmp2; 1080 else 1081 tmp = 0; 1082 } else if (timing_config->dram_type == DDR3) { 1083 tmp = 0; 1084 } 1085 mmio_clrsetbits_32(PI_REG(i, 72), 0x3f << 16, tmp << 16); 1086 /* PI_73 PI_RD_TO_ODTH_F0:RW:8:6 */ 1087 if ((timing_config->dram_type == LPDDR3) || 1088 (timing_config->dram_type == LPDDR4)) { 1089 /* min_rl_preamble = cl + TDQSCK_MIN - 1 */ 1090 tmp1 = pdram_timing->cl; 1091 tmp1 += get_pi_todtoff_min(pdram_timing, timing_config); 1092 tmp1--; 1093 /* todtoff_max */ 1094 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1095 if (tmp1 > tmp2) 1096 tmp = tmp1 - tmp2; 1097 else 1098 tmp = 0; 1099 } else if (timing_config->dram_type == DDR3) { 1100 tmp = pdram_timing->cl - pdram_timing->cwl; 1101 } 1102 mmio_clrsetbits_32(PI_REG(i, 73), 0x3f << 8, tmp << 8); 1103 /* PI_89 PI_RDLAT_ADJ_F0:RW:16:8 */ 1104 tmp = get_pi_rdlat_adj(pdram_timing); 1105 mmio_clrsetbits_32(PI_REG(i, 89), 0xff << 16, tmp << 16); 1106 /* PI_90 PI_WRLAT_ADJ_F0:RW:16:8 */ 1107 tmp = get_pi_wrlat_adj(pdram_timing, timing_config); 1108 mmio_clrsetbits_32(PI_REG(i, 90), 0xff << 16, tmp << 16); 1109 /* PI_91 PI_TDFI_WRCSLAT_F0:RW:16:8 */ 1110 tmp1 = tmp; 1111 if (tmp1 == 0) 1112 tmp = 0; 1113 else if (tmp1 < 5) 1114 tmp = tmp1 - 1; 1115 else 1116 tmp = tmp1 - 5; 1117 mmio_clrsetbits_32(PI_REG(i, 91), 0xff << 16, tmp << 16); 1118 /* PI_95 PI_TDFI_CALVL_CAPTURE_F0:RW:16:10 */ 1119 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 1120 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 1121 tmp1++; 1122 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 1123 mmio_clrsetbits_32(PI_REG(i, 95), 0x3ff << 16, tmp << 16); 1124 /* PI_95 PI_TDFI_CALVL_CC_F0:RW:0:10 */ 1125 mmio_clrsetbits_32(PI_REG(i, 95), 0x3ff, tmp + 18); 1126 /* PI_102 PI_TMRZ_F0:RW:8:5 */ 1127 mmio_clrsetbits_32(PI_REG(i, 102), 0x1f << 8, 1128 pdram_timing->tmrz << 8); 1129 /* PI_111 PI_TDFI_CALVL_STROBE_F0:RW:8:4 */ 1130 tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz); 1131 if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0) 1132 tmp1++; 1133 /* pi_tdfi_calvl_strobe=tds_train+5 */ 1134 tmp = tmp1 + 5; 1135 mmio_clrsetbits_32(PI_REG(i, 111), 0xf << 8, tmp << 8); 1136 /* PI_116 PI_TCKEHDQS_F0:RW:16:6 */ 1137 tmp = 10000 / (1000000 / pdram_timing->mhz); 1138 if ((10000 % (1000000 / pdram_timing->mhz)) != 0) 1139 tmp++; 1140 if (pdram_timing->mhz <= 100) 1141 tmp = tmp + 1; 1142 else 1143 tmp = tmp + 8; 1144 mmio_clrsetbits_32(PI_REG(i, 116), 0x3f << 16, tmp << 16); 1145 /* PI_125 PI_MR1_DATA_F0_0:RW+:8:16 */ 1146 mmio_clrsetbits_32(PI_REG(i, 125), 0xffff << 8, 1147 pdram_timing->mr[1] << 8); 1148 /* PI_133 PI_MR1_DATA_F0_1:RW+:0:16 */ 1149 mmio_clrsetbits_32(PI_REG(i, 133), 0xffff, pdram_timing->mr[1]); 1150 /* PI_140 PI_MR1_DATA_F0_2:RW+:16:16 */ 1151 mmio_clrsetbits_32(PI_REG(i, 140), 0xffffu << 16, 1152 pdram_timing->mr[1] << 16); 1153 /* PI_148 PI_MR1_DATA_F0_3:RW+:0:16 */ 1154 mmio_clrsetbits_32(PI_REG(i, 148), 0xffff, pdram_timing->mr[1]); 1155 /* PI_126 PI_MR2_DATA_F0_0:RW+:0:16 */ 1156 mmio_clrsetbits_32(PI_REG(i, 126), 0xffff, pdram_timing->mr[2]); 1157 /* PI_133 PI_MR2_DATA_F0_1:RW+:16:16 */ 1158 mmio_clrsetbits_32(PI_REG(i, 133), 0xffffu << 16, 1159 pdram_timing->mr[2] << 16); 1160 /* PI_141 PI_MR2_DATA_F0_2:RW+:0:16 */ 1161 mmio_clrsetbits_32(PI_REG(i, 141), 0xffff, pdram_timing->mr[2]); 1162 /* PI_148 PI_MR2_DATA_F0_3:RW+:16:16 */ 1163 mmio_clrsetbits_32(PI_REG(i, 148), 0xffffu << 16, 1164 pdram_timing->mr[2] << 16); 1165 /* PI_156 PI_TFC_F0:RW:0:10 */ 1166 mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff, 1167 pdram_timing->tfc_long); 1168 /* PI_158 PI_TWR_F0:RW:24:6 */ 1169 mmio_clrsetbits_32(PI_REG(i, 158), 0x3f << 24, 1170 pdram_timing->twr << 24); 1171 /* PI_158 PI_TWTR_F0:RW:16:6 */ 1172 mmio_clrsetbits_32(PI_REG(i, 158), 0x3f << 16, 1173 pdram_timing->twtr << 16); 1174 /* PI_158 PI_TRCD_F0:RW:8:8 */ 1175 mmio_clrsetbits_32(PI_REG(i, 158), 0xff << 8, 1176 pdram_timing->trcd << 8); 1177 /* PI_158 PI_TRP_F0:RW:0:8 */ 1178 mmio_clrsetbits_32(PI_REG(i, 158), 0xff, pdram_timing->trp); 1179 /* PI_157 PI_TRTP_F0:RW:24:8 */ 1180 mmio_clrsetbits_32(PI_REG(i, 157), 0xffu << 24, 1181 pdram_timing->trtp << 24); 1182 /* PI_159 PI_TRAS_MIN_F0:RW:24:8 */ 1183 mmio_clrsetbits_32(PI_REG(i, 159), 0xffu << 24, 1184 pdram_timing->tras_min << 24); 1185 /* PI_159 PI_TRAS_MAX_F0:RW:0:17 */ 1186 tmp = pdram_timing->tras_max * 99 / 100; 1187 mmio_clrsetbits_32(PI_REG(i, 159), 0x1ffff, tmp); 1188 /* PI_160 PI_TMRD_F0:RW:16:6 */ 1189 mmio_clrsetbits_32(PI_REG(i, 160), 0x3f << 16, 1190 pdram_timing->tmrd << 16); 1191 /*PI_160 PI_TDQSCK_MAX_F0:RW:0:4 */ 1192 mmio_clrsetbits_32(PI_REG(i, 160), 0xf, 1193 pdram_timing->tdqsck_max); 1194 /* PI_187 PI_TDFI_CTRLUPD_MAX_F0:RW:8:16 */ 1195 mmio_clrsetbits_32(PI_REG(i, 187), 0xffff << 8, 1196 (2 * pdram_timing->trefi) << 8); 1197 /* PI_188 PI_TDFI_CTRLUPD_INTERVAL_F0:RW:0:32 */ 1198 mmio_clrsetbits_32(PI_REG(i, 188), 0xffffffff, 1199 20 * pdram_timing->trefi); 1200 } 1201 } 1202 1203 static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config, 1204 struct dram_timing_t *pdram_timing) 1205 { 1206 uint32_t tmp, tmp1, tmp2; 1207 uint32_t i; 1208 1209 for (i = 0; i < timing_config->ch_cnt; i++) { 1210 /* PI_04 PI_TDFI_PHYMSTR_MAX_F1:RW:0:32 */ 1211 tmp = 4 * pdram_timing->trefi; 1212 mmio_write_32(PI_REG(i, 4), tmp); 1213 /* PI_05 PI_TDFI_PHYMSTR_RESP_F1:RW:0:16 */ 1214 tmp = 2 * pdram_timing->trefi; 1215 mmio_clrsetbits_32(PI_REG(i, 5), 0xffff, tmp); 1216 /* PI_12 PI_TDFI_PHYUPD_RESP_F1:RW:0:16 */ 1217 mmio_clrsetbits_32(PI_REG(i, 12), 0xffff, tmp); 1218 1219 /* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F1:RW:8:8 */ 1220 if (timing_config->dram_type == LPDDR4) 1221 tmp = 2; 1222 else 1223 tmp = 0; 1224 tmp = (pdram_timing->bl / 2) + 4 + 1225 (get_pi_rdlat_adj(pdram_timing) - 2) + tmp + 1226 get_pi_tdfi_phy_rdlat(pdram_timing, timing_config); 1227 mmio_clrsetbits_32(PI_REG(i, 42), 0xff << 8, tmp << 8); 1228 /* PI_43 PI_WRLAT_F1:RW:24:5 */ 1229 if (timing_config->dram_type == LPDDR3) { 1230 tmp = get_pi_wrlat(pdram_timing, timing_config); 1231 mmio_clrsetbits_32(PI_REG(i, 43), 0x1f << 24, 1232 tmp << 24); 1233 } 1234 /* PI_44 PI_ADDITIVE_LAT_F1:RW:0:6 */ 1235 mmio_clrsetbits_32(PI_REG(i, 44), 0x3f, PI_ADD_LATENCY); 1236 /* PI_44 PI_CASLAT_LIN_F1:RW:8:7:=0x18 */ 1237 mmio_clrsetbits_32(PI_REG(i, 44), 0x7f << 8, 1238 (pdram_timing->cl * 2) << 8); 1239 /* PI_47 PI_TREF_F1:RW:16:16 */ 1240 mmio_clrsetbits_32(PI_REG(i, 47), 0xffffu << 16, 1241 pdram_timing->trefi << 16); 1242 /* PI_47 PI_TRFC_F1:RW:0:10 */ 1243 mmio_clrsetbits_32(PI_REG(i, 47), 0x3ff, pdram_timing->trfc); 1244 /* PI_67 PI_TODTL_2CMD_F1:RW:8:8 */ 1245 if (timing_config->dram_type == LPDDR3) { 1246 tmp = get_pi_todtoff_max(pdram_timing, timing_config); 1247 mmio_clrsetbits_32(PI_REG(i, 67), 0xff << 8, tmp << 8); 1248 } 1249 /* PI_72 PI_WR_TO_ODTH_F1:RW:24:6 */ 1250 if ((timing_config->dram_type == LPDDR3) || 1251 (timing_config->dram_type == LPDDR4)) { 1252 tmp1 = get_pi_wrlat(pdram_timing, timing_config); 1253 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1254 if (tmp1 > tmp2) 1255 tmp = tmp1 - tmp2; 1256 else 1257 tmp = 0; 1258 } else if (timing_config->dram_type == DDR3) { 1259 tmp = 0; 1260 } 1261 mmio_clrsetbits_32(PI_REG(i, 72), 0x3f << 24, tmp << 24); 1262 /* PI_73 PI_RD_TO_ODTH_F1:RW:16:6 */ 1263 if ((timing_config->dram_type == LPDDR3) || 1264 (timing_config->dram_type == LPDDR4)) { 1265 /* min_rl_preamble = cl + TDQSCK_MIN - 1 */ 1266 tmp1 = pdram_timing->cl + 1267 get_pi_todtoff_min(pdram_timing, timing_config); 1268 tmp1--; 1269 /* todtoff_max */ 1270 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1271 if (tmp1 > tmp2) 1272 tmp = tmp1 - tmp2; 1273 else 1274 tmp = 0; 1275 } else if (timing_config->dram_type == DDR3) 1276 tmp = pdram_timing->cl - pdram_timing->cwl; 1277 1278 mmio_clrsetbits_32(PI_REG(i, 73), 0x3f << 16, tmp << 16); 1279 /*P I_89 PI_RDLAT_ADJ_F1:RW:24:8 */ 1280 tmp = get_pi_rdlat_adj(pdram_timing); 1281 mmio_clrsetbits_32(PI_REG(i, 89), 0xffu << 24, tmp << 24); 1282 /* PI_90 PI_WRLAT_ADJ_F1:RW:24:8 */ 1283 tmp = get_pi_wrlat_adj(pdram_timing, timing_config); 1284 mmio_clrsetbits_32(PI_REG(i, 90), 0xffu << 24, tmp << 24); 1285 /* PI_91 PI_TDFI_WRCSLAT_F1:RW:24:8 */ 1286 tmp1 = tmp; 1287 if (tmp1 == 0) 1288 tmp = 0; 1289 else if (tmp1 < 5) 1290 tmp = tmp1 - 1; 1291 else 1292 tmp = tmp1 - 5; 1293 mmio_clrsetbits_32(PI_REG(i, 91), 0xffu << 24, tmp << 24); 1294 /*PI_96 PI_TDFI_CALVL_CAPTURE_F1:RW:16:10 */ 1295 /* tadr=20ns */ 1296 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 1297 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 1298 tmp1++; 1299 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 1300 mmio_clrsetbits_32(PI_REG(i, 96), 0x3ff << 16, tmp << 16); 1301 /* PI_96 PI_TDFI_CALVL_CC_F1:RW:0:10 */ 1302 tmp = tmp + 18; 1303 mmio_clrsetbits_32(PI_REG(i, 96), 0x3ff, tmp); 1304 /*PI_103 PI_TMRZ_F1:RW:0:5 */ 1305 mmio_clrsetbits_32(PI_REG(i, 103), 0x1f, pdram_timing->tmrz); 1306 /*PI_111 PI_TDFI_CALVL_STROBE_F1:RW:16:4 */ 1307 /* tds_train=ceil(2/ns) */ 1308 tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz); 1309 if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0) 1310 tmp1++; 1311 /* pi_tdfi_calvl_strobe=tds_train+5 */ 1312 tmp = tmp1 + 5; 1313 mmio_clrsetbits_32(PI_REG(i, 111), 0xf << 16, 1314 tmp << 16); 1315 /* PI_116 PI_TCKEHDQS_F1:RW:24:6 */ 1316 tmp = 10000 / (1000000 / pdram_timing->mhz); 1317 if ((10000 % (1000000 / pdram_timing->mhz)) != 0) 1318 tmp++; 1319 if (pdram_timing->mhz <= 100) 1320 tmp = tmp + 1; 1321 else 1322 tmp = tmp + 8; 1323 mmio_clrsetbits_32(PI_REG(i, 116), 0x3f << 24, 1324 tmp << 24); 1325 /* PI_128 PI_MR1_DATA_F1_0:RW+:0:16 */ 1326 mmio_clrsetbits_32(PI_REG(i, 128), 0xffff, pdram_timing->mr[1]); 1327 /* PI_135 PI_MR1_DATA_F1_1:RW+:8:16 */ 1328 mmio_clrsetbits_32(PI_REG(i, 135), 0xffff << 8, 1329 pdram_timing->mr[1] << 8); 1330 /* PI_143 PI_MR1_DATA_F1_2:RW+:0:16 */ 1331 mmio_clrsetbits_32(PI_REG(i, 143), 0xffff, pdram_timing->mr[1]); 1332 /* PI_150 PI_MR1_DATA_F1_3:RW+:8:16 */ 1333 mmio_clrsetbits_32(PI_REG(i, 150), 0xffff << 8, 1334 pdram_timing->mr[1] << 8); 1335 /* PI_128 PI_MR2_DATA_F1_0:RW+:16:16 */ 1336 mmio_clrsetbits_32(PI_REG(i, 128), 0xffffu << 16, 1337 pdram_timing->mr[2] << 16); 1338 /* PI_136 PI_MR2_DATA_F1_1:RW+:0:16 */ 1339 mmio_clrsetbits_32(PI_REG(i, 136), 0xffff, pdram_timing->mr[2]); 1340 /* PI_143 PI_MR2_DATA_F1_2:RW+:16:16 */ 1341 mmio_clrsetbits_32(PI_REG(i, 143), 0xffffu << 16, 1342 pdram_timing->mr[2] << 16); 1343 /* PI_151 PI_MR2_DATA_F1_3:RW+:0:16 */ 1344 mmio_clrsetbits_32(PI_REG(i, 151), 0xffff, pdram_timing->mr[2]); 1345 /* PI_156 PI_TFC_F1:RW:16:10 */ 1346 mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff << 16, 1347 pdram_timing->tfc_long << 16); 1348 /* PI_162 PI_TWR_F1:RW:8:6 */ 1349 mmio_clrsetbits_32(PI_REG(i, 162), 0x3f << 8, 1350 pdram_timing->twr << 8); 1351 /* PI_162 PI_TWTR_F1:RW:0:6 */ 1352 mmio_clrsetbits_32(PI_REG(i, 162), 0x3f, pdram_timing->twtr); 1353 /* PI_161 PI_TRCD_F1:RW:24:8 */ 1354 mmio_clrsetbits_32(PI_REG(i, 161), 0xffu << 24, 1355 pdram_timing->trcd << 24); 1356 /* PI_161 PI_TRP_F1:RW:16:8 */ 1357 mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 16, 1358 pdram_timing->trp << 16); 1359 /* PI_161 PI_TRTP_F1:RW:8:8 */ 1360 mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 8, 1361 pdram_timing->trtp << 8); 1362 /* PI_163 PI_TRAS_MIN_F1:RW:24:8 */ 1363 mmio_clrsetbits_32(PI_REG(i, 163), 0xffu << 24, 1364 pdram_timing->tras_min << 24); 1365 /* PI_163 PI_TRAS_MAX_F1:RW:0:17 */ 1366 mmio_clrsetbits_32(PI_REG(i, 163), 0x1ffff, 1367 pdram_timing->tras_max * 99 / 100); 1368 /* PI_164 PI_TMRD_F1:RW:16:6 */ 1369 mmio_clrsetbits_32(PI_REG(i, 164), 0x3f << 16, 1370 pdram_timing->tmrd << 16); 1371 /* PI_164 PI_TDQSCK_MAX_F1:RW:0:4 */ 1372 mmio_clrsetbits_32(PI_REG(i, 164), 0xf, 1373 pdram_timing->tdqsck_max); 1374 /* PI_189 PI_TDFI_CTRLUPD_MAX_F1:RW:0:16 */ 1375 mmio_clrsetbits_32(PI_REG(i, 189), 0xffff, 1376 2 * pdram_timing->trefi); 1377 /* PI_190 PI_TDFI_CTRLUPD_INTERVAL_F1:RW:0:32 */ 1378 mmio_clrsetbits_32(PI_REG(i, 190), 0xffffffff, 1379 20 * pdram_timing->trefi); 1380 } 1381 } 1382 1383 static void gen_rk3399_pi_params(struct timing_related_config *timing_config, 1384 struct dram_timing_t *pdram_timing, 1385 uint32_t fn) 1386 { 1387 if (fn == 0) 1388 gen_rk3399_pi_params_f0(timing_config, pdram_timing); 1389 else 1390 gen_rk3399_pi_params_f1(timing_config, pdram_timing); 1391 } 1392 1393 static void gen_rk3399_set_odt(uint32_t odt_en) 1394 { 1395 uint32_t drv_odt_val; 1396 uint32_t i; 1397 1398 for (i = 0; i < rk3399_dram_status.timing_config.ch_cnt; i++) { 1399 drv_odt_val = (odt_en | (0 << 1) | (0 << 2)) << 16; 1400 mmio_clrsetbits_32(PHY_REG(i, 5), 0x7 << 16, drv_odt_val); 1401 mmio_clrsetbits_32(PHY_REG(i, 133), 0x7 << 16, drv_odt_val); 1402 mmio_clrsetbits_32(PHY_REG(i, 261), 0x7 << 16, drv_odt_val); 1403 mmio_clrsetbits_32(PHY_REG(i, 389), 0x7 << 16, drv_odt_val); 1404 drv_odt_val = (odt_en | (0 << 1) | (0 << 2)) << 24; 1405 mmio_clrsetbits_32(PHY_REG(i, 6), 0x7 << 24, drv_odt_val); 1406 mmio_clrsetbits_32(PHY_REG(i, 134), 0x7 << 24, drv_odt_val); 1407 mmio_clrsetbits_32(PHY_REG(i, 262), 0x7 << 24, drv_odt_val); 1408 mmio_clrsetbits_32(PHY_REG(i, 390), 0x7 << 24, drv_odt_val); 1409 } 1410 } 1411 1412 static void gen_rk3399_phy_dll_bypass(uint32_t mhz, uint32_t ch, 1413 uint32_t index, uint32_t dram_type) 1414 { 1415 uint32_t sw_master_mode = 0; 1416 uint32_t rddqs_gate_delay, rddqs_latency, total_delay; 1417 uint32_t i; 1418 1419 if (dram_type == DDR3) 1420 total_delay = PI_PAD_DELAY_PS_VALUE; 1421 else if (dram_type == LPDDR3) 1422 total_delay = PI_PAD_DELAY_PS_VALUE + 2500; 1423 else 1424 total_delay = PI_PAD_DELAY_PS_VALUE + 1500; 1425 /* total_delay + 0.55tck */ 1426 total_delay += (55 * 10000)/mhz; 1427 rddqs_latency = total_delay * mhz / 1000000; 1428 total_delay -= rddqs_latency * 1000000 / mhz; 1429 rddqs_gate_delay = total_delay * 0x200 * mhz / 1000000; 1430 if (mhz <= PHY_DLL_BYPASS_FREQ) { 1431 sw_master_mode = 0xc; 1432 mmio_setbits_32(PHY_REG(ch, 514), 1); 1433 mmio_setbits_32(PHY_REG(ch, 642), 1); 1434 mmio_setbits_32(PHY_REG(ch, 770), 1); 1435 1436 /* setting bypass mode slave delay */ 1437 for (i = 0; i < 4; i++) { 1438 /* wr dq delay = -180deg + (0x60 / 4) * 20ps */ 1439 mmio_clrsetbits_32(PHY_REG(ch, 1 + 128 * i), 0x7ff << 8, 1440 0x4a0 << 8); 1441 /* rd dqs/dq delay = (0x60 / 4) * 20ps */ 1442 mmio_clrsetbits_32(PHY_REG(ch, 11 + 128 * i), 0x3ff, 1443 0xa0); 1444 /* rd rddqs_gate delay */ 1445 mmio_clrsetbits_32(PHY_REG(ch, 2 + 128 * i), 0x3ff, 1446 rddqs_gate_delay); 1447 mmio_clrsetbits_32(PHY_REG(ch, 78 + 128 * i), 0xf, 1448 rddqs_latency); 1449 } 1450 for (i = 0; i < 3; i++) 1451 /* adr delay */ 1452 mmio_clrsetbits_32(PHY_REG(ch, 513 + 128 * i), 1453 0x7ff << 16, 0x80 << 16); 1454 1455 if ((mmio_read_32(PHY_REG(ch, 86)) & 0xc00) == 0) { 1456 /* 1457 * old status is normal mode, 1458 * and saving the wrdqs slave delay 1459 */ 1460 for (i = 0; i < 4; i++) { 1461 /* save and clear wr dqs slave delay */ 1462 wrdqs_delay_val[ch][index][i] = 0x3ff & 1463 (mmio_read_32(PHY_REG(ch, 63 + i * 128)) 1464 >> 16); 1465 mmio_clrsetbits_32(PHY_REG(ch, 63 + i * 128), 1466 0x03ff << 16, 0 << 16); 1467 /* 1468 * in normal mode the cmd may delay 1cycle by 1469 * wrlvl and in bypass mode making dqs also 1470 * delay 1cycle. 1471 */ 1472 mmio_clrsetbits_32(PHY_REG(ch, 78 + i * 128), 1473 0x07 << 8, 0x1 << 8); 1474 } 1475 } 1476 } else if (mmio_read_32(PHY_REG(ch, 86)) & 0xc00) { 1477 /* old status is bypass mode and restore wrlvl resume */ 1478 for (i = 0; i < 4; i++) { 1479 mmio_clrsetbits_32(PHY_REG(ch, 63 + i * 128), 1480 0x03ff << 16, 1481 (wrdqs_delay_val[ch][index][i] & 1482 0x3ff) << 16); 1483 /* resume phy_write_path_lat_add */ 1484 mmio_clrbits_32(PHY_REG(ch, 78 + i * 128), 0x07 << 8); 1485 } 1486 } 1487 1488 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ 1489 mmio_clrsetbits_32(PHY_REG(ch, 86), 0xf << 8, sw_master_mode << 8); 1490 mmio_clrsetbits_32(PHY_REG(ch, 214), 0xf << 8, sw_master_mode << 8); 1491 mmio_clrsetbits_32(PHY_REG(ch, 342), 0xf << 8, sw_master_mode << 8); 1492 mmio_clrsetbits_32(PHY_REG(ch, 470), 0xf << 8, sw_master_mode << 8); 1493 1494 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ 1495 mmio_clrsetbits_32(PHY_REG(ch, 547), 0xf << 16, sw_master_mode << 16); 1496 mmio_clrsetbits_32(PHY_REG(ch, 675), 0xf << 16, sw_master_mode << 16); 1497 mmio_clrsetbits_32(PHY_REG(ch, 803), 0xf << 16, sw_master_mode << 16); 1498 } 1499 1500 static void gen_rk3399_phy_params(struct timing_related_config *timing_config, 1501 struct drv_odt_lp_config *drv_config, 1502 struct dram_timing_t *pdram_timing, 1503 uint32_t fn) 1504 { 1505 uint32_t tmp, i, div, j; 1506 uint32_t mem_delay_ps, pad_delay_ps, total_delay_ps, delay_frac_ps; 1507 uint32_t trpre_min_ps, gate_delay_ps, gate_delay_frac_ps; 1508 uint32_t ie_enable, tsel_enable, cas_lat, rddata_en_ie_dly, tsel_adder; 1509 uint32_t extra_adder, delta, hs_offset; 1510 1511 for (i = 0; i < timing_config->ch_cnt; i++) { 1512 1513 pad_delay_ps = PI_PAD_DELAY_PS_VALUE; 1514 ie_enable = PI_IE_ENABLE_VALUE; 1515 tsel_enable = PI_TSEL_ENABLE_VALUE; 1516 1517 mmio_clrsetbits_32(PHY_REG(i, 896), (0x3 << 8) | 1, fn << 8); 1518 1519 /* PHY_LOW_FREQ_SEL */ 1520 /* DENALI_PHY_913 1bit offset_0 */ 1521 if (timing_config->freq > 400) 1522 mmio_clrbits_32(PHY_REG(i, 913), 1); 1523 else 1524 mmio_setbits_32(PHY_REG(i, 913), 1); 1525 1526 /* PHY_RPTR_UPDATE_x */ 1527 /* DENALI_PHY_87/215/343/471 4bit offset_16 */ 1528 tmp = 2500 / (1000000 / pdram_timing->mhz) + 3; 1529 if ((2500 % (1000000 / pdram_timing->mhz)) != 0) 1530 tmp++; 1531 mmio_clrsetbits_32(PHY_REG(i, 87), 0xf << 16, tmp << 16); 1532 mmio_clrsetbits_32(PHY_REG(i, 215), 0xf << 16, tmp << 16); 1533 mmio_clrsetbits_32(PHY_REG(i, 343), 0xf << 16, tmp << 16); 1534 mmio_clrsetbits_32(PHY_REG(i, 471), 0xf << 16, tmp << 16); 1535 1536 /* PHY_PLL_CTRL */ 1537 /* DENALI_PHY_911 13bits offset_0 */ 1538 /* PHY_LP4_BOOT_PLL_CTRL */ 1539 /* DENALI_PHY_919 13bits offset_0 */ 1540 tmp = (1 << 12) | (2 << 7) | (1 << 1); 1541 mmio_clrsetbits_32(PHY_REG(i, 911), 0x1fff, tmp); 1542 mmio_clrsetbits_32(PHY_REG(i, 919), 0x1fff, tmp); 1543 1544 /* PHY_PLL_CTRL_CA */ 1545 /* DENALI_PHY_911 13bits offset_16 */ 1546 /* PHY_LP4_BOOT_PLL_CTRL_CA */ 1547 /* DENALI_PHY_919 13bits offset_16 */ 1548 tmp = (2 << 7) | (1 << 5) | (1 << 1); 1549 mmio_clrsetbits_32(PHY_REG(i, 911), 0x1fff << 16, tmp << 16); 1550 mmio_clrsetbits_32(PHY_REG(i, 919), 0x1fff << 16, tmp << 16); 1551 1552 /* PHY_TCKSRE_WAIT */ 1553 /* DENALI_PHY_922 4bits offset_24 */ 1554 if (pdram_timing->mhz <= 400) 1555 tmp = 1; 1556 else if (pdram_timing->mhz <= 800) 1557 tmp = 3; 1558 else if (pdram_timing->mhz <= 1000) 1559 tmp = 4; 1560 else 1561 tmp = 5; 1562 mmio_clrsetbits_32(PHY_REG(i, 922), 0xf << 24, tmp << 24); 1563 /* PHY_CAL_CLK_SELECT_0:RW8:3 */ 1564 div = pdram_timing->mhz / (2 * 20); 1565 for (j = 2, tmp = 1; j <= 128; j <<= 1, tmp++) { 1566 if (div < j) 1567 break; 1568 } 1569 mmio_clrsetbits_32(PHY_REG(i, 947), 0x7 << 8, tmp << 8); 1570 1571 if (timing_config->dram_type == DDR3) { 1572 mem_delay_ps = 0; 1573 trpre_min_ps = 1000; 1574 } else if (timing_config->dram_type == LPDDR4) { 1575 mem_delay_ps = 1500; 1576 trpre_min_ps = 900; 1577 } else if (timing_config->dram_type == LPDDR3) { 1578 mem_delay_ps = 2500; 1579 trpre_min_ps = 900; 1580 } else { 1581 ERROR("gen_rk3399_phy_params:dramtype unsupport\n"); 1582 return; 1583 } 1584 total_delay_ps = mem_delay_ps + pad_delay_ps; 1585 delay_frac_ps = 1000 * total_delay_ps / 1586 (1000000 / pdram_timing->mhz); 1587 gate_delay_ps = delay_frac_ps + 1000 - (trpre_min_ps / 2); 1588 gate_delay_frac_ps = gate_delay_ps % 1000; 1589 tmp = gate_delay_frac_ps * 0x200 / 1000; 1590 /* PHY_RDDQS_GATE_SLAVE_DELAY */ 1591 /* DENALI_PHY_77/205/333/461 10bits offset_16 */ 1592 mmio_clrsetbits_32(PHY_REG(i, 77), 0x2ff << 16, tmp << 16); 1593 mmio_clrsetbits_32(PHY_REG(i, 205), 0x2ff << 16, tmp << 16); 1594 mmio_clrsetbits_32(PHY_REG(i, 333), 0x2ff << 16, tmp << 16); 1595 mmio_clrsetbits_32(PHY_REG(i, 461), 0x2ff << 16, tmp << 16); 1596 1597 tmp = gate_delay_ps / 1000; 1598 /* PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST */ 1599 /* DENALI_PHY_10/138/266/394 4bit offset_0 */ 1600 mmio_clrsetbits_32(PHY_REG(i, 10), 0xf, tmp); 1601 mmio_clrsetbits_32(PHY_REG(i, 138), 0xf, tmp); 1602 mmio_clrsetbits_32(PHY_REG(i, 266), 0xf, tmp); 1603 mmio_clrsetbits_32(PHY_REG(i, 394), 0xf, tmp); 1604 /* PHY_GTLVL_LAT_ADJ_START */ 1605 /* DENALI_PHY_80/208/336/464 4bits offset_16 */ 1606 tmp = rddqs_delay_ps / (1000000 / pdram_timing->mhz) + 2; 1607 mmio_clrsetbits_32(PHY_REG(i, 80), 0xf << 16, tmp << 16); 1608 mmio_clrsetbits_32(PHY_REG(i, 208), 0xf << 16, tmp << 16); 1609 mmio_clrsetbits_32(PHY_REG(i, 336), 0xf << 16, tmp << 16); 1610 mmio_clrsetbits_32(PHY_REG(i, 464), 0xf << 16, tmp << 16); 1611 1612 cas_lat = pdram_timing->cl + PI_ADD_LATENCY; 1613 rddata_en_ie_dly = ie_enable / (1000000 / pdram_timing->mhz); 1614 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 1615 rddata_en_ie_dly++; 1616 rddata_en_ie_dly = rddata_en_ie_dly - 1; 1617 tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz); 1618 if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0) 1619 tsel_adder++; 1620 if (rddata_en_ie_dly > tsel_adder) 1621 extra_adder = rddata_en_ie_dly - tsel_adder; 1622 else 1623 extra_adder = 0; 1624 delta = cas_lat - rddata_en_ie_dly; 1625 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 1626 hs_offset = 2; 1627 else 1628 hs_offset = 1; 1629 if (rddata_en_ie_dly > (cas_lat - 1 - hs_offset)) 1630 tmp = 0; 1631 else if ((delta == 2) || (delta == 1)) 1632 tmp = rddata_en_ie_dly - 0 - extra_adder; 1633 else 1634 tmp = extra_adder; 1635 /* PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY */ 1636 /* DENALI_PHY_9/137/265/393 4bit offset_16 */ 1637 mmio_clrsetbits_32(PHY_REG(i, 9), 0xf << 16, tmp << 16); 1638 mmio_clrsetbits_32(PHY_REG(i, 137), 0xf << 16, tmp << 16); 1639 mmio_clrsetbits_32(PHY_REG(i, 265), 0xf << 16, tmp << 16); 1640 mmio_clrsetbits_32(PHY_REG(i, 393), 0xf << 16, tmp << 16); 1641 /* PHY_RDDATA_EN_TSEL_DLY */ 1642 /* DENALI_PHY_86/214/342/470 4bit offset_0 */ 1643 mmio_clrsetbits_32(PHY_REG(i, 86), 0xf, tmp); 1644 mmio_clrsetbits_32(PHY_REG(i, 214), 0xf, tmp); 1645 mmio_clrsetbits_32(PHY_REG(i, 342), 0xf, tmp); 1646 mmio_clrsetbits_32(PHY_REG(i, 470), 0xf, tmp); 1647 1648 if (tsel_adder > rddata_en_ie_dly) 1649 extra_adder = tsel_adder - rddata_en_ie_dly; 1650 else 1651 extra_adder = 0; 1652 if (rddata_en_ie_dly > (cas_lat - 1 - hs_offset)) 1653 tmp = tsel_adder; 1654 else 1655 tmp = rddata_en_ie_dly - 0 + extra_adder; 1656 /* PHY_LP4_BOOT_RDDATA_EN_DLY */ 1657 /* DENALI_PHY_9/137/265/393 4bit offset_8 */ 1658 mmio_clrsetbits_32(PHY_REG(i, 9), 0xf << 8, tmp << 8); 1659 mmio_clrsetbits_32(PHY_REG(i, 137), 0xf << 8, tmp << 8); 1660 mmio_clrsetbits_32(PHY_REG(i, 265), 0xf << 8, tmp << 8); 1661 mmio_clrsetbits_32(PHY_REG(i, 393), 0xf << 8, tmp << 8); 1662 /* PHY_RDDATA_EN_DLY */ 1663 /* DENALI_PHY_85/213/341/469 4bit offset_24 */ 1664 mmio_clrsetbits_32(PHY_REG(i, 85), 0xf << 24, tmp << 24); 1665 mmio_clrsetbits_32(PHY_REG(i, 213), 0xf << 24, tmp << 24); 1666 mmio_clrsetbits_32(PHY_REG(i, 341), 0xf << 24, tmp << 24); 1667 mmio_clrsetbits_32(PHY_REG(i, 469), 0xf << 24, tmp << 24); 1668 1669 if (pdram_timing->mhz <= ENPER_CS_TRAINING_FREQ) { 1670 /* 1671 * Note:Per-CS Training is not compatible at speeds 1672 * under 533 MHz. If the PHY is running at a speed 1673 * less than 533MHz, all phy_per_cs_training_en_X 1674 * parameters must be cleared to 0. 1675 */ 1676 1677 /*DENALI_PHY_84/212/340/468 1bit offset_16 */ 1678 mmio_clrbits_32(PHY_REG(i, 84), 0x1 << 16); 1679 mmio_clrbits_32(PHY_REG(i, 212), 0x1 << 16); 1680 mmio_clrbits_32(PHY_REG(i, 340), 0x1 << 16); 1681 mmio_clrbits_32(PHY_REG(i, 468), 0x1 << 16); 1682 } else { 1683 mmio_setbits_32(PHY_REG(i, 84), 0x1 << 16); 1684 mmio_setbits_32(PHY_REG(i, 212), 0x1 << 16); 1685 mmio_setbits_32(PHY_REG(i, 340), 0x1 << 16); 1686 mmio_setbits_32(PHY_REG(i, 468), 0x1 << 16); 1687 } 1688 gen_rk3399_phy_dll_bypass(pdram_timing->mhz, i, fn, 1689 timing_config->dram_type); 1690 } 1691 } 1692 1693 static int to_get_clk_index(unsigned int mhz) 1694 { 1695 int pll_cnt, i; 1696 1697 pll_cnt = ARRAY_SIZE(dpll_rates_table); 1698 1699 /* Assuming rate_table is in descending order */ 1700 for (i = 0; i < pll_cnt; i++) { 1701 if (mhz >= dpll_rates_table[i].mhz) 1702 break; 1703 } 1704 1705 /* if mhz lower than lowest frequency in table, use lowest frequency */ 1706 if (i == pll_cnt) 1707 i = pll_cnt - 1; 1708 1709 return i; 1710 } 1711 1712 uint32_t ddr_get_rate(void) 1713 { 1714 uint32_t refdiv, postdiv1, fbdiv, postdiv2; 1715 1716 refdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) & 0x3f; 1717 fbdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 0)) & 0xfff; 1718 postdiv1 = 1719 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 8) & 0x7; 1720 postdiv2 = 1721 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 12) & 0x7; 1722 1723 return (24 / refdiv * fbdiv / postdiv1 / postdiv2) * 1000 * 1000; 1724 } 1725 1726 /* 1727 * return: bit12: channel 1, external self-refresh 1728 * bit11: channel 1, stdby_mode 1729 * bit10: channel 1, self-refresh with controller and memory clock gate 1730 * bit9: channel 1, self-refresh 1731 * bit8: channel 1, power-down 1732 * 1733 * bit4: channel 1, external self-refresh 1734 * bit3: channel 0, stdby_mode 1735 * bit2: channel 0, self-refresh with controller and memory clock gate 1736 * bit1: channel 0, self-refresh 1737 * bit0: channel 0, power-down 1738 */ 1739 uint32_t exit_low_power(void) 1740 { 1741 uint32_t low_power = 0; 1742 uint32_t channel_mask; 1743 uint32_t tmp, i; 1744 1745 channel_mask = (mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & 1746 0x3; 1747 for (i = 0; i < 2; i++) { 1748 if (!(channel_mask & (1 << i))) 1749 continue; 1750 1751 /* exit stdby mode */ 1752 mmio_write_32(CIC_BASE + CIC_CTRL1, 1753 (1 << (i + 16)) | (0 << i)); 1754 /* exit external self-refresh */ 1755 tmp = i ? 12 : 8; 1756 low_power |= ((mmio_read_32(PMU_BASE + PMU_SFT_CON) >> tmp) & 1757 0x1) << (4 + 8 * i); 1758 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, 1 << tmp); 1759 while (!(mmio_read_32(PMU_BASE + PMU_DDR_SREF_ST) & (1 << i))) 1760 ; 1761 /* exit auto low-power */ 1762 mmio_clrbits_32(CTL_REG(i, 101), 0x7); 1763 /* lp_cmd to exit */ 1764 if (((mmio_read_32(CTL_REG(i, 100)) >> 24) & 0x7f) != 1765 0x40) { 1766 while (mmio_read_32(CTL_REG(i, 200)) & 0x1) 1767 ; 1768 mmio_clrsetbits_32(CTL_REG(i, 93), 0xffu << 24, 1769 0x69 << 24); 1770 while (((mmio_read_32(CTL_REG(i, 100)) >> 24) & 0x7f) != 1771 0x40) 1772 ; 1773 } 1774 } 1775 return low_power; 1776 } 1777 1778 void resume_low_power(uint32_t low_power) 1779 { 1780 uint32_t channel_mask; 1781 uint32_t tmp, i, val; 1782 1783 channel_mask = (mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & 1784 0x3; 1785 for (i = 0; i < 2; i++) { 1786 if (!(channel_mask & (1 << i))) 1787 continue; 1788 1789 /* resume external self-refresh */ 1790 tmp = i ? 12 : 8; 1791 val = (low_power >> (4 + 8 * i)) & 0x1; 1792 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, val << tmp); 1793 /* resume auto low-power */ 1794 val = (low_power >> (8 * i)) & 0x7; 1795 mmio_setbits_32(CTL_REG(i, 101), val); 1796 /* resume stdby mode */ 1797 val = (low_power >> (3 + 8 * i)) & 0x1; 1798 mmio_write_32(CIC_BASE + CIC_CTRL1, 1799 (1 << (i + 16)) | (val << i)); 1800 } 1801 } 1802 1803 static void dram_low_power_config(void) 1804 { 1805 uint32_t tmp, i; 1806 uint32_t ch_cnt = rk3399_dram_status.timing_config.ch_cnt; 1807 uint32_t dram_type = rk3399_dram_status.timing_config.dram_type; 1808 1809 if (dram_type == DDR3) 1810 tmp = (2 << 16) | (0x7 << 8); 1811 else 1812 tmp = (3 << 16) | (0x7 << 8); 1813 1814 for (i = 0; i < ch_cnt; i++) 1815 mmio_clrsetbits_32(CTL_REG(i, 101), 0x70f0f, tmp); 1816 1817 /* standby idle */ 1818 mmio_write_32(CIC_BASE + CIC_CG_WAIT_TH, 0x640008); 1819 1820 if (ch_cnt == 2) { 1821 mmio_write_32(GRF_BASE + GRF_DDRC1_CON1, 1822 (((0x1<<4) | (0x1<<5) | (0x1<<6) | 1823 (0x1<<7)) << 16) | 1824 ((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7))); 1825 mmio_write_32(CIC_BASE + CIC_CTRL1, 0x002a0028); 1826 } 1827 1828 mmio_write_32(GRF_BASE + GRF_DDRC0_CON1, 1829 (((0x1<<4) | (0x1<<5) | (0x1<<6) | (0x1<<7)) << 16) | 1830 ((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7))); 1831 mmio_write_32(CIC_BASE + CIC_CTRL1, 0x00150014); 1832 } 1833 1834 void dram_dfs_init(void) 1835 { 1836 uint32_t trefi0, trefi1, boot_freq; 1837 uint32_t rddqs_adjust, rddqs_slave; 1838 1839 /* get sdram config for os reg */ 1840 get_dram_drv_odt_val(sdram_config.dramtype, 1841 &rk3399_dram_status.drv_odt_lp_cfg); 1842 sdram_timing_cfg_init(&rk3399_dram_status.timing_config, 1843 &sdram_config, 1844 &rk3399_dram_status.drv_odt_lp_cfg); 1845 1846 trefi0 = ((mmio_read_32(CTL_REG(0, 48)) >> 16) & 0xffff) + 8; 1847 trefi1 = ((mmio_read_32(CTL_REG(0, 49)) >> 16) & 0xffff) + 8; 1848 1849 rk3399_dram_status.index_freq[0] = trefi0 * 10 / 39; 1850 rk3399_dram_status.index_freq[1] = trefi1 * 10 / 39; 1851 rk3399_dram_status.current_index = 1852 (mmio_read_32(CTL_REG(0, 111)) >> 16) & 0x3; 1853 if (rk3399_dram_status.timing_config.dram_type == DDR3) { 1854 rk3399_dram_status.index_freq[0] /= 2; 1855 rk3399_dram_status.index_freq[1] /= 2; 1856 } 1857 boot_freq = 1858 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]; 1859 boot_freq = dpll_rates_table[to_get_clk_index(boot_freq)].mhz; 1860 rk3399_dram_status.boot_freq = boot_freq; 1861 rk3399_dram_status.index_freq[rk3399_dram_status.current_index] = 1862 boot_freq; 1863 rk3399_dram_status.index_freq[(rk3399_dram_status.current_index + 1) & 1864 0x1] = 0; 1865 rk3399_dram_status.low_power_stat = 0; 1866 /* 1867 * following register decide if NOC stall the access request 1868 * or return error when NOC being idled. when doing ddr frequency 1869 * scaling in M0 or DCF, we need to make sure noc stall the access 1870 * request, if return error cpu may data abort when ddr frequency 1871 * changing. it don't need to set this register every times, 1872 * so we init this register in function dram_dfs_init(). 1873 */ 1874 mmio_write_32(GRF_BASE + GRF_SOC_CON(0), 0xffffffff); 1875 mmio_write_32(GRF_BASE + GRF_SOC_CON(1), 0xffffffff); 1876 mmio_write_32(GRF_BASE + GRF_SOC_CON(2), 0xffffffff); 1877 mmio_write_32(GRF_BASE + GRF_SOC_CON(3), 0xffffffff); 1878 mmio_write_32(GRF_BASE + GRF_SOC_CON(4), 0x70007000); 1879 1880 /* Disable multicast */ 1881 mmio_clrbits_32(PHY_REG(0, 896), 1); 1882 mmio_clrbits_32(PHY_REG(1, 896), 1); 1883 dram_low_power_config(); 1884 1885 /* 1886 * If boot_freq isn't in the bypass mode, it can get the 1887 * rddqs_delay_ps from the result of gate training 1888 */ 1889 if (((mmio_read_32(PHY_REG(0, 86)) >> 8) & 0xf) != 0xc) { 1890 1891 /* 1892 * Select PHY's frequency set to current_index 1893 * index for get the result of gate Training 1894 * from registers 1895 */ 1896 mmio_clrsetbits_32(PHY_REG(0, 896), 0x3 << 8, 1897 rk3399_dram_status.current_index << 8); 1898 rddqs_slave = (mmio_read_32(PHY_REG(0, 77)) >> 16) & 0x3ff; 1899 rddqs_slave = rddqs_slave * 1000000 / boot_freq / 512; 1900 1901 rddqs_adjust = mmio_read_32(PHY_REG(0, 78)) & 0xf; 1902 rddqs_adjust = rddqs_adjust * 1000000 / boot_freq; 1903 rddqs_delay_ps = rddqs_slave + rddqs_adjust - 1904 (1000000 / boot_freq / 2); 1905 } else { 1906 rddqs_delay_ps = 3500; 1907 } 1908 } 1909 1910 /* 1911 * arg0: bit0-7: sr_idle; bit8-15:sr_mc_gate_idle; bit16-31: standby idle 1912 * arg1: bit0-11: pd_idle; bit 16-27: srpd_lite_idle 1913 * arg2: bit0: if odt en 1914 */ 1915 uint32_t dram_set_odt_pd(uint32_t arg0, uint32_t arg1, uint32_t arg2) 1916 { 1917 struct drv_odt_lp_config *lp_cfg = &rk3399_dram_status.drv_odt_lp_cfg; 1918 uint32_t *low_power = &rk3399_dram_status.low_power_stat; 1919 uint32_t dram_type, ch_count, pd_tmp, sr_tmp, i; 1920 1921 dram_type = rk3399_dram_status.timing_config.dram_type; 1922 ch_count = rk3399_dram_status.timing_config.ch_cnt; 1923 1924 lp_cfg->sr_idle = arg0 & 0xff; 1925 lp_cfg->sr_mc_gate_idle = (arg0 >> 8) & 0xff; 1926 lp_cfg->standby_idle = (arg0 >> 16) & 0xffff; 1927 lp_cfg->pd_idle = arg1 & 0xfff; 1928 lp_cfg->srpd_lite_idle = (arg1 >> 16) & 0xfff; 1929 1930 rk3399_dram_status.timing_config.odt = arg2 & 0x1; 1931 1932 exit_low_power(); 1933 1934 *low_power = 0; 1935 1936 /* pd_idle en */ 1937 if (lp_cfg->pd_idle) 1938 *low_power |= ((1 << 0) | (1 << 8)); 1939 /* sr_idle en srpd_lite_idle */ 1940 if (lp_cfg->sr_idle | lp_cfg->srpd_lite_idle) 1941 *low_power |= ((1 << 1) | (1 << 9)); 1942 /* sr_mc_gate_idle */ 1943 if (lp_cfg->sr_mc_gate_idle) 1944 *low_power |= ((1 << 2) | (1 << 10)); 1945 /* standbyidle */ 1946 if (lp_cfg->standby_idle) { 1947 if (rk3399_dram_status.timing_config.ch_cnt == 2) 1948 *low_power |= ((1 << 3) | (1 << 11)); 1949 else 1950 *low_power |= (1 << 3); 1951 } 1952 1953 pd_tmp = arg1; 1954 if (dram_type != LPDDR4) 1955 pd_tmp = arg1 & 0xfff; 1956 sr_tmp = arg0 & 0xffff; 1957 for (i = 0; i < ch_count; i++) { 1958 mmio_write_32(CTL_REG(i, 102), pd_tmp); 1959 mmio_clrsetbits_32(CTL_REG(i, 103), 0xffff, sr_tmp); 1960 } 1961 mmio_write_32(CIC_BASE + CIC_IDLE_TH, (arg0 >> 16) & 0xffff); 1962 1963 return 0; 1964 } 1965 1966 static void m0_configure_ddr(struct pll_div pll_div, uint32_t ddr_index) 1967 { 1968 mmio_write_32(M0_PARAM_ADDR + PARAM_DPLL_CON0, FBDIV(pll_div.fbdiv)); 1969 mmio_write_32(M0_PARAM_ADDR + PARAM_DPLL_CON1, 1970 POSTDIV2(pll_div.postdiv2) | POSTDIV1(pll_div.postdiv1) | 1971 REFDIV(pll_div.refdiv)); 1972 1973 mmio_write_32(M0_PARAM_ADDR + PARAM_DRAM_FREQ, pll_div.mhz); 1974 1975 mmio_write_32(M0_PARAM_ADDR + PARAM_FREQ_SELECT, ddr_index << 4); 1976 dmbst(); 1977 m0_configure_execute_addr(M0_BINCODE_BASE); 1978 } 1979 1980 static uint32_t prepare_ddr_timing(uint32_t mhz) 1981 { 1982 uint32_t index; 1983 struct dram_timing_t dram_timing; 1984 1985 rk3399_dram_status.timing_config.freq = mhz; 1986 1987 if (mhz < 300) 1988 rk3399_dram_status.timing_config.dllbp = 1; 1989 else 1990 rk3399_dram_status.timing_config.dllbp = 0; 1991 1992 if (rk3399_dram_status.timing_config.odt == 1) 1993 gen_rk3399_set_odt(1); 1994 1995 index = (rk3399_dram_status.current_index + 1) & 0x1; 1996 1997 /* 1998 * checking if having available gate traiing timing for 1999 * target freq. 2000 */ 2001 dram_get_parameter(&rk3399_dram_status.timing_config, &dram_timing); 2002 gen_rk3399_ctl_params(&rk3399_dram_status.timing_config, 2003 &dram_timing, index); 2004 gen_rk3399_pi_params(&rk3399_dram_status.timing_config, 2005 &dram_timing, index); 2006 gen_rk3399_phy_params(&rk3399_dram_status.timing_config, 2007 &rk3399_dram_status.drv_odt_lp_cfg, 2008 &dram_timing, index); 2009 rk3399_dram_status.index_freq[index] = mhz; 2010 2011 return index; 2012 } 2013 2014 uint32_t ddr_set_rate(uint32_t hz) 2015 { 2016 uint32_t low_power, index, ddr_index; 2017 uint32_t mhz = hz / (1000 * 1000); 2018 2019 if (mhz == 2020 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]) 2021 return mhz; 2022 2023 index = to_get_clk_index(mhz); 2024 mhz = dpll_rates_table[index].mhz; 2025 2026 ddr_index = prepare_ddr_timing(mhz); 2027 gen_rk3399_enable_training(rk3399_dram_status.timing_config.ch_cnt, 2028 mhz); 2029 if (ddr_index > 1) 2030 goto out; 2031 2032 /* 2033 * Make sure the clock is enabled. The M0 clocks should be on all of the 2034 * time during S0. 2035 */ 2036 m0_configure_ddr(dpll_rates_table[index], ddr_index); 2037 m0_start(); 2038 m0_wait_done(); 2039 m0_stop(); 2040 2041 if (rk3399_dram_status.timing_config.odt == 0) 2042 gen_rk3399_set_odt(0); 2043 2044 rk3399_dram_status.current_index = ddr_index; 2045 low_power = rk3399_dram_status.low_power_stat; 2046 resume_low_power(low_power); 2047 out: 2048 gen_rk3399_disable_training(rk3399_dram_status.timing_config.ch_cnt); 2049 return mhz; 2050 } 2051 2052 uint32_t ddr_round_rate(uint32_t hz) 2053 { 2054 int index; 2055 uint32_t mhz = hz / (1000 * 1000); 2056 2057 index = to_get_clk_index(mhz); 2058 2059 return dpll_rates_table[index].mhz * 1000 * 1000; 2060 } 2061 2062 void ddr_prepare_for_sys_suspend(void) 2063 { 2064 uint32_t mhz = 2065 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]; 2066 2067 /* 2068 * If we're not currently at the boot (assumed highest) frequency, we 2069 * need to change frequencies to configure out current index. 2070 */ 2071 rk3399_suspend_status.freq = mhz; 2072 exit_low_power(); 2073 rk3399_suspend_status.low_power_stat = 2074 rk3399_dram_status.low_power_stat; 2075 rk3399_suspend_status.odt = rk3399_dram_status.timing_config.odt; 2076 rk3399_dram_status.low_power_stat = 0; 2077 rk3399_dram_status.timing_config.odt = 1; 2078 if (mhz != rk3399_dram_status.boot_freq) 2079 ddr_set_rate(rk3399_dram_status.boot_freq * 1000 * 1000); 2080 2081 /* 2082 * This will configure the other index to be the same frequency as the 2083 * current one. We retrain both indices on resume, so both have to be 2084 * setup for the same frequency. 2085 */ 2086 prepare_ddr_timing(rk3399_dram_status.boot_freq); 2087 } 2088 2089 void ddr_prepare_for_sys_resume(void) 2090 { 2091 /* Disable multicast */ 2092 mmio_clrbits_32(PHY_REG(0, 896), 1); 2093 mmio_clrbits_32(PHY_REG(1, 896), 1); 2094 2095 /* The suspend code changes the current index, so reset it now. */ 2096 rk3399_dram_status.current_index = 2097 (mmio_read_32(CTL_REG(0, 111)) >> 16) & 0x3; 2098 rk3399_dram_status.low_power_stat = 2099 rk3399_suspend_status.low_power_stat; 2100 rk3399_dram_status.timing_config.odt = rk3399_suspend_status.odt; 2101 2102 /* 2103 * Set the saved frequency from suspend if it's different than the 2104 * current frequency. 2105 */ 2106 if (rk3399_suspend_status.freq != 2107 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]) { 2108 ddr_set_rate(rk3399_suspend_status.freq * 1000 * 1000); 2109 return; 2110 } 2111 2112 gen_rk3399_set_odt(rk3399_dram_status.timing_config.odt); 2113 resume_low_power(rk3399_dram_status.low_power_stat); 2114 } 2115