1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <debug.h> 32 #include <mmio.h> 33 #include <plat_private.h> 34 #include "dfs.h" 35 #include "dram.h" 36 #include "dram_spec_timing.h" 37 #include "string.h" 38 #include "soc.h" 39 #include "pmu.h" 40 41 #include <delay_timer.h> 42 43 #define ENPER_CS_TRAINING_FREQ (933) 44 #define PHY_DLL_BYPASS_FREQ (260) 45 46 struct pll_div { 47 uint32_t mhz; 48 uint32_t refdiv; 49 uint32_t fbdiv; 50 uint32_t postdiv1; 51 uint32_t postdiv2; 52 uint32_t frac; 53 uint32_t freq; 54 }; 55 56 static const struct pll_div dpll_rates_table[] = { 57 58 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2 */ 59 {.mhz = 933, .refdiv = 3, .fbdiv = 350, .postdiv1 = 3, .postdiv2 = 1}, 60 {.mhz = 800, .refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}, 61 {.mhz = 732, .refdiv = 1, .fbdiv = 61, .postdiv1 = 2, .postdiv2 = 1}, 62 {.mhz = 666, .refdiv = 1, .fbdiv = 111, .postdiv1 = 4, .postdiv2 = 1}, 63 {.mhz = 600, .refdiv = 1, .fbdiv = 50, .postdiv1 = 2, .postdiv2 = 1}, 64 {.mhz = 528, .refdiv = 1, .fbdiv = 66, .postdiv1 = 3, .postdiv2 = 1}, 65 {.mhz = 400, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}, 66 {.mhz = 300, .refdiv = 1, .fbdiv = 50, .postdiv1 = 4, .postdiv2 = 1}, 67 {.mhz = 200, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 2}, 68 }; 69 70 struct rk3399_dram_status { 71 uint32_t current_index; 72 uint32_t index_freq[2]; 73 uint32_t low_power_stat; 74 struct timing_related_config timing_config; 75 struct drv_odt_lp_config drv_odt_lp_cfg; 76 }; 77 78 static struct rk3399_dram_status rk3399_dram_status; 79 static uint32_t wrdqs_delay_val[2][2][4]; 80 81 static struct rk3399_sdram_default_config ddr3_default_config = { 82 .bl = 8, 83 .ap = 0, 84 .burst_ref_cnt = 1, 85 .zqcsi = 0 86 }; 87 88 static struct rk3399_sdram_default_config lpddr3_default_config = { 89 .bl = 8, 90 .ap = 0, 91 .burst_ref_cnt = 1, 92 .zqcsi = 0 93 }; 94 95 static struct rk3399_sdram_default_config lpddr4_default_config = { 96 .bl = 16, 97 .ap = 0, 98 .caodt = 240, 99 .burst_ref_cnt = 1, 100 .zqcsi = 0 101 }; 102 103 uint32_t dcf_code[] = { 104 #include "dcf_code.inc" 105 }; 106 107 #define DCF_START_ADDR (SRAM_BASE + 0x1400) 108 #define DCF_PARAM_ADDR (SRAM_BASE + 0x1000) 109 110 /* DCF_PAMET */ 111 #define PARAM_DRAM_FREQ (0) 112 #define PARAM_DPLL_CON0 (4) 113 #define PARAM_DPLL_CON1 (8) 114 #define PARAM_DPLL_CON2 (0xc) 115 #define PARAM_DPLL_CON3 (0x10) 116 #define PARAM_DPLL_CON4 (0x14) 117 #define PARAM_DPLL_CON5 (0x18) 118 /* equal to fn<<4 */ 119 #define PARAM_FREQ_SELECT (0x1c) 120 121 static uint32_t get_cs_die_capability(struct rk3399_sdram_params *sdram_config, 122 uint8_t channel, uint8_t cs) 123 { 124 struct rk3399_sdram_channel *ch = &sdram_config->ch[channel]; 125 uint32_t bandwidth; 126 uint32_t die_bandwidth; 127 uint32_t die; 128 uint32_t cs_cap; 129 uint32_t row; 130 131 row = cs == 0 ? ch->cs0_row : ch->cs1_row; 132 bandwidth = 8 * (1 << ch->bw); 133 die_bandwidth = 8 * (1 << ch->dbw); 134 die = bandwidth / die_bandwidth; 135 cs_cap = (1 << (row + ((1 << ch->bk) / 4 + 1) + ch->col + 136 (bandwidth / 16))); 137 if (ch->row_3_4) 138 cs_cap = cs_cap * 3 / 4; 139 140 return (cs_cap / die); 141 } 142 143 static void get_dram_drv_odt_val(uint32_t dram_type, 144 struct drv_odt_lp_config *drv_config) 145 { 146 uint32_t tmp; 147 uint32_t mr1_val, mr3_val, mr11_val; 148 149 switch (dram_type) { 150 case DDR3: 151 mr1_val = (mmio_read_32(CTL_REG(0, 133)) >> 16) & 0xffff; 152 tmp = ((mr1_val >> 1) & 1) | ((mr1_val >> 4) & 1); 153 if (tmp) 154 drv_config->dram_side_drv = 34; 155 else 156 drv_config->dram_side_drv = 40; 157 tmp = ((mr1_val >> 2) & 1) | ((mr1_val >> 5) & 1) | 158 ((mr1_val >> 7) & 1); 159 if (tmp == 0) 160 drv_config->dram_side_dq_odt = 0; 161 else if (tmp == 1) 162 drv_config->dram_side_dq_odt = 60; 163 else if (tmp == 3) 164 drv_config->dram_side_dq_odt = 40; 165 else 166 drv_config->dram_side_dq_odt = 120; 167 break; 168 case LPDDR3: 169 mr3_val = mmio_read_32(CTL_REG(0, 138)) & 0xf; 170 mr11_val = (mmio_read_32(CTL_REG(0, 139)) >> 24) & 0x3; 171 if (mr3_val == 0xb) 172 drv_config->dram_side_drv = 3448; 173 else if (mr3_val == 0xa) 174 drv_config->dram_side_drv = 4048; 175 else if (mr3_val == 0x9) 176 drv_config->dram_side_drv = 3440; 177 else if (mr3_val == 0x4) 178 drv_config->dram_side_drv = 60; 179 else if (mr3_val == 0x3) 180 drv_config->dram_side_drv = 48; 181 else if (mr3_val == 0x2) 182 drv_config->dram_side_drv = 40; 183 else 184 drv_config->dram_side_drv = 34; 185 186 if (mr11_val == 1) 187 drv_config->dram_side_dq_odt = 60; 188 else if (mr11_val == 2) 189 drv_config->dram_side_dq_odt = 120; 190 else if (mr11_val == 0) 191 drv_config->dram_side_dq_odt = 0; 192 else 193 drv_config->dram_side_dq_odt = 240; 194 break; 195 case LPDDR4: 196 default: 197 mr3_val = (mmio_read_32(CTL_REG(0, 138)) >> 3) & 0x7; 198 mr11_val = (mmio_read_32(CTL_REG(0, 139)) >> 24) & 0xff; 199 200 if ((mr3_val == 0) || (mr3_val == 7)) 201 drv_config->dram_side_drv = 40; 202 else 203 drv_config->dram_side_drv = 240 / mr3_val; 204 205 tmp = mr11_val & 0x7; 206 if ((tmp == 7) || (tmp == 0)) 207 drv_config->dram_side_dq_odt = 0; 208 else 209 drv_config->dram_side_dq_odt = 240 / tmp; 210 211 tmp = (mr11_val >> 4) & 0x7; 212 if ((tmp == 7) || (tmp == 0)) 213 drv_config->dram_side_ca_odt = 0; 214 else 215 drv_config->dram_side_ca_odt = 240 / tmp; 216 break; 217 } 218 } 219 220 static void sdram_timing_cfg_init(struct timing_related_config *ptiming_config, 221 struct rk3399_sdram_params *sdram_params, 222 struct drv_odt_lp_config *drv_config) 223 { 224 uint32_t i, j; 225 226 for (i = 0; i < sdram_params->num_channels; i++) { 227 ptiming_config->dram_info[i].speed_rate = DDR3_DEFAULT; 228 ptiming_config->dram_info[i].cs_cnt = sdram_params->ch[i].rank; 229 for (j = 0; j < sdram_params->ch[i].rank; j++) { 230 ptiming_config->dram_info[i].per_die_capability[j] = 231 get_cs_die_capability(sdram_params, i, j); 232 } 233 } 234 ptiming_config->dram_type = sdram_params->dramtype; 235 ptiming_config->ch_cnt = sdram_params->num_channels; 236 switch (sdram_params->dramtype) { 237 case DDR3: 238 ptiming_config->bl = ddr3_default_config.bl; 239 ptiming_config->ap = ddr3_default_config.ap; 240 break; 241 case LPDDR3: 242 ptiming_config->bl = lpddr3_default_config.bl; 243 ptiming_config->ap = lpddr3_default_config.ap; 244 break; 245 case LPDDR4: 246 ptiming_config->bl = lpddr4_default_config.bl; 247 ptiming_config->ap = lpddr4_default_config.ap; 248 ptiming_config->rdbi = 0; 249 ptiming_config->wdbi = 0; 250 break; 251 } 252 ptiming_config->dramds = drv_config->dram_side_drv; 253 ptiming_config->dramodt = drv_config->dram_side_dq_odt; 254 ptiming_config->caodt = drv_config->dram_side_ca_odt; 255 } 256 257 struct lat_adj_pair { 258 uint32_t cl; 259 uint32_t rdlat_adj; 260 uint32_t cwl; 261 uint32_t wrlat_adj; 262 }; 263 264 const struct lat_adj_pair ddr3_lat_adj[] = { 265 {6, 5, 5, 4}, 266 {8, 7, 6, 5}, 267 {10, 9, 7, 6}, 268 {11, 9, 8, 7}, 269 {13, 0xb, 9, 8}, 270 {14, 0xb, 0xa, 9} 271 }; 272 273 const struct lat_adj_pair lpddr3_lat_adj[] = { 274 {3, 2, 1, 0}, 275 {6, 5, 3, 2}, 276 {8, 7, 4, 3}, 277 {9, 8, 5, 4}, 278 {10, 9, 6, 5}, 279 {11, 9, 6, 5}, 280 {12, 0xa, 6, 5}, 281 {14, 0xc, 8, 7}, 282 {16, 0xd, 8, 7} 283 }; 284 285 const struct lat_adj_pair lpddr4_lat_adj[] = { 286 {6, 5, 4, 2}, 287 {10, 9, 6, 4}, 288 {14, 0xc, 8, 6}, 289 {20, 0x11, 0xa, 8}, 290 {24, 0x15, 0xc, 0xa}, 291 {28, 0x18, 0xe, 0xc}, 292 {32, 0x1b, 0x10, 0xe}, 293 {36, 0x1e, 0x12, 0x10} 294 }; 295 296 static uint32_t get_rdlat_adj(uint32_t dram_type, uint32_t cl) 297 { 298 const struct lat_adj_pair *p; 299 uint32_t cnt; 300 uint32_t i; 301 302 if (dram_type == DDR3) { 303 p = ddr3_lat_adj; 304 cnt = ARRAY_SIZE(ddr3_lat_adj); 305 } else if (dram_type == LPDDR3) { 306 p = lpddr3_lat_adj; 307 cnt = ARRAY_SIZE(lpddr3_lat_adj); 308 } else { 309 p = lpddr4_lat_adj; 310 cnt = ARRAY_SIZE(lpddr4_lat_adj); 311 } 312 313 for (i = 0; i < cnt; i++) { 314 if (cl == p[i].cl) 315 return p[i].rdlat_adj; 316 } 317 /* fail */ 318 return 0xff; 319 } 320 321 static uint32_t get_wrlat_adj(uint32_t dram_type, uint32_t cwl) 322 { 323 const struct lat_adj_pair *p; 324 uint32_t cnt; 325 uint32_t i; 326 327 if (dram_type == DDR3) { 328 p = ddr3_lat_adj; 329 cnt = ARRAY_SIZE(ddr3_lat_adj); 330 } else if (dram_type == LPDDR3) { 331 p = lpddr3_lat_adj; 332 cnt = ARRAY_SIZE(lpddr3_lat_adj); 333 } else { 334 p = lpddr4_lat_adj; 335 cnt = ARRAY_SIZE(lpddr4_lat_adj); 336 } 337 338 for (i = 0; i < cnt; i++) { 339 if (cwl == p[i].cwl) 340 return p[i].wrlat_adj; 341 } 342 /* fail */ 343 return 0xff; 344 } 345 346 #define PI_REGS_DIMM_SUPPORT (0) 347 #define PI_ADD_LATENCY (0) 348 #define PI_DOUBLEFREEK (1) 349 350 #define PI_PAD_DELAY_PS_VALUE (1000) 351 #define PI_IE_ENABLE_VALUE (3000) 352 #define PI_TSEL_ENABLE_VALUE (700) 353 354 static uint32_t get_pi_rdlat_adj(struct dram_timing_t *pdram_timing) 355 { 356 /*[DLLSUBTYPE2] == "STD_DENALI_HS" */ 357 uint32_t rdlat, delay_adder, ie_enable, hs_offset, tsel_adder, 358 extra_adder, tsel_enable; 359 360 ie_enable = PI_IE_ENABLE_VALUE; 361 tsel_enable = PI_TSEL_ENABLE_VALUE; 362 363 rdlat = pdram_timing->cl + PI_ADD_LATENCY; 364 delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 365 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 366 delay_adder++; 367 hs_offset = 0; 368 tsel_adder = 0; 369 extra_adder = 0; 370 /* rdlat = rdlat - (PREAMBLE_SUPPORT & 0x1); */ 371 tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz); 372 if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0) 373 tsel_adder++; 374 delay_adder = delay_adder - 1; 375 if (tsel_adder > delay_adder) 376 extra_adder = tsel_adder - delay_adder; 377 else 378 extra_adder = 0; 379 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 380 hs_offset = 2; 381 else 382 hs_offset = 1; 383 384 if (delay_adder > (rdlat - 1 - hs_offset)) { 385 rdlat = rdlat - tsel_adder; 386 } else { 387 if ((rdlat - delay_adder) < 2) 388 rdlat = 2; 389 else 390 rdlat = rdlat - delay_adder - extra_adder; 391 } 392 393 return rdlat; 394 } 395 396 static uint32_t get_pi_wrlat(struct dram_timing_t *pdram_timing, 397 struct timing_related_config *timing_config) 398 { 399 uint32_t tmp; 400 401 if (timing_config->dram_type == LPDDR3) { 402 tmp = pdram_timing->cl; 403 if (tmp >= 14) 404 tmp = 8; 405 else if (tmp >= 10) 406 tmp = 6; 407 else if (tmp == 9) 408 tmp = 5; 409 else if (tmp == 8) 410 tmp = 4; 411 else if (tmp == 6) 412 tmp = 3; 413 else 414 tmp = 1; 415 } else { 416 tmp = 1; 417 } 418 419 return tmp; 420 } 421 422 static uint32_t get_pi_wrlat_adj(struct dram_timing_t *pdram_timing, 423 struct timing_related_config *timing_config) 424 { 425 return get_pi_wrlat(pdram_timing, timing_config) + PI_ADD_LATENCY - 1; 426 } 427 428 static uint32_t get_pi_tdfi_phy_rdlat(struct dram_timing_t *pdram_timing, 429 struct timing_related_config *timing_config) 430 { 431 /* [DLLSUBTYPE2] == "STD_DENALI_HS" */ 432 uint32_t cas_lat, delay_adder, ie_enable, hs_offset, ie_delay_adder; 433 uint32_t mem_delay_ps, round_trip_ps; 434 uint32_t phy_internal_delay, lpddr_adder, dfi_adder, rdlat_delay; 435 436 ie_enable = PI_IE_ENABLE_VALUE; 437 438 delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 439 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 440 delay_adder++; 441 delay_adder = delay_adder - 1; 442 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 443 hs_offset = 2; 444 else 445 hs_offset = 1; 446 447 cas_lat = pdram_timing->cl + PI_ADD_LATENCY; 448 449 if (delay_adder > (cas_lat - 1 - hs_offset)) { 450 ie_delay_adder = 0; 451 } else { 452 ie_delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 453 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 454 ie_delay_adder++; 455 } 456 457 if (timing_config->dram_type == DDR3) { 458 mem_delay_ps = 0; 459 } else if (timing_config->dram_type == LPDDR4) { 460 mem_delay_ps = 3600; 461 } else if (timing_config->dram_type == LPDDR3) { 462 mem_delay_ps = 5500; 463 } else { 464 printf("get_pi_tdfi_phy_rdlat:dramtype unsupport\n"); 465 return 0; 466 } 467 round_trip_ps = 1100 + 500 + mem_delay_ps + 500 + 600; 468 delay_adder = round_trip_ps / (1000000 / pdram_timing->mhz); 469 if ((round_trip_ps % (1000000 / pdram_timing->mhz)) != 0) 470 delay_adder++; 471 472 phy_internal_delay = 5 + 2 + 4; 473 lpddr_adder = mem_delay_ps / (1000000 / pdram_timing->mhz); 474 if ((mem_delay_ps % (1000000 / pdram_timing->mhz)) != 0) 475 lpddr_adder++; 476 dfi_adder = 0; 477 phy_internal_delay = phy_internal_delay + 2; 478 rdlat_delay = delay_adder + phy_internal_delay + 479 ie_delay_adder + lpddr_adder + dfi_adder; 480 481 rdlat_delay = rdlat_delay + 2; 482 return rdlat_delay; 483 } 484 485 static uint32_t get_pi_todtoff_min(struct dram_timing_t *pdram_timing, 486 struct timing_related_config *timing_config) 487 { 488 uint32_t tmp, todtoff_min_ps; 489 490 if (timing_config->dram_type == LPDDR3) 491 todtoff_min_ps = 2500; 492 else if (timing_config->dram_type == LPDDR4) 493 todtoff_min_ps = 1500; 494 else 495 todtoff_min_ps = 0; 496 /* todtoff_min */ 497 tmp = todtoff_min_ps / (1000000 / pdram_timing->mhz); 498 if ((todtoff_min_ps % (1000000 / pdram_timing->mhz)) != 0) 499 tmp++; 500 return tmp; 501 } 502 503 static uint32_t get_pi_todtoff_max(struct dram_timing_t *pdram_timing, 504 struct timing_related_config *timing_config) 505 { 506 uint32_t tmp, todtoff_max_ps; 507 508 if ((timing_config->dram_type == LPDDR4) 509 || (timing_config->dram_type == LPDDR3)) 510 todtoff_max_ps = 3500; 511 else 512 todtoff_max_ps = 0; 513 514 /* todtoff_max */ 515 tmp = todtoff_max_ps / (1000000 / pdram_timing->mhz); 516 if ((todtoff_max_ps % (1000000 / pdram_timing->mhz)) != 0) 517 tmp++; 518 return tmp; 519 } 520 521 static void gen_rk3399_ctl_params_f0(struct timing_related_config 522 *timing_config, 523 struct dram_timing_t *pdram_timing) 524 { 525 uint32_t i; 526 uint32_t tmp, tmp1; 527 528 for (i = 0; i < timing_config->ch_cnt; i++) { 529 if (timing_config->dram_type == DDR3) { 530 tmp = ((700000 + 10) * timing_config->freq + 531 999) / 1000; 532 tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) + 533 pdram_timing->tmod + pdram_timing->tzqinit; 534 mmio_write_32(CTL_REG(i, 5), tmp); 535 536 mmio_clrsetbits_32(CTL_REG(i, 22), 0xffff, 537 pdram_timing->tdllk); 538 539 mmio_write_32(CTL_REG(i, 32), 540 (pdram_timing->tmod << 8) | 541 pdram_timing->tmrd); 542 543 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16, 544 (pdram_timing->txsr - 545 pdram_timing->trcd) << 16); 546 } else if (timing_config->dram_type == LPDDR4) { 547 mmio_write_32(CTL_REG(i, 5), pdram_timing->tinit1 + 548 pdram_timing->tinit3); 549 mmio_write_32(CTL_REG(i, 32), 550 (pdram_timing->tmrd << 8) | 551 pdram_timing->tmrd); 552 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16, 553 pdram_timing->txsr << 16); 554 } else { 555 mmio_write_32(CTL_REG(i, 5), pdram_timing->tinit1); 556 mmio_write_32(CTL_REG(i, 7), pdram_timing->tinit4); 557 mmio_write_32(CTL_REG(i, 32), 558 (pdram_timing->tmrd << 8) | 559 pdram_timing->tmrd); 560 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16, 561 pdram_timing->txsr << 16); 562 } 563 mmio_write_32(CTL_REG(i, 6), pdram_timing->tinit3); 564 mmio_write_32(CTL_REG(i, 8), pdram_timing->tinit5); 565 mmio_clrsetbits_32(CTL_REG(i, 23), (0x7f << 16), 566 ((pdram_timing->cl * 2) << 16)); 567 mmio_clrsetbits_32(CTL_REG(i, 23), (0x1f << 24), 568 (pdram_timing->cwl << 24)); 569 mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f, pdram_timing->al); 570 mmio_clrsetbits_32(CTL_REG(i, 26), 0xffff << 16, 571 (pdram_timing->trc << 24) | 572 (pdram_timing->trrd << 16)); 573 mmio_write_32(CTL_REG(i, 27), 574 (pdram_timing->tfaw << 24) | 575 (pdram_timing->trppb << 16) | 576 (pdram_timing->twtr << 8) | 577 pdram_timing->tras_min); 578 579 mmio_clrsetbits_32(CTL_REG(i, 31), 0xff << 24, 580 max(4, pdram_timing->trtp) << 24); 581 mmio_write_32(CTL_REG(i, 33), (pdram_timing->tcke << 24) | 582 pdram_timing->tras_max); 583 mmio_clrsetbits_32(CTL_REG(i, 34), 0xff, 584 max(1, pdram_timing->tckesr)); 585 mmio_clrsetbits_32(CTL_REG(i, 39), 586 (0x3f << 16) | (0xff << 8), 587 (pdram_timing->twr << 16) | 588 (pdram_timing->trcd << 8)); 589 mmio_clrsetbits_32(CTL_REG(i, 42), 0x1f << 16, 590 pdram_timing->tmrz << 16); 591 tmp = pdram_timing->tdal ? pdram_timing->tdal : 592 (pdram_timing->twr + pdram_timing->trp); 593 mmio_clrsetbits_32(CTL_REG(i, 44), 0xff, tmp); 594 mmio_clrsetbits_32(CTL_REG(i, 45), 0xff, pdram_timing->trp); 595 mmio_write_32(CTL_REG(i, 48), 596 ((pdram_timing->trefi - 8) << 16) | 597 pdram_timing->trfc); 598 mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff, pdram_timing->txp); 599 mmio_clrsetbits_32(CTL_REG(i, 53), 0xffff << 16, 600 pdram_timing->txpdll << 16); 601 mmio_clrsetbits_32(CTL_REG(i, 55), 0xf << 24, 602 pdram_timing->tcscke << 24); 603 mmio_clrsetbits_32(CTL_REG(i, 55), 0xff, pdram_timing->tmrri); 604 mmio_write_32(CTL_REG(i, 56), 605 (pdram_timing->tzqcke << 24) | 606 (pdram_timing->tmrwckel << 16) | 607 (pdram_timing->tckehcs << 8) | 608 pdram_timing->tckelcs); 609 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff, pdram_timing->txsnr); 610 mmio_clrsetbits_32(CTL_REG(i, 62), 0xffff << 16, 611 (pdram_timing->tckehcmd << 24) | 612 (pdram_timing->tckelcmd << 16)); 613 mmio_write_32(CTL_REG(i, 63), 614 (pdram_timing->tckelpd << 24) | 615 (pdram_timing->tescke << 16) | 616 (pdram_timing->tsr << 8) | 617 pdram_timing->tckckel); 618 mmio_clrsetbits_32(CTL_REG(i, 64), 0xfff, 619 (pdram_timing->tcmdcke << 8) | 620 pdram_timing->tcsckeh); 621 mmio_clrsetbits_32(CTL_REG(i, 92), 0xffff << 8, 622 (pdram_timing->tcksrx << 16) | 623 (pdram_timing->tcksre << 8)); 624 mmio_clrsetbits_32(CTL_REG(i, 108), 0x1 << 24, 625 (timing_config->dllbp << 24)); 626 mmio_clrsetbits_32(CTL_REG(i, 122), 0x3ff << 16, 627 (pdram_timing->tvrcg_enable << 16)); 628 mmio_write_32(CTL_REG(i, 123), (pdram_timing->tfc_long << 16) | 629 pdram_timing->tvrcg_disable); 630 mmio_write_32(CTL_REG(i, 124), 631 (pdram_timing->tvref_long << 16) | 632 (pdram_timing->tckfspx << 8) | 633 pdram_timing->tckfspe); 634 mmio_write_32(CTL_REG(i, 133), (pdram_timing->mr[1] << 16) | 635 pdram_timing->mr[0]); 636 mmio_clrsetbits_32(CTL_REG(i, 134), 0xffff, 637 pdram_timing->mr[2]); 638 mmio_clrsetbits_32(CTL_REG(i, 138), 0xffff, 639 pdram_timing->mr[3]); 640 mmio_clrsetbits_32(CTL_REG(i, 139), 0xff << 24, 641 pdram_timing->mr11 << 24); 642 mmio_write_32(CTL_REG(i, 147), 643 (pdram_timing->mr[1] << 16) | 644 pdram_timing->mr[0]); 645 mmio_clrsetbits_32(CTL_REG(i, 148), 0xffff, 646 pdram_timing->mr[2]); 647 mmio_clrsetbits_32(CTL_REG(i, 152), 0xffff, 648 pdram_timing->mr[3]); 649 mmio_clrsetbits_32(CTL_REG(i, 153), 0xff << 24, 650 pdram_timing->mr11 << 24); 651 if (timing_config->dram_type == LPDDR4) { 652 mmio_clrsetbits_32(CTL_REG(i, 140), 0xffff << 16, 653 pdram_timing->mr12 << 16); 654 mmio_clrsetbits_32(CTL_REG(i, 142), 0xffff << 16, 655 pdram_timing->mr14 << 16); 656 mmio_clrsetbits_32(CTL_REG(i, 145), 0xffff << 16, 657 pdram_timing->mr22 << 16); 658 mmio_clrsetbits_32(CTL_REG(i, 154), 0xffff << 16, 659 pdram_timing->mr12 << 16); 660 mmio_clrsetbits_32(CTL_REG(i, 156), 0xffff << 16, 661 pdram_timing->mr14 << 16); 662 mmio_clrsetbits_32(CTL_REG(i, 159), 0xffff << 16, 663 pdram_timing->mr22 << 16); 664 } 665 mmio_clrsetbits_32(CTL_REG(i, 179), 0xfff << 8, 666 pdram_timing->tzqinit << 8); 667 mmio_write_32(CTL_REG(i, 180), (pdram_timing->tzqcs << 16) | 668 (pdram_timing->tzqinit / 2)); 669 mmio_write_32(CTL_REG(i, 181), (pdram_timing->tzqlat << 16) | 670 pdram_timing->tzqcal); 671 mmio_clrsetbits_32(CTL_REG(i, 212), 0xff << 8, 672 pdram_timing->todton << 8); 673 674 if (timing_config->odt) { 675 mmio_setbits_32(CTL_REG(i, 213), 1 << 16); 676 if (timing_config->freq < 400) 677 tmp = 4 << 24; 678 else 679 tmp = 8 << 24; 680 } else { 681 mmio_clrbits_32(CTL_REG(i, 213), 1 << 16); 682 tmp = 2 << 24; 683 } 684 685 mmio_clrsetbits_32(CTL_REG(i, 216), 0x1f << 24, tmp); 686 mmio_clrsetbits_32(CTL_REG(i, 221), (0x3 << 16) | (0xf << 8), 687 (pdram_timing->tdqsck << 16) | 688 (pdram_timing->tdqsck_max << 8)); 689 tmp = 690 (get_wrlat_adj(timing_config->dram_type, pdram_timing->cwl) 691 << 8) | get_rdlat_adj(timing_config->dram_type, 692 pdram_timing->cl); 693 mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff, tmp); 694 mmio_clrsetbits_32(CTL_REG(i, 82), 0xffff << 16, 695 (4 * pdram_timing->trefi) << 16); 696 697 mmio_clrsetbits_32(CTL_REG(i, 83), 0xffff, 698 (2 * pdram_timing->trefi) & 0xffff); 699 700 if ((timing_config->dram_type == LPDDR3) || 701 (timing_config->dram_type == LPDDR4)) { 702 tmp = get_pi_wrlat(pdram_timing, timing_config); 703 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 704 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 705 } else { 706 tmp = 0; 707 } 708 mmio_clrsetbits_32(CTL_REG(i, 214), 0x3f << 16, 709 (tmp & 0x3f) << 16); 710 711 if ((timing_config->dram_type == LPDDR3) || 712 (timing_config->dram_type == LPDDR4)) { 713 /* min_rl_preamble = cl+TDQSCK_MIN -1 */ 714 tmp = pdram_timing->cl + 715 get_pi_todtoff_min(pdram_timing, timing_config) - 1; 716 /* todtoff_max */ 717 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 718 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 719 } else { 720 tmp = pdram_timing->cl - pdram_timing->cwl; 721 } 722 mmio_clrsetbits_32(CTL_REG(i, 215), 0x3f << 8, 723 (tmp & 0x3f) << 8); 724 725 mmio_clrsetbits_32(CTL_REG(i, 275), 0xff << 16, 726 (get_pi_tdfi_phy_rdlat(pdram_timing, 727 timing_config) & 728 0xff) << 16); 729 730 mmio_clrsetbits_32(CTL_REG(i, 277), 0xffff, 731 (2 * pdram_timing->trefi) & 0xffff); 732 733 mmio_clrsetbits_32(CTL_REG(i, 282), 0xffff, 734 (2 * pdram_timing->trefi) & 0xffff); 735 736 mmio_write_32(CTL_REG(i, 283), 20 * pdram_timing->trefi); 737 738 /* CTL_308 TDFI_CALVL_CAPTURE_F0:RW:16:10 */ 739 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 740 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 741 tmp1++; 742 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 743 mmio_clrsetbits_32(CTL_REG(i, 308), 0x3ff << 16, tmp << 16); 744 745 /* CTL_308 TDFI_CALVL_CC_F0:RW:0:10 */ 746 tmp = tmp + 18; 747 mmio_clrsetbits_32(CTL_REG(i, 308), 0x3ff, tmp); 748 749 /* CTL_314 TDFI_WRCSLAT_F0:RW:8:8 */ 750 tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config); 751 if (timing_config->freq <= ENPER_CS_TRAINING_FREQ) { 752 if (tmp1 == 0) 753 tmp = 0; 754 else if (tmp1 < 5) 755 tmp = tmp1 - 1; 756 else 757 tmp = tmp1 - 5; 758 } else { 759 tmp = tmp1 - 2; 760 } 761 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 8, tmp << 8); 762 763 /* CTL_314 TDFI_RDCSLAT_F0:RW:0:8 */ 764 if ((timing_config->freq <= ENPER_CS_TRAINING_FREQ) && 765 (pdram_timing->cl >= 5)) 766 tmp = pdram_timing->cl - 5; 767 else 768 tmp = pdram_timing->cl - 2; 769 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff, tmp); 770 } 771 } 772 773 static void gen_rk3399_ctl_params_f1(struct timing_related_config 774 *timing_config, 775 struct dram_timing_t *pdram_timing) 776 { 777 uint32_t i; 778 uint32_t tmp, tmp1; 779 780 for (i = 0; i < timing_config->ch_cnt; i++) { 781 if (timing_config->dram_type == DDR3) { 782 tmp = 783 ((700000 + 10) * timing_config->freq + 999) / 1000; 784 tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) + 785 pdram_timing->tmod + pdram_timing->tzqinit; 786 mmio_write_32(CTL_REG(i, 9), tmp); 787 mmio_clrsetbits_32(CTL_REG(i, 22), 0xffff << 16, 788 pdram_timing->tdllk << 16); 789 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, 790 (pdram_timing->tmod << 24) | 791 (pdram_timing->tmrd << 16) | 792 (pdram_timing->trtp << 8)); 793 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16, 794 (pdram_timing->txsr - 795 pdram_timing->trcd) << 16); 796 } else if (timing_config->dram_type == LPDDR4) { 797 mmio_write_32(CTL_REG(i, 9), pdram_timing->tinit1 + 798 pdram_timing->tinit3); 799 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, 800 (pdram_timing->tmrd << 24) | 801 (pdram_timing->tmrd << 16) | 802 (pdram_timing->trtp << 8)); 803 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16, 804 pdram_timing->txsr << 16); 805 } else { 806 mmio_write_32(CTL_REG(i, 9), pdram_timing->tinit1); 807 mmio_write_32(CTL_REG(i, 11), pdram_timing->tinit4); 808 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, 809 (pdram_timing->tmrd << 24) | 810 (pdram_timing->tmrd << 16) | 811 (pdram_timing->trtp << 8)); 812 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16, 813 pdram_timing->txsr << 16); 814 } 815 mmio_write_32(CTL_REG(i, 10), pdram_timing->tinit3); 816 mmio_write_32(CTL_REG(i, 12), pdram_timing->tinit5); 817 mmio_clrsetbits_32(CTL_REG(i, 24), (0x7f << 8), 818 ((pdram_timing->cl * 2) << 8)); 819 mmio_clrsetbits_32(CTL_REG(i, 24), (0x1f << 16), 820 (pdram_timing->cwl << 16)); 821 mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f << 24, 822 pdram_timing->al << 24); 823 mmio_clrsetbits_32(CTL_REG(i, 28), 0xffffff00, 824 (pdram_timing->tras_min << 24) | 825 (pdram_timing->trc << 16) | 826 (pdram_timing->trrd << 8)); 827 mmio_clrsetbits_32(CTL_REG(i, 29), 0xffffff, 828 (pdram_timing->tfaw << 16) | 829 (pdram_timing->trppb << 8) | 830 pdram_timing->twtr); 831 mmio_write_32(CTL_REG(i, 35), (pdram_timing->tcke << 24) | 832 pdram_timing->tras_max); 833 mmio_clrsetbits_32(CTL_REG(i, 36), 0xff, 834 max(1, pdram_timing->tckesr)); 835 mmio_clrsetbits_32(CTL_REG(i, 39), (0xff << 24), 836 (pdram_timing->trcd << 24)); 837 mmio_clrsetbits_32(CTL_REG(i, 40), 0x3f, pdram_timing->twr); 838 mmio_clrsetbits_32(CTL_REG(i, 42), 0x1f << 24, 839 pdram_timing->tmrz << 24); 840 tmp = pdram_timing->tdal ? pdram_timing->tdal : 841 (pdram_timing->twr + pdram_timing->trp); 842 mmio_clrsetbits_32(CTL_REG(i, 44), 0xff << 8, tmp << 8); 843 mmio_clrsetbits_32(CTL_REG(i, 45), 0xff << 8, 844 pdram_timing->trp << 8); 845 mmio_write_32(CTL_REG(i, 49), 846 ((pdram_timing->trefi - 8) << 16) | 847 pdram_timing->trfc); 848 mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff << 16, 849 pdram_timing->txp << 16); 850 mmio_clrsetbits_32(CTL_REG(i, 54), 0xffff, 851 pdram_timing->txpdll); 852 mmio_clrsetbits_32(CTL_REG(i, 55), 0xff << 8, 853 pdram_timing->tmrri << 8); 854 mmio_write_32(CTL_REG(i, 57), (pdram_timing->tmrwckel << 24) | 855 (pdram_timing->tckehcs << 16) | 856 (pdram_timing->tckelcs << 8) | 857 pdram_timing->tcscke); 858 mmio_clrsetbits_32(CTL_REG(i, 58), 0xf, pdram_timing->tzqcke); 859 mmio_clrsetbits_32(CTL_REG(i, 61), 0xffff, pdram_timing->txsnr); 860 mmio_clrsetbits_32(CTL_REG(i, 64), 0xffff << 16, 861 (pdram_timing->tckehcmd << 24) | 862 (pdram_timing->tckelcmd << 16)); 863 mmio_write_32(CTL_REG(i, 65), (pdram_timing->tckelpd << 24) | 864 (pdram_timing->tescke << 16) | 865 (pdram_timing->tsr << 8) | 866 pdram_timing->tckckel); 867 mmio_clrsetbits_32(CTL_REG(i, 66), 0xfff, 868 (pdram_timing->tcmdcke << 8) | 869 pdram_timing->tcsckeh); 870 mmio_clrsetbits_32(CTL_REG(i, 92), (0xff << 24), 871 (pdram_timing->tcksre << 24)); 872 mmio_clrsetbits_32(CTL_REG(i, 93), 0xff, 873 pdram_timing->tcksrx); 874 mmio_clrsetbits_32(CTL_REG(i, 108), (0x1 << 25), 875 (timing_config->dllbp << 25)); 876 mmio_write_32(CTL_REG(i, 125), 877 (pdram_timing->tvrcg_disable << 16) | 878 pdram_timing->tvrcg_enable); 879 mmio_write_32(CTL_REG(i, 126), (pdram_timing->tckfspx << 24) | 880 (pdram_timing->tckfspe << 16) | 881 pdram_timing->tfc_long); 882 mmio_clrsetbits_32(CTL_REG(i, 127), 0xffff, 883 pdram_timing->tvref_long); 884 mmio_clrsetbits_32(CTL_REG(i, 134), 0xffff << 16, 885 pdram_timing->mr[0] << 16); 886 mmio_write_32(CTL_REG(i, 135), (pdram_timing->mr[2] << 16) | 887 pdram_timing->mr[1]); 888 mmio_clrsetbits_32(CTL_REG(i, 138), 0xffff << 16, 889 pdram_timing->mr[3] << 16); 890 mmio_clrsetbits_32(CTL_REG(i, 140), 0xff, pdram_timing->mr11); 891 mmio_clrsetbits_32(CTL_REG(i, 148), 0xffff << 16, 892 pdram_timing->mr[0] << 16); 893 mmio_write_32(CTL_REG(i, 149), (pdram_timing->mr[2] << 16) | 894 pdram_timing->mr[1]); 895 mmio_clrsetbits_32(CTL_REG(i, 152), 0xffff << 16, 896 pdram_timing->mr[3] << 16); 897 mmio_clrsetbits_32(CTL_REG(i, 154), 0xff, pdram_timing->mr11); 898 if (timing_config->dram_type == LPDDR4) { 899 mmio_clrsetbits_32(CTL_REG(i, 141), 0xffff, 900 pdram_timing->mr12); 901 mmio_clrsetbits_32(CTL_REG(i, 143), 0xffff, 902 pdram_timing->mr14); 903 mmio_clrsetbits_32(CTL_REG(i, 146), 0xffff, 904 pdram_timing->mr22); 905 mmio_clrsetbits_32(CTL_REG(i, 155), 0xffff, 906 pdram_timing->mr12); 907 mmio_clrsetbits_32(CTL_REG(i, 157), 0xffff, 908 pdram_timing->mr14); 909 mmio_clrsetbits_32(CTL_REG(i, 160), 0xffff, 910 pdram_timing->mr22); 911 } 912 mmio_write_32(CTL_REG(i, 182), 913 ((pdram_timing->tzqinit / 2) << 16) | 914 pdram_timing->tzqinit); 915 mmio_write_32(CTL_REG(i, 183), (pdram_timing->tzqcal << 16) | 916 pdram_timing->tzqcs); 917 mmio_clrsetbits_32(CTL_REG(i, 184), 0x3f, pdram_timing->tzqlat); 918 mmio_clrsetbits_32(CTL_REG(i, 188), 0xfff, 919 pdram_timing->tzqreset); 920 mmio_clrsetbits_32(CTL_REG(i, 212), 0xff << 16, 921 pdram_timing->todton << 16); 922 923 if (timing_config->odt) { 924 mmio_setbits_32(CTL_REG(i, 213), (1 << 24)); 925 if (timing_config->freq < 400) 926 tmp = 4 << 24; 927 else 928 tmp = 8 << 24; 929 } else { 930 mmio_clrbits_32(CTL_REG(i, 213), (1 << 24)); 931 tmp = 2 << 24; 932 } 933 mmio_clrsetbits_32(CTL_REG(i, 217), 0x1f << 24, tmp); 934 mmio_clrsetbits_32(CTL_REG(i, 221), 0xf << 24, 935 (pdram_timing->tdqsck_max << 24)); 936 mmio_clrsetbits_32(CTL_REG(i, 222), 0x3, pdram_timing->tdqsck); 937 mmio_clrsetbits_32(CTL_REG(i, 291), 0xffff, 938 (get_wrlat_adj(timing_config->dram_type, 939 pdram_timing->cwl) << 8) | 940 get_rdlat_adj(timing_config->dram_type, 941 pdram_timing->cl)); 942 943 mmio_clrsetbits_32(CTL_REG(i, 84), 0xffff, 944 (4 * pdram_timing->trefi) & 0xffff); 945 946 mmio_clrsetbits_32(CTL_REG(i, 84), 0xffff << 16, 947 ((2 * pdram_timing->trefi) & 0xffff) << 16); 948 949 if ((timing_config->dram_type == LPDDR3) || 950 (timing_config->dram_type == LPDDR4)) { 951 tmp = get_pi_wrlat(pdram_timing, timing_config); 952 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 953 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 954 } else { 955 tmp = 0; 956 } 957 mmio_clrsetbits_32(CTL_REG(i, 214), 0x3f << 24, 958 (tmp & 0x3f) << 24); 959 960 if ((timing_config->dram_type == LPDDR3) || 961 (timing_config->dram_type == LPDDR4)) { 962 /* min_rl_preamble = cl + TDQSCK_MIN - 1 */ 963 tmp = pdram_timing->cl + 964 get_pi_todtoff_min(pdram_timing, timing_config); 965 tmp--; 966 /* todtoff_max */ 967 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 968 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 969 } else { 970 tmp = pdram_timing->cl - pdram_timing->cwl; 971 } 972 mmio_clrsetbits_32(CTL_REG(i, 215), 0x3f << 16, 973 (tmp & 0x3f) << 16); 974 975 mmio_clrsetbits_32(CTL_REG(i, 275), 0xff << 24, 976 (get_pi_tdfi_phy_rdlat(pdram_timing, 977 timing_config) & 978 0xff) << 24); 979 980 mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff << 16, 981 ((2 * pdram_timing->trefi) & 0xffff) << 16); 982 983 mmio_clrsetbits_32(CTL_REG(i, 289), 0xffff, 984 (2 * pdram_timing->trefi) & 0xffff); 985 986 mmio_write_32(CTL_REG(i, 290), 20 * pdram_timing->trefi); 987 988 /* CTL_309 TDFI_CALVL_CAPTURE_F1:RW:16:10 */ 989 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 990 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 991 tmp1++; 992 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 993 mmio_clrsetbits_32(CTL_REG(i, 309), 0x3ff << 16, tmp << 16); 994 995 /* CTL_309 TDFI_CALVL_CC_F1:RW:0:10 */ 996 tmp = tmp + 18; 997 mmio_clrsetbits_32(CTL_REG(i, 309), 0x3ff, tmp); 998 999 /* CTL_314 TDFI_WRCSLAT_F1:RW:24:8 */ 1000 tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config); 1001 if (timing_config->freq <= ENPER_CS_TRAINING_FREQ) { 1002 if (tmp1 == 0) 1003 tmp = 0; 1004 else if (tmp1 < 5) 1005 tmp = tmp1 - 1; 1006 else 1007 tmp = tmp1 - 5; 1008 } else { 1009 tmp = tmp1 - 2; 1010 } 1011 1012 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 24, tmp << 24); 1013 1014 /* CTL_314 TDFI_RDCSLAT_F1:RW:16:8 */ 1015 if ((timing_config->freq <= ENPER_CS_TRAINING_FREQ) && 1016 (pdram_timing->cl >= 5)) 1017 tmp = pdram_timing->cl - 5; 1018 else 1019 tmp = pdram_timing->cl - 2; 1020 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 16, tmp << 16); 1021 } 1022 } 1023 1024 static void gen_rk3399_enable_training(uint32_t ch_cnt, uint32_t nmhz) 1025 { 1026 uint32_t i, tmp; 1027 1028 if (nmhz <= PHY_DLL_BYPASS_FREQ) 1029 tmp = 0; 1030 else 1031 tmp = 1; 1032 1033 for (i = 0; i < ch_cnt; i++) { 1034 mmio_clrsetbits_32(CTL_REG(i, 305), 1 << 16, tmp << 16); 1035 mmio_clrsetbits_32(CTL_REG(i, 71), 1, tmp); 1036 } 1037 } 1038 1039 static void gen_rk3399_ctl_params(struct timing_related_config *timing_config, 1040 struct dram_timing_t *pdram_timing, 1041 uint32_t fn) 1042 { 1043 if (fn == 0) 1044 gen_rk3399_ctl_params_f0(timing_config, pdram_timing); 1045 else 1046 gen_rk3399_ctl_params_f1(timing_config, pdram_timing); 1047 } 1048 1049 static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config, 1050 struct dram_timing_t *pdram_timing) 1051 { 1052 uint32_t tmp, tmp1, tmp2; 1053 uint32_t i; 1054 1055 for (i = 0; i < timing_config->ch_cnt; i++) { 1056 /* PI_02 PI_TDFI_PHYMSTR_MAX_F0:RW:0:32 */ 1057 tmp = 4 * pdram_timing->trefi; 1058 mmio_write_32(PI_REG(i, 2), tmp); 1059 /* PI_03 PI_TDFI_PHYMSTR_RESP_F0:RW:0:16 */ 1060 tmp = 2 * pdram_timing->trefi; 1061 mmio_clrsetbits_32(PI_REG(i, 3), 0xffff, tmp); 1062 /* PI_07 PI_TDFI_PHYUPD_RESP_F0:RW:16:16 */ 1063 mmio_clrsetbits_32(PI_REG(i, 7), 0xffff << 16, tmp << 16); 1064 1065 /* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F0:RW:0:8 */ 1066 if (timing_config->dram_type == LPDDR4) 1067 tmp = 2; 1068 else 1069 tmp = 0; 1070 tmp = (pdram_timing->bl / 2) + 4 + 1071 (get_pi_rdlat_adj(pdram_timing) - 2) + tmp + 1072 get_pi_tdfi_phy_rdlat(pdram_timing, timing_config); 1073 mmio_clrsetbits_32(PI_REG(i, 42), 0xff, tmp); 1074 /* PI_43 PI_WRLAT_F0:RW:0:5 */ 1075 if (timing_config->dram_type == LPDDR3) { 1076 tmp = get_pi_wrlat(pdram_timing, timing_config); 1077 mmio_clrsetbits_32(PI_REG(i, 43), 0x1f, tmp); 1078 } 1079 /* PI_43 PI_ADDITIVE_LAT_F0:RW:8:6 */ 1080 mmio_clrsetbits_32(PI_REG(i, 43), 0x3f << 8, 1081 PI_ADD_LATENCY << 8); 1082 1083 /* PI_43 PI_CASLAT_LIN_F0:RW:16:7 */ 1084 mmio_clrsetbits_32(PI_REG(i, 43), 0x7f << 16, 1085 (pdram_timing->cl * 2) << 16); 1086 /* PI_46 PI_TREF_F0:RW:16:16 */ 1087 mmio_clrsetbits_32(PI_REG(i, 46), 0xffff << 16, 1088 pdram_timing->trefi << 16); 1089 /* PI_46 PI_TRFC_F0:RW:0:10 */ 1090 mmio_clrsetbits_32(PI_REG(i, 46), 0x3ff, pdram_timing->trfc); 1091 /* PI_66 PI_TODTL_2CMD_F0:RW:24:8 */ 1092 if (timing_config->dram_type == LPDDR3) { 1093 tmp = get_pi_todtoff_max(pdram_timing, timing_config); 1094 mmio_clrsetbits_32(PI_REG(i, 66), 0xff << 24, 1095 tmp << 24); 1096 } 1097 /* PI_72 PI_WR_TO_ODTH_F0:RW:16:6 */ 1098 if ((timing_config->dram_type == LPDDR3) || 1099 (timing_config->dram_type == LPDDR4)) { 1100 tmp1 = get_pi_wrlat(pdram_timing, timing_config); 1101 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1102 if (tmp1 > tmp2) 1103 tmp = tmp1 - tmp2; 1104 else 1105 tmp = 0; 1106 } else if (timing_config->dram_type == DDR3) { 1107 tmp = 0; 1108 } 1109 mmio_clrsetbits_32(PI_REG(i, 72), 0x3f << 16, tmp << 16); 1110 /* PI_73 PI_RD_TO_ODTH_F0:RW:8:6 */ 1111 if ((timing_config->dram_type == LPDDR3) || 1112 (timing_config->dram_type == LPDDR4)) { 1113 /* min_rl_preamble = cl + TDQSCK_MIN - 1 */ 1114 tmp1 = pdram_timing->cl; 1115 tmp1 += get_pi_todtoff_min(pdram_timing, timing_config); 1116 tmp1--; 1117 /* todtoff_max */ 1118 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1119 if (tmp1 > tmp2) 1120 tmp = tmp1 - tmp2; 1121 else 1122 tmp = 0; 1123 } else if (timing_config->dram_type == DDR3) { 1124 tmp = pdram_timing->cl - pdram_timing->cwl; 1125 } 1126 mmio_clrsetbits_32(PI_REG(i, 73), 0x3f << 8, tmp << 8); 1127 /* PI_89 PI_RDLAT_ADJ_F0:RW:16:8 */ 1128 tmp = get_pi_rdlat_adj(pdram_timing); 1129 mmio_clrsetbits_32(PI_REG(i, 89), 0xff << 16, tmp << 16); 1130 /* PI_90 PI_WRLAT_ADJ_F0:RW:16:8 */ 1131 tmp = get_pi_wrlat_adj(pdram_timing, timing_config); 1132 mmio_clrsetbits_32(PI_REG(i, 90), 0xff << 16, tmp << 16); 1133 /* PI_91 PI_TDFI_WRCSLAT_F0:RW:16:8 */ 1134 tmp1 = tmp; 1135 if (tmp1 == 0) 1136 tmp = 0; 1137 else if (tmp1 < 5) 1138 tmp = tmp1 - 1; 1139 else 1140 tmp = tmp1 - 5; 1141 mmio_clrsetbits_32(PI_REG(i, 91), 0xff << 16, tmp << 16); 1142 /* PI_95 PI_TDFI_CALVL_CAPTURE_F0:RW:16:10 */ 1143 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 1144 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 1145 tmp1++; 1146 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 1147 mmio_clrsetbits_32(PI_REG(i, 95), 0x3ff << 16, tmp << 16); 1148 /* PI_95 PI_TDFI_CALVL_CC_F0:RW:0:10 */ 1149 mmio_clrsetbits_32(PI_REG(i, 95), 0x3ff, tmp + 18); 1150 /* PI_102 PI_TMRZ_F0:RW:8:5 */ 1151 mmio_clrsetbits_32(PI_REG(i, 102), 0x1f << 8, 1152 pdram_timing->tmrz << 8); 1153 /* PI_111 PI_TDFI_CALVL_STROBE_F0:RW:8:4 */ 1154 tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz); 1155 if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0) 1156 tmp1++; 1157 /* pi_tdfi_calvl_strobe=tds_train+5 */ 1158 tmp = tmp1 + 5; 1159 mmio_clrsetbits_32(PI_REG(i, 111), 0xf << 8, tmp << 8); 1160 /* PI_116 PI_TCKEHDQS_F0:RW:16:6 */ 1161 tmp = 10000 / (1000000 / pdram_timing->mhz); 1162 if ((10000 % (1000000 / pdram_timing->mhz)) != 0) 1163 tmp++; 1164 if (pdram_timing->mhz <= 100) 1165 tmp = tmp + 1; 1166 else 1167 tmp = tmp + 8; 1168 mmio_clrsetbits_32(PI_REG(i, 116), 0x3f << 16, tmp << 16); 1169 /* PI_125 PI_MR1_DATA_F0_0:RW+:8:16 */ 1170 mmio_clrsetbits_32(PI_REG(i, 125), 0xffff << 8, 1171 pdram_timing->mr[1] << 8); 1172 /* PI_133 PI_MR1_DATA_F0_1:RW+:0:16 */ 1173 mmio_clrsetbits_32(PI_REG(i, 133), 0xffff, pdram_timing->mr[1]); 1174 /* PI_140 PI_MR1_DATA_F0_2:RW+:16:16 */ 1175 mmio_clrsetbits_32(PI_REG(i, 140), 0xffff << 16, 1176 pdram_timing->mr[1] << 16); 1177 /* PI_148 PI_MR1_DATA_F0_3:RW+:0:16 */ 1178 mmio_clrsetbits_32(PI_REG(i, 148), 0xffff, pdram_timing->mr[1]); 1179 /* PI_126 PI_MR2_DATA_F0_0:RW+:0:16 */ 1180 mmio_clrsetbits_32(PI_REG(i, 126), 0xffff, pdram_timing->mr[2]); 1181 /* PI_133 PI_MR2_DATA_F0_1:RW+:16:16 */ 1182 mmio_clrsetbits_32(PI_REG(i, 133), 0xffff << 16, 1183 pdram_timing->mr[2] << 16); 1184 /* PI_141 PI_MR2_DATA_F0_2:RW+:0:16 */ 1185 mmio_clrsetbits_32(PI_REG(i, 141), 0xffff, pdram_timing->mr[2]); 1186 /* PI_148 PI_MR2_DATA_F0_3:RW+:16:16 */ 1187 mmio_clrsetbits_32(PI_REG(i, 148), 0xffff << 16, 1188 pdram_timing->mr[2] << 16); 1189 /* PI_156 PI_TFC_F0:RW:0:10 */ 1190 mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff, pdram_timing->trfc); 1191 /* PI_158 PI_TWR_F0:RW:24:6 */ 1192 mmio_clrsetbits_32(PI_REG(i, 158), 0x3f << 24, 1193 pdram_timing->twr << 24); 1194 /* PI_158 PI_TWTR_F0:RW:16:6 */ 1195 mmio_clrsetbits_32(PI_REG(i, 158), 0x3f << 16, 1196 pdram_timing->twtr << 16); 1197 /* PI_158 PI_TRCD_F0:RW:8:8 */ 1198 mmio_clrsetbits_32(PI_REG(i, 158), 0xff << 8, 1199 pdram_timing->trcd << 8); 1200 /* PI_158 PI_TRP_F0:RW:0:8 */ 1201 mmio_clrsetbits_32(PI_REG(i, 158), 0xff, pdram_timing->trp); 1202 /* PI_157 PI_TRTP_F0:RW:24:8 */ 1203 mmio_clrsetbits_32(PI_REG(i, 157), 0xff << 24, 1204 pdram_timing->trtp << 24); 1205 /* PI_159 PI_TRAS_MIN_F0:RW:24:8 */ 1206 mmio_clrsetbits_32(PI_REG(i, 159), 0xff << 24, 1207 pdram_timing->tras_min << 24); 1208 /* PI_159 PI_TRAS_MAX_F0:RW:0:17 */ 1209 tmp = pdram_timing->tras_max * 99 / 100; 1210 mmio_clrsetbits_32(PI_REG(i, 159), 0x1ffff, tmp); 1211 /* PI_160 PI_TMRD_F0:RW:16:6 */ 1212 mmio_clrsetbits_32(PI_REG(i, 160), 0x3f << 16, 1213 pdram_timing->tmrd << 16); 1214 /*PI_160 PI_TDQSCK_MAX_F0:RW:0:4 */ 1215 mmio_clrsetbits_32(PI_REG(i, 160), 0xf, 1216 pdram_timing->tdqsck_max); 1217 /* PI_187 PI_TDFI_CTRLUPD_MAX_F0:RW:8:16 */ 1218 mmio_clrsetbits_32(PI_REG(i, 187), 0xffff << 8, 1219 (2 * pdram_timing->trefi) << 8); 1220 /* PI_188 PI_TDFI_CTRLUPD_INTERVAL_F0:RW:0:32 */ 1221 mmio_clrsetbits_32(PI_REG(i, 188), 0xffffffff, 1222 20 * pdram_timing->trefi); 1223 } 1224 } 1225 1226 static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config, 1227 struct dram_timing_t *pdram_timing) 1228 { 1229 uint32_t tmp, tmp1, tmp2; 1230 uint32_t i; 1231 1232 for (i = 0; i < timing_config->ch_cnt; i++) { 1233 /* PI_04 PI_TDFI_PHYMSTR_MAX_F1:RW:0:32 */ 1234 tmp = 4 * pdram_timing->trefi; 1235 mmio_write_32(PI_REG(i, 4), tmp); 1236 /* PI_05 PI_TDFI_PHYMSTR_RESP_F1:RW:0:16 */ 1237 tmp = 2 * pdram_timing->trefi; 1238 mmio_clrsetbits_32(PI_REG(i, 5), 0xffff, tmp); 1239 /* PI_12 PI_TDFI_PHYUPD_RESP_F1:RW:0:16 */ 1240 mmio_clrsetbits_32(PI_REG(i, 12), 0xffff, tmp); 1241 1242 /* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F1:RW:8:8 */ 1243 if (timing_config->dram_type == LPDDR4) 1244 tmp = 2; 1245 else 1246 tmp = 0; 1247 tmp = (pdram_timing->bl / 2) + 4 + 1248 (get_pi_rdlat_adj(pdram_timing) - 2) + tmp + 1249 get_pi_tdfi_phy_rdlat(pdram_timing, timing_config); 1250 mmio_clrsetbits_32(PI_REG(i, 42), 0xff << 8, tmp << 8); 1251 /* PI_43 PI_WRLAT_F1:RW:24:5 */ 1252 if (timing_config->dram_type == LPDDR3) { 1253 tmp = get_pi_wrlat(pdram_timing, timing_config); 1254 mmio_clrsetbits_32(PI_REG(i, 43), 0x1f << 24, 1255 tmp << 24); 1256 } 1257 /* PI_44 PI_ADDITIVE_LAT_F1:RW:0:6 */ 1258 mmio_clrsetbits_32(PI_REG(i, 44), 0x3f, PI_ADD_LATENCY); 1259 /* PI_44 PI_CASLAT_LIN_F1:RW:8:7:=0x18 */ 1260 mmio_clrsetbits_32(PI_REG(i, 44), 0x7f << 8, 1261 pdram_timing->cl * 2); 1262 /* PI_47 PI_TREF_F1:RW:16:16 */ 1263 mmio_clrsetbits_32(PI_REG(i, 47), 0xffff << 16, 1264 pdram_timing->trefi << 16); 1265 /* PI_47 PI_TRFC_F1:RW:0:10 */ 1266 mmio_clrsetbits_32(PI_REG(i, 47), 0x3ff, pdram_timing->trfc); 1267 /* PI_67 PI_TODTL_2CMD_F1:RW:8:8 */ 1268 if (timing_config->dram_type == LPDDR3) { 1269 tmp = get_pi_todtoff_max(pdram_timing, timing_config); 1270 mmio_clrsetbits_32(PI_REG(i, 67), 0xff << 8, tmp << 8); 1271 } 1272 /* PI_72 PI_WR_TO_ODTH_F1:RW:24:6 */ 1273 if ((timing_config->dram_type == LPDDR3) || 1274 (timing_config->dram_type == LPDDR4)) { 1275 tmp1 = get_pi_wrlat(pdram_timing, timing_config); 1276 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1277 if (tmp1 > tmp2) 1278 tmp = tmp1 - tmp2; 1279 else 1280 tmp = 0; 1281 } else if (timing_config->dram_type == DDR3) { 1282 tmp = 0; 1283 } 1284 mmio_clrsetbits_32(PI_REG(i, 72), 0x3f << 24, tmp << 24); 1285 /* PI_73 PI_RD_TO_ODTH_F1:RW:16:6 */ 1286 if ((timing_config->dram_type == LPDDR3) || 1287 (timing_config->dram_type == LPDDR4)) { 1288 /* min_rl_preamble = cl + TDQSCK_MIN - 1 */ 1289 tmp1 = pdram_timing->cl + 1290 get_pi_todtoff_min(pdram_timing, timing_config); 1291 tmp1--; 1292 /* todtoff_max */ 1293 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1294 if (tmp1 > tmp2) 1295 tmp = tmp1 - tmp2; 1296 else 1297 tmp = 0; 1298 } else if (timing_config->dram_type == DDR3) 1299 tmp = pdram_timing->cl - pdram_timing->cwl; 1300 1301 mmio_clrsetbits_32(PI_REG(i, 73), 0x3f << 16, tmp << 16); 1302 /*P I_89 PI_RDLAT_ADJ_F1:RW:24:8 */ 1303 tmp = get_pi_rdlat_adj(pdram_timing); 1304 mmio_clrsetbits_32(PI_REG(i, 89), 0xff << 24, tmp << 24); 1305 /* PI_90 PI_WRLAT_ADJ_F1:RW:24:8 */ 1306 tmp = get_pi_wrlat_adj(pdram_timing, timing_config); 1307 mmio_clrsetbits_32(PI_REG(i, 90), 0xff << 24, tmp << 24); 1308 /* PI_91 PI_TDFI_WRCSLAT_F1:RW:24:8 */ 1309 tmp1 = tmp; 1310 if (tmp1 == 0) 1311 tmp = 0; 1312 else if (tmp1 < 5) 1313 tmp = tmp1 - 1; 1314 else 1315 tmp = tmp1 - 5; 1316 mmio_clrsetbits_32(PI_REG(i, 91), 0xff << 24, tmp << 24); 1317 /*PI_96 PI_TDFI_CALVL_CAPTURE_F1:RW:16:10 */ 1318 /* tadr=20ns */ 1319 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 1320 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 1321 tmp1++; 1322 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 1323 mmio_clrsetbits_32(PI_REG(i, 96), 0x3ff << 16, tmp << 16); 1324 /* PI_96 PI_TDFI_CALVL_CC_F1:RW:0:10 */ 1325 tmp = tmp + 18; 1326 mmio_clrsetbits_32(PI_REG(i, 96), 0x3ff, tmp); 1327 /*PI_103 PI_TMRZ_F1:RW:0:5 */ 1328 mmio_clrsetbits_32(PI_REG(i, 103), 0x1f, pdram_timing->tmrz); 1329 /*PI_111 PI_TDFI_CALVL_STROBE_F1:RW:16:4 */ 1330 /* tds_train=ceil(2/ns) */ 1331 tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz); 1332 if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0) 1333 tmp1++; 1334 /* pi_tdfi_calvl_strobe=tds_train+5 */ 1335 tmp = tmp1 + 5; 1336 mmio_clrsetbits_32(PI_REG(i, 111), 0xf << 16, 1337 tmp << 16); 1338 /* PI_116 PI_TCKEHDQS_F1:RW:24:6 */ 1339 tmp = 10000 / (1000000 / pdram_timing->mhz); 1340 if ((10000 % (1000000 / pdram_timing->mhz)) != 0) 1341 tmp++; 1342 if (pdram_timing->mhz <= 100) 1343 tmp = tmp + 1; 1344 else 1345 tmp = tmp + 8; 1346 mmio_clrsetbits_32(PI_REG(i, 116), 0x3f << 24, 1347 tmp << 24); 1348 /* PI_128 PI_MR1_DATA_F1_0:RW+:0:16 */ 1349 mmio_clrsetbits_32(PI_REG(i, 128), 0xffff, pdram_timing->mr[1]); 1350 /* PI_135 PI_MR1_DATA_F1_1:RW+:8:16 */ 1351 mmio_clrsetbits_32(PI_REG(i, 135), 0xffff << 8, 1352 pdram_timing->mr[1] << 8); 1353 /* PI_143 PI_MR1_DATA_F1_2:RW+:0:16 */ 1354 mmio_clrsetbits_32(PI_REG(i, 143), 0xffff, pdram_timing->mr[1]); 1355 /* PI_150 PI_MR1_DATA_F1_3:RW+:8:16 */ 1356 mmio_clrsetbits_32(PI_REG(i, 150), 0xffff << 8, 1357 pdram_timing->mr[1] << 8); 1358 /* PI_128 PI_MR2_DATA_F1_0:RW+:16:16 */ 1359 mmio_clrsetbits_32(PI_REG(i, 128), 0xffff << 16, 1360 pdram_timing->mr[2] << 16); 1361 /* PI_136 PI_MR2_DATA_F1_1:RW+:0:16 */ 1362 mmio_clrsetbits_32(PI_REG(i, 136), 0xffff, pdram_timing->mr[2]); 1363 /* PI_143 PI_MR2_DATA_F1_2:RW+:16:16 */ 1364 mmio_clrsetbits_32(PI_REG(i, 143), 0xffff << 16, 1365 pdram_timing->mr[2] << 16); 1366 /* PI_151 PI_MR2_DATA_F1_3:RW+:0:16 */ 1367 mmio_clrsetbits_32(PI_REG(i, 151), 0xffff, pdram_timing->mr[2]); 1368 /* PI_156 PI_TFC_F1:RW:16:10 */ 1369 mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff << 16, 1370 pdram_timing->trfc << 16); 1371 /* PI_162 PI_TWR_F1:RW:8:6 */ 1372 mmio_clrsetbits_32(PI_REG(i, 162), 0x3f << 8, 1373 pdram_timing->twr << 8); 1374 /* PI_162 PI_TWTR_F1:RW:0:6 */ 1375 mmio_clrsetbits_32(PI_REG(i, 162), 0x3f, pdram_timing->twtr); 1376 /* PI_161 PI_TRCD_F1:RW:24:8 */ 1377 mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 24, 1378 pdram_timing->trcd << 24); 1379 /* PI_161 PI_TRP_F1:RW:16:8 */ 1380 mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 16, 1381 pdram_timing->trp << 16); 1382 /* PI_161 PI_TRTP_F1:RW:8:8 */ 1383 mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 8, 1384 pdram_timing->trtp << 8); 1385 /* PI_163 PI_TRAS_MIN_F1:RW:24:8 */ 1386 mmio_clrsetbits_32(PI_REG(i, 163), 0xff << 24, 1387 pdram_timing->tras_min << 24); 1388 /* PI_163 PI_TRAS_MAX_F1:RW:0:17 */ 1389 mmio_clrsetbits_32(PI_REG(i, 163), 0x1ffff, 1390 pdram_timing->tras_max * 99 / 100); 1391 /* PI_164 PI_TMRD_F1:RW:16:6 */ 1392 mmio_clrsetbits_32(PI_REG(i, 164), 0x3f << 16, 1393 pdram_timing->tmrd << 16); 1394 /* PI_164 PI_TDQSCK_MAX_F1:RW:0:4 */ 1395 mmio_clrsetbits_32(PI_REG(i, 164), 0xf, 1396 pdram_timing->tdqsck_max); 1397 /* PI_189 PI_TDFI_CTRLUPD_MAX_F1:RW:0:16 */ 1398 mmio_clrsetbits_32(PI_REG(i, 189), 0xffff, 1399 2 * pdram_timing->trefi); 1400 /* PI_190 PI_TDFI_CTRLUPD_INTERVAL_F1:RW:0:32 */ 1401 mmio_clrsetbits_32(PI_REG(i, 190), 0xffffffff, 1402 20 * pdram_timing->trefi); 1403 } 1404 } 1405 1406 static void gen_rk3399_pi_params(struct timing_related_config *timing_config, 1407 struct dram_timing_t *pdram_timing, 1408 uint32_t fn) 1409 { 1410 if (fn == 0) 1411 gen_rk3399_pi_params_f0(timing_config, pdram_timing); 1412 else 1413 gen_rk3399_pi_params_f1(timing_config, pdram_timing); 1414 } 1415 1416 static void gen_rk3399_set_odt(uint32_t odt_en) 1417 { 1418 uint32_t drv_odt_val; 1419 uint32_t i; 1420 1421 for (i = 0; i < rk3399_dram_status.timing_config.ch_cnt; i++) { 1422 drv_odt_val = (odt_en | (0 << 1) | (0 << 2)) << 16; 1423 mmio_clrsetbits_32(PHY_REG(i, 5), 0x7 << 16, drv_odt_val); 1424 mmio_clrsetbits_32(PHY_REG(i, 133), 0x7 << 16, drv_odt_val); 1425 mmio_clrsetbits_32(PHY_REG(i, 261), 0x7 << 16, drv_odt_val); 1426 mmio_clrsetbits_32(PHY_REG(i, 389), 0x7 << 16, drv_odt_val); 1427 drv_odt_val = (odt_en | (0 << 1) | (0 << 2)) << 24; 1428 mmio_clrsetbits_32(PHY_REG(i, 6), 0x7 << 24, drv_odt_val); 1429 mmio_clrsetbits_32(PHY_REG(i, 134), 0x7 << 24, drv_odt_val); 1430 mmio_clrsetbits_32(PHY_REG(i, 262), 0x7 << 24, drv_odt_val); 1431 mmio_clrsetbits_32(PHY_REG(i, 390), 0x7 << 24, drv_odt_val); 1432 } 1433 } 1434 1435 static void gen_rk3399_phy_dll_bypass(uint32_t mhz, uint32_t ch, 1436 uint32_t index, uint32_t dram_type) 1437 { 1438 uint32_t sw_master_mode = 0; 1439 uint32_t rddqs_gate_delay, rddqs_latency, total_delay; 1440 uint32_t i; 1441 1442 if (dram_type == DDR3) 1443 total_delay = PI_PAD_DELAY_PS_VALUE; 1444 else if (dram_type == LPDDR3) 1445 total_delay = PI_PAD_DELAY_PS_VALUE + 2500; 1446 else 1447 total_delay = PI_PAD_DELAY_PS_VALUE + 1500; 1448 /* total_delay + 0.55tck */ 1449 total_delay += (55 * 10000)/mhz; 1450 rddqs_latency = total_delay * mhz / 1000000; 1451 total_delay -= rddqs_latency * 1000000 / mhz; 1452 rddqs_gate_delay = total_delay * 0x200 * mhz / 1000000; 1453 if (mhz <= PHY_DLL_BYPASS_FREQ) { 1454 sw_master_mode = 0xc; 1455 mmio_setbits_32(PHY_REG(ch, 514), 1); 1456 mmio_setbits_32(PHY_REG(ch, 642), 1); 1457 mmio_setbits_32(PHY_REG(ch, 770), 1); 1458 1459 /* setting bypass mode slave delay */ 1460 for (i = 0; i < 4; i++) { 1461 /* wr dq delay = -180deg + (0x60 / 4) * 20ps */ 1462 mmio_clrsetbits_32(PHY_REG(ch, 1 + 128 * i), 0x7ff << 8, 1463 0x4a0 << 8); 1464 /* rd dqs/dq delay = (0x60 / 4) * 20ps */ 1465 mmio_clrsetbits_32(PHY_REG(ch, 11 + 128 * i), 0x3ff, 1466 0xa0); 1467 /* rd rddqs_gate delay */ 1468 mmio_clrsetbits_32(PHY_REG(ch, 2 + 128 * i), 0x3ff, 1469 rddqs_gate_delay); 1470 mmio_clrsetbits_32(PHY_REG(ch, 78 + 128 * i), 0xf, 1471 rddqs_latency); 1472 } 1473 for (i = 0; i < 3; i++) 1474 /* adr delay */ 1475 mmio_clrsetbits_32(PHY_REG(ch, 513 + 128 * i), 1476 0x7ff << 16, 0x80 << 16); 1477 1478 if ((mmio_read_32(PHY_REG(ch, 86)) & 0xc00) == 0) { 1479 /* 1480 * old status is normal mode, 1481 * and saving the wrdqs slave delay 1482 */ 1483 for (i = 0; i < 4; i++) { 1484 /* save and clear wr dqs slave delay */ 1485 wrdqs_delay_val[ch][index][i] = 0x3ff & 1486 (mmio_read_32(PHY_REG(ch, 63 + i * 128)) 1487 >> 16); 1488 mmio_clrsetbits_32(PHY_REG(ch, 63 + i * 128), 1489 0x03ff << 16, 0 << 16); 1490 /* 1491 * in normal mode the cmd may delay 1cycle by 1492 * wrlvl and in bypass mode making dqs also 1493 * delay 1cycle. 1494 */ 1495 mmio_clrsetbits_32(PHY_REG(ch, 78 + i * 128), 1496 0x07 << 8, 0x1 << 8); 1497 } 1498 } 1499 } else if (mmio_read_32(PHY_REG(ch, 86)) & 0xc00) { 1500 /* old status is bypass mode and restore wrlvl resume */ 1501 for (i = 0; i < 4; i++) { 1502 mmio_clrsetbits_32(PHY_REG(ch, 63 + i * 128), 1503 0x03ff << 16, 1504 (wrdqs_delay_val[ch][index][i] & 1505 0x3ff) << 16); 1506 /* resume phy_write_path_lat_add */ 1507 mmio_clrbits_32(PHY_REG(ch, 78 + i * 128), 0x07 << 8); 1508 } 1509 } 1510 1511 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ 1512 mmio_clrsetbits_32(PHY_REG(ch, 86), 0xf << 8, sw_master_mode << 8); 1513 mmio_clrsetbits_32(PHY_REG(ch, 214), 0xf << 8, sw_master_mode << 8); 1514 mmio_clrsetbits_32(PHY_REG(ch, 342), 0xf << 8, sw_master_mode << 8); 1515 mmio_clrsetbits_32(PHY_REG(ch, 470), 0xf << 8, sw_master_mode << 8); 1516 1517 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ 1518 mmio_clrsetbits_32(PHY_REG(ch, 547), 0xf << 16, sw_master_mode << 16); 1519 mmio_clrsetbits_32(PHY_REG(ch, 675), 0xf << 16, sw_master_mode << 16); 1520 mmio_clrsetbits_32(PHY_REG(ch, 803), 0xf << 16, sw_master_mode << 16); 1521 } 1522 1523 static void gen_rk3399_phy_params(struct timing_related_config *timing_config, 1524 struct drv_odt_lp_config *drv_config, 1525 struct dram_timing_t *pdram_timing, 1526 uint32_t fn) 1527 { 1528 uint32_t tmp, i, div, j; 1529 uint32_t mem_delay_ps, pad_delay_ps, total_delay_ps, delay_frac_ps; 1530 uint32_t trpre_min_ps, gate_delay_ps, gate_delay_frac_ps; 1531 uint32_t ie_enable, tsel_enable, cas_lat, rddata_en_ie_dly, tsel_adder; 1532 uint32_t extra_adder, delta, hs_offset; 1533 1534 for (i = 0; i < timing_config->ch_cnt; i++) { 1535 1536 pad_delay_ps = PI_PAD_DELAY_PS_VALUE; 1537 ie_enable = PI_IE_ENABLE_VALUE; 1538 tsel_enable = PI_TSEL_ENABLE_VALUE; 1539 1540 mmio_clrsetbits_32(PHY_REG(i, 896), (0x3 << 8) | 1, fn << 8); 1541 1542 /* PHY_LOW_FREQ_SEL */ 1543 /* DENALI_PHY_913 1bit offset_0 */ 1544 if (timing_config->freq > 400) 1545 mmio_clrbits_32(PHY_REG(i, 913), 1); 1546 else 1547 mmio_setbits_32(PHY_REG(i, 913), 1); 1548 1549 /* PHY_RPTR_UPDATE_x */ 1550 /* DENALI_PHY_87/215/343/471 4bit offset_16 */ 1551 tmp = 2500 / (1000000 / pdram_timing->mhz) + 3; 1552 if ((2500 % (1000000 / pdram_timing->mhz)) != 0) 1553 tmp++; 1554 mmio_clrsetbits_32(PHY_REG(i, 87), 0xf << 16, tmp << 16); 1555 mmio_clrsetbits_32(PHY_REG(i, 215), 0xf << 16, tmp << 16); 1556 mmio_clrsetbits_32(PHY_REG(i, 343), 0xf << 16, tmp << 16); 1557 mmio_clrsetbits_32(PHY_REG(i, 471), 0xf << 16, tmp << 16); 1558 1559 /* PHY_PLL_CTRL */ 1560 /* DENALI_PHY_911 13bits offset_0 */ 1561 /* PHY_LP4_BOOT_PLL_CTRL */ 1562 /* DENALI_PHY_919 13bits offset_0 */ 1563 if (pdram_timing->mhz <= 150) 1564 tmp = 3; 1565 else if (pdram_timing->mhz <= 300) 1566 tmp = 2; 1567 else if (pdram_timing->mhz <= 600) 1568 tmp = 1; 1569 else 1570 tmp = 0; 1571 tmp = (1 << 12) | (tmp << 9) | (2 << 7) | (1 << 1); 1572 mmio_clrsetbits_32(PHY_REG(i, 911), 0x1fff, tmp); 1573 mmio_clrsetbits_32(PHY_REG(i, 919), 0x1fff, tmp); 1574 1575 /* PHY_PLL_CTRL_CA */ 1576 /* DENALI_PHY_911 13bits offset_16 */ 1577 /* PHY_LP4_BOOT_PLL_CTRL_CA */ 1578 /* DENALI_PHY_919 13bits offset_16 */ 1579 if (pdram_timing->mhz <= 150) 1580 tmp = 3; 1581 else if (pdram_timing->mhz <= 300) 1582 tmp = 2; 1583 else if (pdram_timing->mhz <= 600) 1584 tmp = 1; 1585 else 1586 tmp = 0; 1587 tmp = (tmp << 9) | (2 << 7) | (1 << 5) | (1 << 1); 1588 mmio_clrsetbits_32(PHY_REG(i, 911), 0x1fff << 16, tmp << 16); 1589 mmio_clrsetbits_32(PHY_REG(i, 919), 0x1fff << 16, tmp << 16); 1590 1591 /* PHY_TCKSRE_WAIT */ 1592 /* DENALI_PHY_922 4bits offset_24 */ 1593 if (pdram_timing->mhz <= 400) 1594 tmp = 1; 1595 else if (pdram_timing->mhz <= 800) 1596 tmp = 3; 1597 else if (pdram_timing->mhz <= 1000) 1598 tmp = 4; 1599 else 1600 tmp = 5; 1601 mmio_clrsetbits_32(PHY_REG(i, 922), 0xf << 24, tmp << 24); 1602 /* PHY_CAL_CLK_SELECT_0:RW8:3 */ 1603 div = pdram_timing->mhz / (2 * 20); 1604 for (j = 2, tmp = 1; j <= 128; j <<= 1, tmp++) { 1605 if (div < j) 1606 break; 1607 } 1608 mmio_clrsetbits_32(PHY_REG(i, 947), 0x7 << 8, tmp << 8); 1609 mmio_setbits_32(PHY_REG(i, 927), (1 << 22)); 1610 1611 if (timing_config->dram_type == DDR3) { 1612 mem_delay_ps = 0; 1613 trpre_min_ps = 1000; 1614 } else if (timing_config->dram_type == LPDDR4) { 1615 mem_delay_ps = 1500; 1616 trpre_min_ps = 900; 1617 } else if (timing_config->dram_type == LPDDR3) { 1618 mem_delay_ps = 2500; 1619 trpre_min_ps = 900; 1620 } else { 1621 ERROR("gen_rk3399_phy_params:dramtype unsupport\n"); 1622 return; 1623 } 1624 total_delay_ps = mem_delay_ps + pad_delay_ps; 1625 delay_frac_ps = 1000 * total_delay_ps / 1626 (1000000 / pdram_timing->mhz); 1627 gate_delay_ps = delay_frac_ps + 1000 - (trpre_min_ps / 2); 1628 gate_delay_frac_ps = gate_delay_ps % 1000; 1629 tmp = gate_delay_frac_ps * 0x200 / 1000; 1630 /* PHY_RDDQS_GATE_SLAVE_DELAY */ 1631 /* DENALI_PHY_77/205/333/461 10bits offset_16 */ 1632 mmio_clrsetbits_32(PHY_REG(i, 77), 0x2ff << 16, tmp << 16); 1633 mmio_clrsetbits_32(PHY_REG(i, 205), 0x2ff << 16, tmp << 16); 1634 mmio_clrsetbits_32(PHY_REG(i, 333), 0x2ff << 16, tmp << 16); 1635 mmio_clrsetbits_32(PHY_REG(i, 461), 0x2ff << 16, tmp << 16); 1636 1637 tmp = gate_delay_ps / 1000; 1638 /* PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST */ 1639 /* DENALI_PHY_10/138/266/394 4bit offset_0 */ 1640 mmio_clrsetbits_32(PHY_REG(i, 10), 0xf, tmp); 1641 mmio_clrsetbits_32(PHY_REG(i, 138), 0xf, tmp); 1642 mmio_clrsetbits_32(PHY_REG(i, 266), 0xf, tmp); 1643 mmio_clrsetbits_32(PHY_REG(i, 394), 0xf, tmp); 1644 /* PHY_GTLVL_LAT_ADJ_START */ 1645 /* DENALI_PHY_80/208/336/464 4bits offset_16 */ 1646 tmp = delay_frac_ps / 1000; 1647 mmio_clrsetbits_32(PHY_REG(i, 80), 0xf << 16, tmp << 16); 1648 mmio_clrsetbits_32(PHY_REG(i, 208), 0xf << 16, tmp << 16); 1649 mmio_clrsetbits_32(PHY_REG(i, 336), 0xf << 16, tmp << 16); 1650 mmio_clrsetbits_32(PHY_REG(i, 464), 0xf << 16, tmp << 16); 1651 1652 cas_lat = pdram_timing->cl + PI_ADD_LATENCY; 1653 rddata_en_ie_dly = ie_enable / (1000000 / pdram_timing->mhz); 1654 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 1655 rddata_en_ie_dly++; 1656 rddata_en_ie_dly = rddata_en_ie_dly - 1; 1657 tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz); 1658 if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0) 1659 tsel_adder++; 1660 if (rddata_en_ie_dly > tsel_adder) 1661 extra_adder = rddata_en_ie_dly - tsel_adder; 1662 else 1663 extra_adder = 0; 1664 delta = cas_lat - rddata_en_ie_dly; 1665 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 1666 hs_offset = 2; 1667 else 1668 hs_offset = 1; 1669 if (rddata_en_ie_dly > (cas_lat - 1 - hs_offset)) 1670 tmp = 0; 1671 else if ((delta == 2) || (delta == 1)) 1672 tmp = rddata_en_ie_dly - 0 - extra_adder; 1673 else 1674 tmp = extra_adder; 1675 /* PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY */ 1676 /* DENALI_PHY_9/137/265/393 4bit offset_16 */ 1677 mmio_clrsetbits_32(PHY_REG(i, 9), 0xf << 16, tmp << 16); 1678 mmio_clrsetbits_32(PHY_REG(i, 137), 0xf << 16, tmp << 16); 1679 mmio_clrsetbits_32(PHY_REG(i, 265), 0xf << 16, tmp << 16); 1680 mmio_clrsetbits_32(PHY_REG(i, 393), 0xf << 16, tmp << 16); 1681 /* PHY_RDDATA_EN_TSEL_DLY */ 1682 /* DENALI_PHY_86/214/342/470 4bit offset_0 */ 1683 mmio_clrsetbits_32(PHY_REG(i, 86), 0xf, tmp); 1684 mmio_clrsetbits_32(PHY_REG(i, 214), 0xf, tmp); 1685 mmio_clrsetbits_32(PHY_REG(i, 342), 0xf, tmp); 1686 mmio_clrsetbits_32(PHY_REG(i, 470), 0xf, tmp); 1687 1688 if (tsel_adder > rddata_en_ie_dly) 1689 extra_adder = tsel_adder - rddata_en_ie_dly; 1690 else 1691 extra_adder = 0; 1692 if (rddata_en_ie_dly > (cas_lat - 1 - hs_offset)) 1693 tmp = tsel_adder; 1694 else 1695 tmp = rddata_en_ie_dly - 0 + extra_adder; 1696 /* PHY_LP4_BOOT_RDDATA_EN_DLY */ 1697 /* DENALI_PHY_9/137/265/393 4bit offset_8 */ 1698 mmio_clrsetbits_32(PHY_REG(i, 9), 0xf << 8, tmp << 8); 1699 mmio_clrsetbits_32(PHY_REG(i, 137), 0xf << 8, tmp << 8); 1700 mmio_clrsetbits_32(PHY_REG(i, 265), 0xf << 8, tmp << 8); 1701 mmio_clrsetbits_32(PHY_REG(i, 393), 0xf << 8, tmp << 8); 1702 /* PHY_RDDATA_EN_DLY */ 1703 /* DENALI_PHY_85/213/341/469 4bit offset_24 */ 1704 mmio_clrsetbits_32(PHY_REG(i, 85), 0xf << 24, tmp << 24); 1705 mmio_clrsetbits_32(PHY_REG(i, 213), 0xf << 24, tmp << 24); 1706 mmio_clrsetbits_32(PHY_REG(i, 341), 0xf << 24, tmp << 24); 1707 mmio_clrsetbits_32(PHY_REG(i, 469), 0xf << 24, tmp << 24); 1708 1709 if (pdram_timing->mhz <= ENPER_CS_TRAINING_FREQ) { 1710 /* 1711 * Note:Per-CS Training is not compatible at speeds 1712 * under 533 MHz. If the PHY is running at a speed 1713 * less than 533MHz, all phy_per_cs_training_en_X 1714 * parameters must be cleared to 0. 1715 */ 1716 1717 /*DENALI_PHY_84/212/340/468 1bit offset_16 */ 1718 mmio_clrbits_32(PHY_REG(i, 84), 0x1 << 16); 1719 mmio_clrbits_32(PHY_REG(i, 212), 0x1 << 16); 1720 mmio_clrbits_32(PHY_REG(i, 340), 0x1 << 16); 1721 mmio_clrbits_32(PHY_REG(i, 468), 0x1 << 16); 1722 } else { 1723 mmio_setbits_32(PHY_REG(i, 84), 0x1 << 16); 1724 mmio_setbits_32(PHY_REG(i, 212), 0x1 << 16); 1725 mmio_setbits_32(PHY_REG(i, 340), 0x1 << 16); 1726 mmio_setbits_32(PHY_REG(i, 468), 0x1 << 16); 1727 } 1728 gen_rk3399_phy_dll_bypass(pdram_timing->mhz, i, fn, 1729 timing_config->dram_type); 1730 } 1731 } 1732 1733 static int to_get_clk_index(unsigned int mhz) 1734 { 1735 int pll_cnt, i; 1736 1737 pll_cnt = ARRAY_SIZE(dpll_rates_table); 1738 1739 /* Assumming rate_table is in descending order */ 1740 for (i = 0; i < pll_cnt; i++) { 1741 if (mhz >= dpll_rates_table[i].mhz) 1742 break; 1743 } 1744 1745 /* if mhz lower than lowest frequency in table, use lowest frequency */ 1746 if (i == pll_cnt) 1747 i = pll_cnt - 1; 1748 1749 return i; 1750 } 1751 1752 uint32_t rkclk_prepare_pll_timing(unsigned int mhz) 1753 { 1754 unsigned int refdiv, postdiv1, fbdiv, postdiv2; 1755 int index; 1756 1757 index = to_get_clk_index(mhz); 1758 refdiv = dpll_rates_table[index].refdiv; 1759 fbdiv = dpll_rates_table[index].fbdiv; 1760 postdiv1 = dpll_rates_table[index].postdiv1; 1761 postdiv2 = dpll_rates_table[index].postdiv2; 1762 mmio_write_32(DCF_PARAM_ADDR + PARAM_DPLL_CON0, FBDIV(fbdiv)); 1763 mmio_write_32(DCF_PARAM_ADDR + PARAM_DPLL_CON1, 1764 POSTDIV2(postdiv2) | POSTDIV1(postdiv1) | REFDIV(refdiv)); 1765 return (24 * fbdiv) / refdiv / postdiv1 / postdiv2; 1766 } 1767 1768 uint32_t ddr_get_rate(void) 1769 { 1770 uint32_t refdiv, postdiv1, fbdiv, postdiv2; 1771 1772 refdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) & 0x3f; 1773 fbdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 0)) & 0xfff; 1774 postdiv1 = 1775 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 8) & 0x7; 1776 postdiv2 = 1777 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 12) & 0x7; 1778 1779 return (24 / refdiv * fbdiv / postdiv1 / postdiv2) * 1000 * 1000; 1780 } 1781 1782 /* 1783 * return: bit12: channel 1, external self-refresh 1784 * bit11: channel 1, stdby_mode 1785 * bit10: channel 1, self-refresh with controller and memory clock gate 1786 * bit9: channel 1, self-refresh 1787 * bit8: channel 1, power-down 1788 * 1789 * bit4: channel 1, external self-refresh 1790 * bit3: channel 0, stdby_mode 1791 * bit2: channel 0, self-refresh with controller and memory clock gate 1792 * bit1: channel 0, self-refresh 1793 * bit0: channel 0, power-down 1794 */ 1795 uint32_t exit_low_power(void) 1796 { 1797 uint32_t low_power = 0; 1798 uint32_t channel_mask; 1799 uint32_t tmp, i; 1800 1801 channel_mask = (mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & 1802 0x3; 1803 for (i = 0; i < 2; i++) { 1804 if (!(channel_mask & (1 << i))) 1805 continue; 1806 1807 /* exit stdby mode */ 1808 mmio_write_32(CIC_BASE + CIC_CTRL1, 1809 (1 << (i + 16)) | (0 << i)); 1810 /* exit external self-refresh */ 1811 tmp = i ? 12 : 8; 1812 low_power |= ((mmio_read_32(PMU_BASE + PMU_SFT_CON) >> tmp) & 1813 0x1) << (4 + 8 * i); 1814 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, 1 << tmp); 1815 while (!(mmio_read_32(PMU_BASE + PMU_DDR_SREF_ST) & (1 << i))) 1816 ; 1817 /* exit auto low-power */ 1818 mmio_clrbits_32(CTL_REG(i, 101), 0x7); 1819 /* lp_cmd to exit */ 1820 if (((mmio_read_32(CTL_REG(i, 100)) >> 24) & 0x7f) != 1821 0x40) { 1822 while (mmio_read_32(CTL_REG(i, 200)) & 0x1) 1823 ; 1824 mmio_clrsetbits_32(CTL_REG(i, 93), 0xff << 24, 1825 0x69 << 24); 1826 while (((mmio_read_32(CTL_REG(i, 100)) >> 24) & 0x7f) != 1827 0x40) 1828 ; 1829 } 1830 } 1831 return low_power; 1832 } 1833 1834 void resume_low_power(uint32_t low_power) 1835 { 1836 uint32_t channel_mask; 1837 uint32_t tmp, i, val; 1838 1839 channel_mask = (mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & 1840 0x3; 1841 for (i = 0; i < 2; i++) { 1842 if (!(channel_mask & (1 << i))) 1843 continue; 1844 1845 /* resume external self-refresh */ 1846 tmp = i ? 12 : 8; 1847 val = (low_power >> (4 + 8 * i)) & 0x1; 1848 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, val << tmp); 1849 /* resume auto low-power */ 1850 val = (low_power >> (8 * i)) & 0x7; 1851 mmio_setbits_32(CTL_REG(i, 101), val); 1852 /* resume stdby mode */ 1853 val = (low_power >> (3 + 8 * i)) & 0x1; 1854 mmio_write_32(CIC_BASE + CIC_CTRL1, 1855 (1 << (i + 16)) | (val << i)); 1856 } 1857 } 1858 1859 static void wait_dcf_done(void) 1860 { 1861 while ((mmio_read_32(DCF_BASE + DCF_DCF_ISR) & (DCF_DONE)) == 0) 1862 continue; 1863 } 1864 1865 void clr_dcf_irq(void) 1866 { 1867 /* clear dcf irq status */ 1868 mmio_write_32(DCF_BASE + DCF_DCF_ISR, DCF_TIMEOUT | DCF_ERR | DCF_DONE); 1869 } 1870 1871 static void enable_dcf(uint32_t dcf_addr) 1872 { 1873 /* config DCF start addr */ 1874 mmio_write_32(DCF_BASE + DCF_DCF_ADDR, dcf_addr); 1875 /* wait dcf done */ 1876 while (mmio_read_32(DCF_BASE + DCF_DCF_CTRL) & 1) 1877 continue; 1878 /* clear dcf irq status */ 1879 mmio_write_32(DCF_BASE + DCF_DCF_ISR, DCF_TIMEOUT | DCF_ERR | DCF_DONE); 1880 /* DCF start */ 1881 mmio_setbits_32(DCF_BASE + DCF_DCF_CTRL, DCF_START); 1882 } 1883 1884 static void dcf_start(uint32_t freq, uint32_t index) 1885 { 1886 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 1887 (0x1 << (1 + 16)) | (1 << 1)); 1888 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(11), 1889 (0x1 << (0 + 16)) | (1 << 0)); 1890 mmio_write_32(DCF_PARAM_ADDR + PARAM_FREQ_SELECT, index << 4); 1891 1892 mmio_write_32(DCF_PARAM_ADDR + PARAM_DRAM_FREQ, freq); 1893 1894 rkclk_prepare_pll_timing(freq); 1895 udelay(10); 1896 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), 1897 (0x1 << (1 + 16)) | (0 << 1)); 1898 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(11), 1899 (0x1 << (0 + 16)) | (0 << 0)); 1900 udelay(10); 1901 enable_dcf(DCF_START_ADDR); 1902 } 1903 1904 static void dram_low_power_config(void) 1905 { 1906 uint32_t tmp, i; 1907 uint32_t ch_cnt = rk3399_dram_status.timing_config.ch_cnt; 1908 uint32_t dram_type = rk3399_dram_status.timing_config.dram_type; 1909 1910 if (dram_type == DDR3) 1911 tmp = (2 << 16) | (0x7 << 8); 1912 else 1913 tmp = (3 << 16) | (0x7 << 8); 1914 1915 for (i = 0; i < ch_cnt; i++) 1916 mmio_clrsetbits_32(CTL_REG(i, 101), 0x70f0f, tmp); 1917 1918 /* standby idle */ 1919 mmio_write_32(CIC_BASE + CIC_CG_WAIT_TH, 0x640008); 1920 1921 if (ch_cnt == 2) { 1922 mmio_write_32(GRF_BASE + GRF_DDRC1_CON1, 1923 (((0x1<<4) | (0x1<<5) | (0x1<<6) | 1924 (0x1<<7)) << 16) | 1925 ((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7))); 1926 mmio_write_32(CIC_BASE + CIC_CTRL1, 0x002a0028); 1927 } 1928 1929 mmio_write_32(GRF_BASE + GRF_DDRC0_CON1, 1930 (((0x1<<4) | (0x1<<5) | (0x1<<6) | (0x1<<7)) << 16) | 1931 ((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7))); 1932 mmio_write_32(CIC_BASE + CIC_CTRL1, 0x00150014); 1933 } 1934 1935 void dram_dfs_init(void) 1936 { 1937 uint32_t trefi0, trefi1; 1938 1939 /* get sdram config for os reg */ 1940 get_dram_drv_odt_val(sdram_config.dramtype, 1941 &rk3399_dram_status.drv_odt_lp_cfg); 1942 sdram_timing_cfg_init(&rk3399_dram_status.timing_config, 1943 &sdram_config, 1944 &rk3399_dram_status.drv_odt_lp_cfg); 1945 1946 trefi0 = ((mmio_read_32(CTL_REG(0, 48)) >> 16) & 0xffff) + 8; 1947 trefi1 = ((mmio_read_32(CTL_REG(0, 49)) >> 16) & 0xffff) + 8; 1948 1949 rk3399_dram_status.index_freq[0] = trefi0 * 10 / 39; 1950 rk3399_dram_status.index_freq[1] = trefi1 * 10 / 39; 1951 rk3399_dram_status.current_index = 1952 (mmio_read_32(CTL_REG(0, 111)) >> 16) & 0x3; 1953 if (rk3399_dram_status.timing_config.dram_type == DDR3) { 1954 rk3399_dram_status.index_freq[0] /= 2; 1955 rk3399_dram_status.index_freq[1] /= 2; 1956 } 1957 rk3399_dram_status.index_freq[(rk3399_dram_status.current_index + 1) 1958 & 0x1] = 0; 1959 dram_low_power_config(); 1960 } 1961 1962 /* 1963 * arg0: bit0-7: sr_idle; bit8-15:sr_mc_gate_idle; bit16-31: standby idle 1964 * arg1: bit0-11: pd_idle; bit 16-27: srpd_lite_idle 1965 * arg2: bit0: if odt en 1966 */ 1967 uint32_t dram_set_odt_pd(uint32_t arg0, uint32_t arg1, uint32_t arg2) 1968 { 1969 struct drv_odt_lp_config *lp_cfg = &rk3399_dram_status.drv_odt_lp_cfg; 1970 uint32_t *low_power = &rk3399_dram_status.low_power_stat; 1971 uint32_t dram_type, ch_count, pd_tmp, sr_tmp, i; 1972 1973 dram_type = rk3399_dram_status.timing_config.dram_type; 1974 ch_count = rk3399_dram_status.timing_config.ch_cnt; 1975 1976 lp_cfg->sr_idle = arg0 & 0xff; 1977 lp_cfg->sr_mc_gate_idle = (arg0 >> 8) & 0xff; 1978 lp_cfg->standby_idle = (arg0 >> 16) & 0xffff; 1979 lp_cfg->pd_idle = arg1 & 0xfff; 1980 lp_cfg->srpd_lite_idle = (arg1 >> 16) & 0xfff; 1981 1982 rk3399_dram_status.timing_config.odt = arg2 & 0x1; 1983 1984 exit_low_power(); 1985 1986 *low_power = 0; 1987 1988 /* pd_idle en */ 1989 if (lp_cfg->pd_idle) 1990 *low_power |= ((1 << 0) | (1 << 8)); 1991 /* sr_idle en srpd_lite_idle */ 1992 if (lp_cfg->sr_idle | lp_cfg->srpd_lite_idle) 1993 *low_power |= ((1 << 1) | (1 << 9)); 1994 /* sr_mc_gate_idle */ 1995 if (lp_cfg->sr_mc_gate_idle) 1996 *low_power |= ((1 << 2) | (1 << 10)); 1997 /* standbyidle */ 1998 if (lp_cfg->standby_idle) { 1999 if (rk3399_dram_status.timing_config.ch_cnt == 2) 2000 *low_power |= ((1 << 3) | (1 << 11)); 2001 else 2002 *low_power |= (1 << 3); 2003 } 2004 2005 pd_tmp = arg1; 2006 if (dram_type != LPDDR4) 2007 pd_tmp = arg1 & 0xfff; 2008 sr_tmp = arg0 & 0xffff; 2009 for (i = 0; i < ch_count; i++) { 2010 mmio_write_32(CTL_REG(i, 102), pd_tmp); 2011 mmio_clrsetbits_32(CTL_REG(i, 103), 0xffff, sr_tmp); 2012 } 2013 mmio_write_32(CIC_BASE + CIC_IDLE_TH, (arg0 >> 16) & 0xffff); 2014 2015 return 0; 2016 } 2017 2018 static uint32_t prepare_ddr_timing(uint32_t mhz) 2019 { 2020 uint32_t index; 2021 struct dram_timing_t dram_timing; 2022 2023 rk3399_dram_status.timing_config.freq = mhz; 2024 2025 if (mhz < 300) 2026 rk3399_dram_status.timing_config.dllbp = 1; 2027 else 2028 rk3399_dram_status.timing_config.dllbp = 0; 2029 2030 if (rk3399_dram_status.timing_config.odt == 1) 2031 gen_rk3399_set_odt(1); 2032 2033 index = (rk3399_dram_status.current_index + 1) & 0x1; 2034 if (rk3399_dram_status.index_freq[index] == mhz) 2035 goto out; 2036 2037 /* 2038 * checking if having available gate traiing timing for 2039 * target freq. 2040 */ 2041 dram_get_parameter(&rk3399_dram_status.timing_config, &dram_timing); 2042 gen_rk3399_ctl_params(&rk3399_dram_status.timing_config, 2043 &dram_timing, index); 2044 gen_rk3399_pi_params(&rk3399_dram_status.timing_config, 2045 &dram_timing, index); 2046 gen_rk3399_phy_params(&rk3399_dram_status.timing_config, 2047 &rk3399_dram_status.drv_odt_lp_cfg, 2048 &dram_timing, index); 2049 rk3399_dram_status.index_freq[index] = mhz; 2050 2051 out: 2052 gen_rk3399_enable_training(rk3399_dram_status.timing_config.ch_cnt, 2053 mhz); 2054 return index; 2055 } 2056 2057 void print_dram_status_info(void) 2058 { 2059 uint32_t *p; 2060 uint32_t i; 2061 2062 p = (uint32_t *) &rk3399_dram_status.timing_config; 2063 INFO("rk3399_dram_status.timing_config:\n"); 2064 for (i = 0; i < sizeof(struct timing_related_config) / 4; i++) 2065 tf_printf("%u\n", p[i]); 2066 p = (uint32_t *) &rk3399_dram_status.drv_odt_lp_cfg; 2067 INFO("rk3399_dram_status.drv_odt_lp_cfg:\n"); 2068 for (i = 0; i < sizeof(struct drv_odt_lp_config) / 4; i++) 2069 tf_printf("%u\n", p[i]); 2070 } 2071 2072 uint32_t ddr_set_rate(uint32_t hz) 2073 { 2074 uint32_t low_power, index; 2075 uint32_t mhz = hz / (1000 * 1000); 2076 2077 if (mhz == 2078 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]) 2079 goto out; 2080 2081 index = to_get_clk_index(mhz); 2082 mhz = dpll_rates_table[index].mhz; 2083 2084 index = prepare_ddr_timing(mhz); 2085 if (index > 1) 2086 goto out; 2087 2088 dcf_start(mhz, index); 2089 wait_dcf_done(); 2090 if (rk3399_dram_status.timing_config.odt == 0) 2091 gen_rk3399_set_odt(0); 2092 2093 rk3399_dram_status.current_index = index; 2094 low_power = rk3399_dram_status.low_power_stat; 2095 resume_low_power(low_power); 2096 out: 2097 return mhz; 2098 } 2099 2100 uint32_t ddr_round_rate(uint32_t hz) 2101 { 2102 int index; 2103 uint32_t mhz = hz / (1000 * 1000); 2104 2105 index = to_get_clk_index(mhz); 2106 2107 return dpll_rates_table[index].mhz * 1000 * 1000; 2108 } 2109