16fba6e04STony Xie /* 26fba6e04STony Xie * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 36fba6e04STony Xie * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 56fba6e04STony Xie */ 66fba6e04STony Xie 76fba6e04STony Xie #ifndef __PLAT_DEF_H__ 86fba6e04STony Xie #define __PLAT_DEF_H__ 96fba6e04STony Xie 106fba6e04STony Xie /* Special value used to verify platform parameters from BL2 to BL3-1 */ 116fba6e04STony Xie #define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 126fba6e04STony Xie 136fba6e04STony Xie #define CCI400_BASE 0xffb90000 146fba6e04STony Xie #define CCI400_SIZE 0x10000 156fba6e04STony Xie 166fba6e04STony Xie #define GIC400_BASE 0xffb70000 176fba6e04STony Xie #define GIC400_SIZE 0x10000 186fba6e04STony Xie 196fba6e04STony Xie #define STIME_BASE 0xff830000 206fba6e04STony Xie #define STIME_SIZE 0x10000 216fba6e04STony Xie 226fba6e04STony Xie #define CRU_BASE 0xff760000 236fba6e04STony Xie #define CRU_SIZE 0x10000 246fba6e04STony Xie 256fba6e04STony Xie #define GRF_BASE 0xff770000 266fba6e04STony Xie #define GRF_SIZE 0x10000 276fba6e04STony Xie 286fba6e04STony Xie #define SGRF_BASE 0xff740000 296fba6e04STony Xie #define SGRF_SIZE 0x10000 306fba6e04STony Xie 316fba6e04STony Xie #define PMU_BASE 0xff730000 326fba6e04STony Xie #define PMU_GRF_BASE 0xff738000 336fba6e04STony Xie #define PMU_SIZE 0x10000 346fba6e04STony Xie 356fba6e04STony Xie #define RK_INTMEM_BASE 0xff8c0000 366fba6e04STony Xie #define RK_INTMEM_SIZE 0x10000 376fba6e04STony Xie 386fba6e04STony Xie #define UART_DBG_BASE 0xff690000 396fba6e04STony Xie #define UART_DBG_SIZE 0x10000 406fba6e04STony Xie 416fba6e04STony Xie #define CRU_BASE 0xff760000 426fba6e04STony Xie 436fba6e04STony Xie #define PMUSRAM_BASE 0xff720000 446fba6e04STony Xie #define PMUSRAM_SIZE 0x10000 456fba6e04STony Xie #define PMUSRAM_RSIZE 0x1000 466fba6e04STony Xie 476fba6e04STony Xie #define DDR_PCTL_BASE 0xff610000 486fba6e04STony Xie #define DDR_PCTL_SIZE 0x10000 496fba6e04STony Xie 506fba6e04STony Xie #define DDR_PHY_BASE 0xff620000 516fba6e04STony Xie #define DDR_PHY_SIZE 0x10000 526fba6e04STony Xie 536fba6e04STony Xie #define SERVICE_BUS_BASE 0xffac0000 546fba6e04STony Xie #define SERVICE_BUS_SISE 0x50000 556fba6e04STony Xie 566fba6e04STony Xie #define COLD_BOOT_BASE 0xffff0000 576fba6e04STony Xie /************************************************************************** 586fba6e04STony Xie * UART related constants 596fba6e04STony Xie **************************************************************************/ 606fba6e04STony Xie #define RK3368_UART2_BASE UART_DBG_BASE 616fba6e04STony Xie #define RK3368_BAUDRATE 115200 626fba6e04STony Xie #define RK3368_UART_CLOCK 24000000 636fba6e04STony Xie 646fba6e04STony Xie /****************************************************************************** 656fba6e04STony Xie * System counter frequency related constants 666fba6e04STony Xie ******************************************************************************/ 676fba6e04STony Xie #define SYS_COUNTER_FREQ_IN_TICKS 24000000 686fba6e04STony Xie 696fba6e04STony Xie /****************************************************************************** 706fba6e04STony Xie * GIC-400 & interrupt handling related constants 716fba6e04STony Xie ******************************************************************************/ 726fba6e04STony Xie 736fba6e04STony Xie /* Base rk_platform compatible GIC memory map */ 746fba6e04STony Xie #define RK3368_GICD_BASE (GIC400_BASE + 0x1000) 756fba6e04STony Xie #define RK3368_GICC_BASE (GIC400_BASE + 0x2000) 766fba6e04STony Xie #define RK3368_GICR_BASE 0 /* no GICR in GIC-400 */ 776fba6e04STony Xie 786fba6e04STony Xie /***************************************************************************** 796fba6e04STony Xie * CCI-400 related constants 806fba6e04STony Xie ******************************************************************************/ 816fba6e04STony Xie #define PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX 3 826fba6e04STony Xie #define PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX 4 836fba6e04STony Xie 846fba6e04STony Xie /****************************************************************************** 856fba6e04STony Xie * sgi, ppi 866fba6e04STony Xie ******************************************************************************/ 876fba6e04STony Xie #define RK_IRQ_SEC_PHY_TIMER 29 886fba6e04STony Xie 896fba6e04STony Xie #define RK_IRQ_SEC_SGI_0 8 906fba6e04STony Xie #define RK_IRQ_SEC_SGI_1 9 916fba6e04STony Xie #define RK_IRQ_SEC_SGI_2 10 926fba6e04STony Xie #define RK_IRQ_SEC_SGI_3 11 936fba6e04STony Xie #define RK_IRQ_SEC_SGI_4 12 946fba6e04STony Xie #define RK_IRQ_SEC_SGI_5 13 956fba6e04STony Xie #define RK_IRQ_SEC_SGI_6 14 966fba6e04STony Xie #define RK_IRQ_SEC_SGI_7 15 976fba6e04STony Xie 986fba6e04STony Xie /* 996fba6e04STony Xie * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 1006fba6e04STony Xie * terminology. On a GICv2 system or mode, the lists will be merged and treated 1016fba6e04STony Xie * as Group 0 interrupts. 1026fba6e04STony Xie */ 103*2d6f1f01SAntonio Nino Diaz #define PLAT_RK_GICV2_G1S_IRQS \ 104*2d6f1f01SAntonio Nino Diaz INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ 105*2d6f1f01SAntonio Nino Diaz GICV2_INTR_GROUP1, GIC_INTR_CFG_LEVEL) 1066fba6e04STony Xie 1076fba6e04STony Xie #endif /* __PLAT_DEF_H__ */ 108