1 /* 2 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <common_def.h> 12 #include <rk3368_def.h> 13 #include <utils_def.h> 14 15 #define DEBUG_XLAT_TABLE 0 16 17 /******************************************************************************* 18 * Platform binary types for linking 19 ******************************************************************************/ 20 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 21 #define PLATFORM_LINKER_ARCH aarch64 22 23 /******************************************************************************* 24 * Generic platform constants 25 ******************************************************************************/ 26 27 /* Size of cacheable stacks */ 28 #if DEBUG_XLAT_TABLE 29 #define PLATFORM_STACK_SIZE 0x800 30 #elif defined(IMAGE_BL1) 31 #define PLATFORM_STACK_SIZE 0x440 32 #elif defined(IMAGE_BL2) 33 #define PLATFORM_STACK_SIZE 0x400 34 #elif defined(IMAGE_BL31) 35 #define PLATFORM_STACK_SIZE 0x800 36 #elif defined(IMAGE_BL32) 37 #define PLATFORM_STACK_SIZE 0x440 38 #endif 39 40 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 41 42 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 43 #define PLATFORM_SYSTEM_COUNT 1 44 #define PLATFORM_CLUSTER_COUNT 2 45 #define PLATFORM_CLUSTER0_CORE_COUNT 4 46 #define PLATFORM_CLUSTER1_CORE_COUNT 4 47 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 48 PLATFORM_CLUSTER0_CORE_COUNT) 49 #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 50 #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 51 PLATFORM_CLUSTER_COUNT + \ 52 PLATFORM_CORE_COUNT) 53 54 #define PLAT_RK_CLST_TO_CPUID_SHIFT 8 55 56 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 57 58 /* 59 * This macro defines the deepest retention state possible. A higher state 60 * id will represent an invalid or a power down state. 61 */ 62 #define PLAT_MAX_RET_STATE U(1) 63 64 /* 65 * This macro defines the deepest power down states possible. Any state ID 66 * higher than this is invalid. 67 */ 68 #define PLAT_MAX_OFF_STATE U(2) 69 70 /******************************************************************************* 71 * Platform memory map related constants 72 ******************************************************************************/ 73 /* TF txet, ro, rw, Size: 512KB */ 74 #define TZRAM_BASE (0x0) 75 #define TZRAM_SIZE (0x80000) 76 77 /******************************************************************************* 78 * BL31 specific defines. 79 ******************************************************************************/ 80 /* 81 * Put BL3-1 at the top of the Trusted RAM 82 */ 83 #define BL31_BASE (TZRAM_BASE + 0x10000) 84 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 85 86 /******************************************************************************* 87 * Platform specific page table and MMU setup constants 88 ******************************************************************************/ 89 #define ADDR_SPACE_SIZE (1ULL << 32) 90 #define MAX_XLAT_TABLES 8 91 #define MAX_MMAP_REGIONS 16 92 93 /******************************************************************************* 94 * Declarations and constants to access the mailboxes safely. Each mailbox is 95 * aligned on the biggest cache line size in the platform. This is known only 96 * to the platform as it might have a combination of integrated and external 97 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 98 * line at any cache level. They could belong to different cpus/clusters & 99 * get written while being protected by different locks causing corruption of 100 * a valid mailbox address. 101 ******************************************************************************/ 102 #define CACHE_WRITEBACK_SHIFT 6 103 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 104 105 /* 106 * Define GICD and GICC and GICR base 107 */ 108 #define PLAT_RK_GICD_BASE RK3368_GICD_BASE 109 #define PLAT_RK_GICC_BASE RK3368_GICC_BASE 110 111 /* 112 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 113 * terminology. On a GICv2 system or mode, the lists will be merged and treated 114 * as Group 0 interrupts. 115 */ 116 #define PLAT_RK_G1S_IRQS RK_G1S_IRQS 117 118 #define PLAT_RK_UART_BASE RK3368_UART2_BASE 119 #define PLAT_RK_UART_CLOCK RK3368_UART_CLOCK 120 #define PLAT_RK_UART_BAUDRATE RK3368_BAUDRATE 121 122 #define PLAT_RK_CCI_BASE CCI400_BASE 123 124 #define PLAT_RK_PRIMARY_CPU 0x0 125 126 #define PSRAM_DO_DDR_RESUME 0 127 #define PSRAM_CHECK_WAKEUP_CPU 0 128 129 #endif /* PLATFORM_DEF_H */ 130