1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 18 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #ifndef __SOC_H__ 28 #define __SOC_H__ 29 30 enum plls_id { 31 ABPLL_ID = 0, 32 ALPLL_ID, 33 DPLL_ID, 34 CPLL_ID, 35 GPLL_ID, 36 NPLL_ID, 37 END_PLL_ID, 38 }; 39 40 /***************************************************************************** 41 * secure timer 42 *****************************************************************************/ 43 #define TIMER_LOADE_COUNT0 0x00 44 #define TIMER_LOADE_COUNT1 0x04 45 #define TIMER_CURRENT_VALUE0 0x08 46 #define TIMER_CURRENT_VALUE1 0x0C 47 #define TIMER_CONTROL_REG 0x10 48 #define TIMER_INTSTATUS 0x18 49 50 #define TIMER_EN 0x1 51 52 #define STIMER1_BASE (STIME_BASE + 0x20) 53 54 #define CYCL_24M_CNT_US(us) (24 * us) 55 #define CYCL_24M_CNT_MS(ms) (ms * CYCL_24M_CNT_US(1000)) 56 57 /***************************************************************************** 58 * sgrf reg, offset 59 *****************************************************************************/ 60 #define SGRF_SOC_CON(n) (0x0 + (n) * 4) 61 #define SGRF_BUSDMAC_CON(n) (0x100 + (n) * 4) 62 63 #define SGRF_SOC_CON_NS 0xffff0000 64 65 /***************************************************************************** 66 * con6[2]pmusram is security. 67 * con6[6]stimer is security. 68 *****************************************************************************/ 69 #define PMUSRAM_S_SHIFT 2 70 #define PMUSRAM_S 1 71 #define STIMER_S_SHIFT 6 72 #define STIMER_S 1 73 #define SGRF_SOC_CON7_BITS ((0xffff << 16) | \ 74 (PMUSRAM_S << PMUSRAM_S_SHIFT) | \ 75 (STIMER_S << STIMER_S_SHIFT)) 76 77 #define SGRF_BUSDMAC_CON0_NS 0xfffcfff8 78 #define SGRF_BUSDMAC_CON1_NS 0xffff0fff 79 80 /* 81 * sgrf_soc_con1~2, mask and offset 82 */ 83 #define CPU_BOOT_ADDR_WMASK 0xffff0000 84 #define CPU_BOOT_ADDR_ALIGN 16 85 86 /***************************************************************************** 87 * cru reg, offset 88 *****************************************************************************/ 89 #define CRU_SOFTRST_CON 0x300 90 #define CRU_SOFTRSTS_CON(n) (CRU_SOFTRST_CON + ((n) * 4)) 91 #define CRU_SOFTRSTS_CON_CNT 15 92 93 #define SOFTRST_DMA1 0x40004 94 #define SOFTRST_DMA2 0x10001 95 96 #define RST_DMA1_MSK 0x4 97 #define RST_DMA2_MSK 0x0 98 99 #define CRU_CLKSEL_CON 0x100 100 #define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON + ((i) * 4)) 101 #define CRU_CLKSEL_CON_CNT 56 102 103 #define CRU_CLKGATE_CON 0x200 104 #define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + ((i) * 4)) 105 #define CRU_CLKGATES_CON_CNT 25 106 107 #define CRU_GLB_SRST_FST 0x280 108 #define CRU_GLB_SRST_SND 0x284 109 #define CRU_GLB_RST_CON 0x388 110 111 #define CRU_CONS_GATEID(i) (16 * (i)) 112 #define GATE_ID(reg, bit) ((reg * 16) + bit) 113 114 #define PMU_RST_BY_SECOND_SFT (BIT(1) << 2) 115 #define PMU_RST_NOT_BY_SFT (BIT(1) << 2) 116 117 /*************************************************************************** 118 * pll 119 ***************************************************************************/ 120 #define PLL_PWR_DN_MSK (0x1 << 1) 121 #define PLL_PWR_DN REG_WMSK_BITS(1, 1, 0x1) 122 #define PLL_PWR_ON REG_WMSK_BITS(0, 1, 0x1) 123 #define PLL_RESET REG_WMSK_BITS(1, 5, 0x1) 124 #define PLL_RESET_RESUME REG_WMSK_BITS(0, 5, 0x1) 125 #define PLL_BYPASS_MSK (0x1 << 0) 126 #define PLL_BYPASS_W_MSK (PLL_BYPASS_MSK << 16) 127 #define PLL_BYPASS REG_WMSK_BITS(1, 0, 0x1) 128 #define PLL_NO_BYPASS REG_WMSK_BITS(0, 0, 0x1) 129 #define PLL_MODE_SHIFT 8 130 #define PLL_MODE_MSK 0x3 131 #define PLLS_MODE_WMASK (PLL_MODE_MSK << (16 + PLL_MODE_SHIFT)) 132 #define PLL_SLOW 0x0 133 #define PLL_NORM 0x1 134 #define PLL_DEEP 0x2 135 #define PLL_SLOW_BITS REG_WMSK_BITS(PLL_SLOW, 8, 0x3) 136 #define PLL_NORM_BITS REG_WMSK_BITS(PLL_NORM, 8, 0x3) 137 #define PLL_DEEP_BITS REG_WMSK_BITS(PLL_DEEP, 8, 0x3) 138 139 #define PLL_CONS(id, i) ((id) * 0x10 + ((i) * 4)) 140 141 #define REG_W_MSK(bits_shift, msk) \ 142 ((msk) << ((bits_shift) + 16)) 143 #define REG_VAL_CLRBITS(val, bits_shift, msk) \ 144 (val & (~(msk << bits_shift))) 145 #define REG_SET_BITS(bits, bits_shift, msk) \ 146 (((bits) & (msk)) << (bits_shift)) 147 #define REG_WMSK_BITS(bits, bits_shift, msk) \ 148 (REG_W_MSK(bits_shift, msk) | \ 149 REG_SET_BITS(bits, bits_shift, msk)) 150 151 #define regs_updata_bit_set(addr, shift) \ 152 regs_updata_bits((addr), 0x1, 0x1, (shift)) 153 #define regs_updata_bit_clr(addr, shift) \ 154 regs_updata_bits((addr), 0x0, 0x1, (shift)) 155 156 void __dead2 soc_sys_global_soft_reset(void); 157 void regs_updata_bits(uintptr_t addr, uint32_t val, 158 uint32_t mask, uint32_t shift); 159 void soc_sleep_config(void); 160 void pm_plls_resume(void); 161 162 #endif /* __SOC_H__ */ 163