1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <platform_def.h> 8 9 #include <arch_helpers.h> 10 #include <common/debug.h> 11 #include <lib/mmio.h> 12 13 #include <plat_private.h> 14 #include <rk3368_def.h> 15 #include <soc.h> 16 17 static uint32_t plls_con[END_PLL_ID][4]; 18 19 /* Table of regions to map using the MMU. */ 20 const mmap_region_t plat_rk_mmap[] = { 21 MAP_REGION_FLAT(CCI400_BASE, CCI400_SIZE, 22 MT_DEVICE | MT_RW | MT_SECURE), 23 MAP_REGION_FLAT(GIC400_BASE, GIC400_SIZE, 24 MT_DEVICE | MT_RW | MT_SECURE), 25 MAP_REGION_FLAT(STIME_BASE, STIME_SIZE, 26 MT_DEVICE | MT_RW | MT_SECURE), 27 MAP_REGION_FLAT(SGRF_BASE, SGRF_SIZE, 28 MT_DEVICE | MT_RW | MT_SECURE), 29 MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE, 30 MT_MEMORY | MT_RW | MT_SECURE), 31 MAP_REGION_FLAT(PMU_BASE, PMU_SIZE, 32 MT_DEVICE | MT_RW | MT_SECURE), 33 MAP_REGION_FLAT(UART_DBG_BASE, UART_DBG_SIZE, 34 MT_DEVICE | MT_RW | MT_SECURE), 35 MAP_REGION_FLAT(CRU_BASE, CRU_SIZE, 36 MT_DEVICE | MT_RW | MT_SECURE), 37 MAP_REGION_FLAT(DDR_PCTL_BASE, DDR_PCTL_SIZE, 38 MT_DEVICE | MT_RW | MT_SECURE), 39 MAP_REGION_FLAT(DDR_PHY_BASE, DDR_PHY_SIZE, 40 MT_DEVICE | MT_RW | MT_SECURE), 41 MAP_REGION_FLAT(GRF_BASE, GRF_SIZE, 42 MT_DEVICE | MT_RW | MT_SECURE), 43 MAP_REGION_FLAT(SERVICE_BUS_BASE, SERVICE_BUS_SISE, 44 MT_DEVICE | MT_RW | MT_SECURE), 45 { 0 } 46 }; 47 48 /* The RockChip power domain tree descriptor */ 49 const unsigned char rockchip_power_domain_tree_desc[] = { 50 /* No of root nodes */ 51 PLATFORM_SYSTEM_COUNT, 52 /* No of children for the root node */ 53 PLATFORM_CLUSTER_COUNT, 54 /* No of children for the first cluster node */ 55 PLATFORM_CLUSTER0_CORE_COUNT, 56 /* No of children for the second cluster node */ 57 PLATFORM_CLUSTER1_CORE_COUNT 58 }; 59 60 void secure_timer_init(void) 61 { 62 mmio_write_32(STIMER1_BASE + TIMER_LOADE_COUNT0, 0xffffffff); 63 mmio_write_32(STIMER1_BASE + TIMER_LOADE_COUNT1, 0xffffffff); 64 65 /* auto reload & enable the timer */ 66 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, TIMER_EN); 67 } 68 69 void sgrf_init(void) 70 { 71 /* setting all configurable ip into no-secure */ 72 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SOC_CON_NS); 73 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SOC_CON7_BITS); 74 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SOC_CON_NS); 75 76 /* secure dma to no sesure */ 77 mmio_write_32(SGRF_BASE + SGRF_BUSDMAC_CON(0), SGRF_BUSDMAC_CON0_NS); 78 mmio_write_32(SGRF_BASE + SGRF_BUSDMAC_CON(1), SGRF_BUSDMAC_CON1_NS); 79 dsb(); 80 81 /* rst dma1 */ 82 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), 83 RST_DMA1_MSK | (RST_DMA1_MSK << 16)); 84 /* rst dma2 */ 85 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), 86 RST_DMA2_MSK | (RST_DMA2_MSK << 16)); 87 88 dsb(); 89 90 /* release dma1 rst*/ 91 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), (RST_DMA1_MSK << 16)); 92 /* release dma2 rst*/ 93 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), (RST_DMA2_MSK << 16)); 94 } 95 96 void plat_rockchip_soc_init(void) 97 { 98 secure_timer_init(); 99 sgrf_init(); 100 } 101 102 void regs_updata_bits(uintptr_t addr, uint32_t val, 103 uint32_t mask, uint32_t shift) 104 { 105 uint32_t tmp, orig; 106 107 orig = mmio_read_32(addr); 108 109 tmp = orig & ~(mask << shift); 110 tmp |= (val & mask) << shift; 111 112 if (tmp != orig) 113 mmio_write_32(addr, tmp); 114 dsb(); 115 } 116 117 static void plls_suspend(uint32_t pll_id) 118 { 119 plls_con[pll_id][0] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 0)); 120 plls_con[pll_id][1] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 1)); 121 plls_con[pll_id][2] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 2)); 122 plls_con[pll_id][3] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 3)); 123 124 mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_SLOW_BITS); 125 mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_BYPASS); 126 } 127 128 static void pm_plls_suspend(void) 129 { 130 plls_suspend(NPLL_ID); 131 plls_suspend(CPLL_ID); 132 plls_suspend(GPLL_ID); 133 plls_suspend(ABPLL_ID); 134 plls_suspend(ALPLL_ID); 135 } 136 137 static inline void plls_resume(void) 138 { 139 mmio_write_32(CRU_BASE + PLL_CONS(ABPLL_ID, 3), 140 plls_con[ABPLL_ID][3] | PLL_BYPASS_W_MSK); 141 mmio_write_32(CRU_BASE + PLL_CONS(ALPLL_ID, 3), 142 plls_con[ALPLL_ID][3] | PLL_BYPASS_W_MSK); 143 mmio_write_32(CRU_BASE + PLL_CONS(GPLL_ID, 3), 144 plls_con[GPLL_ID][3] | PLL_BYPASS_W_MSK); 145 mmio_write_32(CRU_BASE + PLL_CONS(CPLL_ID, 3), 146 plls_con[CPLL_ID][3] | PLL_BYPASS_W_MSK); 147 mmio_write_32(CRU_BASE + PLL_CONS(NPLL_ID, 3), 148 plls_con[NPLL_ID][3] | PLL_BYPASS_W_MSK); 149 } 150 151 void soc_sleep_config(void) 152 { 153 int i = 0; 154 155 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) 156 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), 0xffff0000); 157 pm_plls_suspend(); 158 159 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) 160 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), 0xffff0000); 161 } 162 163 void pm_plls_resume(void) 164 { 165 plls_resume(); 166 167 mmio_write_32(CRU_BASE + PLL_CONS(ABPLL_ID, 3), 168 plls_con[ABPLL_ID][3] | PLLS_MODE_WMASK); 169 mmio_write_32(CRU_BASE + PLL_CONS(ALPLL_ID, 3), 170 plls_con[ALPLL_ID][3] | PLLS_MODE_WMASK); 171 mmio_write_32(CRU_BASE + PLL_CONS(GPLL_ID, 3), 172 plls_con[GPLL_ID][3] | PLLS_MODE_WMASK); 173 mmio_write_32(CRU_BASE + PLL_CONS(CPLL_ID, 3), 174 plls_con[CPLL_ID][3] | PLLS_MODE_WMASK); 175 mmio_write_32(CRU_BASE + PLL_CONS(NPLL_ID, 3), 176 plls_con[NPLL_ID][3] | PLLS_MODE_WMASK); 177 } 178 179 void __dead2 rockchip_soc_soft_reset(void) 180 { 181 uint32_t temp_val; 182 183 mmio_write_32(CRU_BASE + PLL_CONS((GPLL_ID), 3), PLL_SLOW_BITS); 184 mmio_write_32(CRU_BASE + PLL_CONS((CPLL_ID), 3), PLL_SLOW_BITS); 185 mmio_write_32(CRU_BASE + PLL_CONS((NPLL_ID), 3), PLL_SLOW_BITS); 186 mmio_write_32(CRU_BASE + PLL_CONS((ABPLL_ID), 3), PLL_SLOW_BITS); 187 mmio_write_32(CRU_BASE + PLL_CONS((ALPLL_ID), 3), PLL_SLOW_BITS); 188 189 temp_val = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON) | 190 PMU_RST_BY_SECOND_SFT; 191 192 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, temp_val); 193 mmio_write_32(CRU_BASE + CRU_GLB_SRST_SND, 0xeca8); 194 195 /* 196 * Maybe the HW needs some times to reset the system, 197 * so we do not hope the core to excute valid codes. 198 */ 199 while (1) 200 ; 201 } 202