1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 18 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <arch_helpers.h> 28 #include <debug.h> 29 #include <mmio.h> 30 #include <platform_def.h> 31 #include <plat_private.h> 32 #include <rk3368_def.h> 33 #include <soc.h> 34 35 static uint32_t plls_con[END_PLL_ID][4]; 36 37 /* Table of regions to map using the MMU. */ 38 const mmap_region_t plat_rk_mmap[] = { 39 MAP_REGION_FLAT(CCI400_BASE, CCI400_SIZE, 40 MT_DEVICE | MT_RW | MT_SECURE), 41 MAP_REGION_FLAT(GIC400_BASE, GIC400_SIZE, 42 MT_DEVICE | MT_RW | MT_SECURE), 43 MAP_REGION_FLAT(STIME_BASE, STIME_SIZE, 44 MT_DEVICE | MT_RW | MT_SECURE), 45 MAP_REGION_FLAT(SGRF_BASE, SGRF_SIZE, 46 MT_DEVICE | MT_RW | MT_SECURE), 47 MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE, 48 MT_MEMORY | MT_RW | MT_SECURE), 49 MAP_REGION_FLAT(PMU_BASE, PMU_SIZE, 50 MT_DEVICE | MT_RW | MT_SECURE), 51 MAP_REGION_FLAT(UART_DBG_BASE, UART_DBG_SIZE, 52 MT_DEVICE | MT_RW | MT_SECURE), 53 MAP_REGION_FLAT(CRU_BASE, CRU_SIZE, 54 MT_DEVICE | MT_RW | MT_SECURE), 55 MAP_REGION_FLAT(DDR_PCTL_BASE, DDR_PCTL_SIZE, 56 MT_DEVICE | MT_RW | MT_SECURE), 57 MAP_REGION_FLAT(DDR_PHY_BASE, DDR_PHY_SIZE, 58 MT_DEVICE | MT_RW | MT_SECURE), 59 MAP_REGION_FLAT(GRF_BASE, GRF_SIZE, 60 MT_DEVICE | MT_RW | MT_SECURE), 61 MAP_REGION_FLAT(SERVICE_BUS_BASE, SERVICE_BUS_SISE, 62 MT_DEVICE | MT_RW | MT_SECURE), 63 { 0 } 64 }; 65 66 /* The RockChip power domain tree descriptor */ 67 const unsigned char rockchip_power_domain_tree_desc[] = { 68 /* No of root nodes */ 69 PLATFORM_SYSTEM_COUNT, 70 /* No of children for the root node */ 71 PLATFORM_CLUSTER_COUNT, 72 /* No of children for the first cluster node */ 73 PLATFORM_CLUSTER0_CORE_COUNT, 74 /* No of children for the second cluster node */ 75 PLATFORM_CLUSTER1_CORE_COUNT 76 }; 77 78 void secure_timer_init(void) 79 { 80 mmio_write_32(STIMER1_BASE + TIMER_LOADE_COUNT0, 0xffffffff); 81 mmio_write_32(STIMER1_BASE + TIMER_LOADE_COUNT1, 0xffffffff); 82 83 /* auto reload & enable the timer */ 84 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, TIMER_EN); 85 } 86 87 void sgrf_init(void) 88 { 89 /* setting all configurable ip into no-secure */ 90 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SOC_CON_NS); 91 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SOC_CON7_BITS); 92 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SOC_CON_NS); 93 94 /* secure dma to no sesure */ 95 mmio_write_32(SGRF_BASE + SGRF_BUSDMAC_CON(0), SGRF_BUSDMAC_CON0_NS); 96 mmio_write_32(SGRF_BASE + SGRF_BUSDMAC_CON(1), SGRF_BUSDMAC_CON1_NS); 97 dsb(); 98 99 /* rst dma1 */ 100 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), 101 RST_DMA1_MSK | (RST_DMA1_MSK << 16)); 102 /* rst dma2 */ 103 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), 104 RST_DMA2_MSK | (RST_DMA2_MSK << 16)); 105 106 dsb(); 107 108 /* release dma1 rst*/ 109 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), (RST_DMA1_MSK << 16)); 110 /* release dma2 rst*/ 111 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), (RST_DMA2_MSK << 16)); 112 } 113 114 void plat_rockchip_soc_init(void) 115 { 116 secure_timer_init(); 117 sgrf_init(); 118 } 119 120 void regs_updata_bits(uintptr_t addr, uint32_t val, 121 uint32_t mask, uint32_t shift) 122 { 123 uint32_t tmp, orig; 124 125 orig = mmio_read_32(addr); 126 127 tmp = orig & ~(mask << shift); 128 tmp |= (val & mask) << shift; 129 130 if (tmp != orig) 131 mmio_write_32(addr, tmp); 132 dsb(); 133 } 134 135 static void plls_suspend(uint32_t pll_id) 136 { 137 plls_con[pll_id][0] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 0)); 138 plls_con[pll_id][1] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 1)); 139 plls_con[pll_id][2] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 2)); 140 plls_con[pll_id][3] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 3)); 141 142 mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_SLOW_BITS); 143 mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_BYPASS); 144 } 145 146 static void pm_plls_suspend(void) 147 { 148 plls_suspend(NPLL_ID); 149 plls_suspend(CPLL_ID); 150 plls_suspend(GPLL_ID); 151 plls_suspend(ABPLL_ID); 152 plls_suspend(ALPLL_ID); 153 } 154 155 static inline void plls_resume(void) 156 { 157 mmio_write_32(CRU_BASE + PLL_CONS(ABPLL_ID, 3), 158 plls_con[ABPLL_ID][3] | PLL_BYPASS_W_MSK); 159 mmio_write_32(CRU_BASE + PLL_CONS(ALPLL_ID, 3), 160 plls_con[ALPLL_ID][3] | PLL_BYPASS_W_MSK); 161 mmio_write_32(CRU_BASE + PLL_CONS(GPLL_ID, 3), 162 plls_con[GPLL_ID][3] | PLL_BYPASS_W_MSK); 163 mmio_write_32(CRU_BASE + PLL_CONS(CPLL_ID, 3), 164 plls_con[CPLL_ID][3] | PLL_BYPASS_W_MSK); 165 mmio_write_32(CRU_BASE + PLL_CONS(NPLL_ID, 3), 166 plls_con[NPLL_ID][3] | PLL_BYPASS_W_MSK); 167 } 168 169 void soc_sleep_config(void) 170 { 171 int i = 0; 172 173 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) 174 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), 0xffff0000); 175 pm_plls_suspend(); 176 177 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) 178 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), 0xffff0000); 179 } 180 181 void pm_plls_resume(void) 182 { 183 plls_resume(); 184 185 mmio_write_32(CRU_BASE + PLL_CONS(ABPLL_ID, 3), 186 plls_con[ABPLL_ID][3] | PLLS_MODE_WMASK); 187 mmio_write_32(CRU_BASE + PLL_CONS(ALPLL_ID, 3), 188 plls_con[ALPLL_ID][3] | PLLS_MODE_WMASK); 189 mmio_write_32(CRU_BASE + PLL_CONS(GPLL_ID, 3), 190 plls_con[GPLL_ID][3] | PLLS_MODE_WMASK); 191 mmio_write_32(CRU_BASE + PLL_CONS(CPLL_ID, 3), 192 plls_con[CPLL_ID][3] | PLLS_MODE_WMASK); 193 mmio_write_32(CRU_BASE + PLL_CONS(NPLL_ID, 3), 194 plls_con[NPLL_ID][3] | PLLS_MODE_WMASK); 195 } 196 197 void __dead2 soc_sys_global_soft_reset(void) 198 { 199 uint32_t temp_val; 200 201 mmio_write_32(CRU_BASE + PLL_CONS((GPLL_ID), 3), PLL_SLOW_BITS); 202 mmio_write_32(CRU_BASE + PLL_CONS((CPLL_ID), 3), PLL_SLOW_BITS); 203 mmio_write_32(CRU_BASE + PLL_CONS((NPLL_ID), 3), PLL_SLOW_BITS); 204 mmio_write_32(CRU_BASE + PLL_CONS((ABPLL_ID), 3), PLL_SLOW_BITS); 205 mmio_write_32(CRU_BASE + PLL_CONS((ALPLL_ID), 3), PLL_SLOW_BITS); 206 207 temp_val = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON) | 208 PMU_RST_BY_SECOND_SFT; 209 210 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, temp_val); 211 mmio_write_32(CRU_BASE + CRU_GLB_SRST_SND, 0xeca8); 212 213 /* 214 * Maybe the HW needs some times to reset the system, 215 * so we do not hope the core to excute valid codes. 216 */ 217 while (1) 218 ; 219 } 220