1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <debug.h> 33 #include <mmio.h> 34 #include <platform_def.h> 35 #include <plat_private.h> 36 #include <rk3368_def.h> 37 #include <soc.h> 38 39 static uint32_t plls_con[END_PLL_ID][4]; 40 41 /* Table of regions to map using the MMU. */ 42 const mmap_region_t plat_rk_mmap[] = { 43 MAP_REGION_FLAT(CCI400_BASE, CCI400_SIZE, 44 MT_DEVICE | MT_RW | MT_SECURE), 45 MAP_REGION_FLAT(GIC400_BASE, GIC400_SIZE, 46 MT_DEVICE | MT_RW | MT_SECURE), 47 MAP_REGION_FLAT(STIME_BASE, STIME_SIZE, 48 MT_DEVICE | MT_RW | MT_SECURE), 49 MAP_REGION_FLAT(SGRF_BASE, SGRF_SIZE, 50 MT_DEVICE | MT_RW | MT_SECURE), 51 MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE, 52 MT_MEMORY | MT_RW | MT_SECURE), 53 MAP_REGION_FLAT(PMU_BASE, PMU_SIZE, 54 MT_DEVICE | MT_RW | MT_SECURE), 55 MAP_REGION_FLAT(UART_DBG_BASE, UART_DBG_SIZE, 56 MT_DEVICE | MT_RW | MT_SECURE), 57 MAP_REGION_FLAT(CRU_BASE, CRU_SIZE, 58 MT_DEVICE | MT_RW | MT_SECURE), 59 MAP_REGION_FLAT(DDR_PCTL_BASE, DDR_PCTL_SIZE, 60 MT_DEVICE | MT_RW | MT_SECURE), 61 MAP_REGION_FLAT(DDR_PHY_BASE, DDR_PHY_SIZE, 62 MT_DEVICE | MT_RW | MT_SECURE), 63 MAP_REGION_FLAT(GRF_BASE, GRF_SIZE, 64 MT_DEVICE | MT_RW | MT_SECURE), 65 MAP_REGION_FLAT(SERVICE_BUS_BASE, SERVICE_BUS_SISE, 66 MT_DEVICE | MT_RW | MT_SECURE), 67 { 0 } 68 }; 69 70 /* The RockChip power domain tree descriptor */ 71 const unsigned char rockchip_power_domain_tree_desc[] = { 72 /* No of root nodes */ 73 PLATFORM_SYSTEM_COUNT, 74 /* No of children for the root node */ 75 PLATFORM_CLUSTER_COUNT, 76 /* No of children for the first cluster node */ 77 PLATFORM_CLUSTER0_CORE_COUNT, 78 /* No of children for the second cluster node */ 79 PLATFORM_CLUSTER1_CORE_COUNT 80 }; 81 82 void secure_timer_init(void) 83 { 84 mmio_write_32(STIMER1_BASE + TIMER_LOADE_COUNT0, 0xffffffff); 85 mmio_write_32(STIMER1_BASE + TIMER_LOADE_COUNT1, 0xffffffff); 86 87 /* auto reload & enable the timer */ 88 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, TIMER_EN); 89 } 90 91 void sgrf_init(void) 92 { 93 /* setting all configurable ip into no-secure */ 94 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SOC_CON_NS); 95 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SOC_CON7_BITS); 96 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SOC_CON_NS); 97 98 /* secure dma to no sesure */ 99 mmio_write_32(SGRF_BASE + SGRF_BUSDMAC_CON(0), SGRF_BUSDMAC_CON0_NS); 100 mmio_write_32(SGRF_BASE + SGRF_BUSDMAC_CON(1), SGRF_BUSDMAC_CON1_NS); 101 dsb(); 102 103 /* rst dma1 */ 104 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), 105 RST_DMA1_MSK | (RST_DMA1_MSK << 16)); 106 /* rst dma2 */ 107 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), 108 RST_DMA2_MSK | (RST_DMA2_MSK << 16)); 109 110 dsb(); 111 112 /* release dma1 rst*/ 113 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), (RST_DMA1_MSK << 16)); 114 /* release dma2 rst*/ 115 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), (RST_DMA2_MSK << 16)); 116 } 117 118 void plat_rockchip_soc_init(void) 119 { 120 secure_timer_init(); 121 sgrf_init(); 122 } 123 124 void regs_updata_bits(uintptr_t addr, uint32_t val, 125 uint32_t mask, uint32_t shift) 126 { 127 uint32_t tmp, orig; 128 129 orig = mmio_read_32(addr); 130 131 tmp = orig & ~(mask << shift); 132 tmp |= (val & mask) << shift; 133 134 if (tmp != orig) 135 mmio_write_32(addr, tmp); 136 dsb(); 137 } 138 139 static void plls_suspend(uint32_t pll_id) 140 { 141 plls_con[pll_id][0] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 0)); 142 plls_con[pll_id][1] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 1)); 143 plls_con[pll_id][2] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 2)); 144 plls_con[pll_id][3] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 3)); 145 146 mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_SLOW_BITS); 147 mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_BYPASS); 148 } 149 150 static void pm_plls_suspend(void) 151 { 152 plls_suspend(NPLL_ID); 153 plls_suspend(CPLL_ID); 154 plls_suspend(GPLL_ID); 155 plls_suspend(ABPLL_ID); 156 plls_suspend(ALPLL_ID); 157 } 158 159 static inline void plls_resume(void) 160 { 161 mmio_write_32(CRU_BASE + PLL_CONS(ABPLL_ID, 3), 162 plls_con[ABPLL_ID][3] | PLL_BYPASS_W_MSK); 163 mmio_write_32(CRU_BASE + PLL_CONS(ALPLL_ID, 3), 164 plls_con[ALPLL_ID][3] | PLL_BYPASS_W_MSK); 165 mmio_write_32(CRU_BASE + PLL_CONS(GPLL_ID, 3), 166 plls_con[GPLL_ID][3] | PLL_BYPASS_W_MSK); 167 mmio_write_32(CRU_BASE + PLL_CONS(CPLL_ID, 3), 168 plls_con[CPLL_ID][3] | PLL_BYPASS_W_MSK); 169 mmio_write_32(CRU_BASE + PLL_CONS(NPLL_ID, 3), 170 plls_con[NPLL_ID][3] | PLL_BYPASS_W_MSK); 171 } 172 173 void soc_sleep_config(void) 174 { 175 int i = 0; 176 177 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) 178 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), 0xffff0000); 179 pm_plls_suspend(); 180 181 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) 182 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), 0xffff0000); 183 } 184 185 void pm_plls_resume(void) 186 { 187 plls_resume(); 188 189 mmio_write_32(CRU_BASE + PLL_CONS(ABPLL_ID, 3), 190 plls_con[ABPLL_ID][3] | PLLS_MODE_WMASK); 191 mmio_write_32(CRU_BASE + PLL_CONS(ALPLL_ID, 3), 192 plls_con[ALPLL_ID][3] | PLLS_MODE_WMASK); 193 mmio_write_32(CRU_BASE + PLL_CONS(GPLL_ID, 3), 194 plls_con[GPLL_ID][3] | PLLS_MODE_WMASK); 195 mmio_write_32(CRU_BASE + PLL_CONS(CPLL_ID, 3), 196 plls_con[CPLL_ID][3] | PLLS_MODE_WMASK); 197 mmio_write_32(CRU_BASE + PLL_CONS(NPLL_ID, 3), 198 plls_con[NPLL_ID][3] | PLLS_MODE_WMASK); 199 } 200 201 void __dead2 rockchip_soc_soft_reset(void) 202 { 203 uint32_t temp_val; 204 205 mmio_write_32(CRU_BASE + PLL_CONS((GPLL_ID), 3), PLL_SLOW_BITS); 206 mmio_write_32(CRU_BASE + PLL_CONS((CPLL_ID), 3), PLL_SLOW_BITS); 207 mmio_write_32(CRU_BASE + PLL_CONS((NPLL_ID), 3), PLL_SLOW_BITS); 208 mmio_write_32(CRU_BASE + PLL_CONS((ABPLL_ID), 3), PLL_SLOW_BITS); 209 mmio_write_32(CRU_BASE + PLL_CONS((ALPLL_ID), 3), PLL_SLOW_BITS); 210 211 temp_val = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON) | 212 PMU_RST_BY_SECOND_SFT; 213 214 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, temp_val); 215 mmio_write_32(CRU_BASE + CRU_GLB_SRST_SND, 0xeca8); 216 217 /* 218 * Maybe the HW needs some times to reset the system, 219 * so we do not hope the core to excute valid codes. 220 */ 221 while (1) 222 ; 223 } 224