1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 18 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #ifndef __PMU_H__ 28 #define __PMU_H__ 29 30 /* Allocate sp reginon in pmusram */ 31 #define PSRAM_SP_SIZE 0x80 32 #define PSRAM_SP_BOTTOM (PSRAM_SP_TOP - PSRAM_SP_SIZE) 33 34 /***************************************************************************** 35 * pmu con,reg 36 *****************************************************************************/ 37 #define PMU_WKUP_CFG0 0x0 38 #define PMU_WKUP_CFG1 0x4 39 #define PMU_WKUP_CFG2 0x8 40 #define PMU_TIMEOUT_CNT 0x7c 41 #define PMU_PWRDN_CON 0xc 42 #define PMU_PWRDN_ST 0x10 43 #define PMU_CORE_PWR_ST 0x38 44 45 #define PMU_PWRMD_CORE 0x14 46 #define PMU_PWRMD_COM 0x18 47 #define PMU_SFT_CON 0x1c 48 #define PMU_BUS_IDE_REQ 0x3c 49 #define PMU_BUS_IDE_ST 0x40 50 #define PMU_OSC_CNT 0x48 51 #define PMU_PLLLOCK_CNT 0x4c 52 #define PMU_PLLRST_CNT 0x50 53 #define PMU_STABLE_CNT 0x54 54 #define PMU_DDRIO_PWR_CNT 0x58 55 #define PMU_WKUPRST_CNT 0x5c 56 57 enum pmu_powermode_core { 58 pmu_mdcr_global_int_dis = 0, 59 pmu_mdcr_core_src_gt, 60 pmu_mdcr_clr_cci, 61 pmu_mdcr_cpu0_pd, 62 pmu_mdcr_clr_clst_l = 4, 63 pmu_mdcr_clr_core, 64 pmu_mdcr_scu_l_pd, 65 pmu_mdcr_core_pd, 66 pmu_mdcr_l2_idle = 8, 67 pmu_mdcr_l2_flush 68 }; 69 70 /* 71 * the shift of bits for cores status 72 */ 73 enum pmu_core_pwrst_shift { 74 clstl_cpu_wfe = 2, 75 clstl_cpu_wfi = 6, 76 clstb_cpu_wfe = 12, 77 clstb_cpu_wfi = 16 78 }; 79 80 enum pmu_pdid { 81 PD_CPUL0 = 0, 82 PD_CPUL1, 83 PD_CPUL2, 84 PD_CPUL3, 85 PD_SCUL, 86 PD_CPUB0 = 5, 87 PD_CPUB1, 88 PD_CPUB2, 89 PD_CPUB3, 90 PD_SCUB = 9, 91 PD_PERI = 13, 92 PD_VIDEO, 93 PD_VIO, 94 PD_GPU0, 95 PD_GPU1, 96 PD_END 97 }; 98 99 enum pmu_bus_ide { 100 bus_ide_req_clst_l = 0, 101 bus_ide_req_clst_b, 102 bus_ide_req_gpu, 103 bus_ide_req_core, 104 bus_ide_req_bus = 4, 105 bus_ide_req_dma, 106 bus_ide_req_peri, 107 bus_ide_req_video, 108 bus_ide_req_vio = 8, 109 bus_ide_req_res0, 110 bus_ide_req_cxcs, 111 bus_ide_req_alive, 112 bus_ide_req_pmu = 12, 113 bus_ide_req_msch, 114 bus_ide_req_cci, 115 bus_ide_req_cci400 = 15, 116 bus_ide_req_end 117 }; 118 119 enum pmu_powermode_common { 120 pmu_mode_en = 0, 121 pmu_mode_res0, 122 pmu_mode_bus_pd, 123 pmu_mode_wkup_rst, 124 pmu_mode_pll_pd = 4, 125 pmu_mode_pwr_off, 126 pmu_mode_pmu_use_if, 127 pmu_mode_pmu_alive_use_if, 128 pmu_mode_osc_dis = 8, 129 pmu_mode_input_clamp, 130 pmu_mode_sref_enter, 131 pmu_mode_ddrc_gt, 132 pmu_mode_ddrio_ret = 12, 133 pmu_mode_ddrio_ret_deq, 134 pmu_mode_clr_pmu, 135 pmu_mode_clr_alive, 136 pmu_mode_clr_bus = 16, 137 pmu_mode_clr_dma, 138 pmu_mode_clr_msch, 139 pmu_mode_clr_peri, 140 pmu_mode_clr_video = 20, 141 pmu_mode_clr_vio, 142 pmu_mode_clr_gpu, 143 pmu_mode_clr_mcu, 144 pmu_mode_clr_cxcs = 24, 145 pmu_mode_clr_cci400, 146 pmu_mode_res1, 147 pmu_mode_res2, 148 pmu_mode_res3 = 28, 149 pmu_mode_mclst 150 }; 151 152 enum pmu_core_power_st { 153 clst_l_cpu_wfe = 2, 154 clst_l_cpu_wfi = 6, 155 clst_b_l2_flsh_done = 10, 156 clst_b_l2_wfi = 11, 157 clst_b_cpu_wfe = 12, 158 clst_b_cpu_wfi = 16, 159 mcu_sleeping = 20, 160 }; 161 162 enum pmu_sft_con { 163 pmu_sft_acinactm_clst_b = 5, 164 pmu_sft_l2flsh_clst_b, 165 pmu_sft_glbl_int_dis_b = 9, 166 pmu_sft_ddrio_ret_cfg = 11, 167 }; 168 169 enum pmu_wkup_cfg2 { 170 pmu_cluster_l_wkup_en = 0, 171 pmu_cluster_b_wkup_en, 172 pmu_gpio_wkup_en, 173 pmu_sdio_wkup_en, 174 pmu_sdmmc_wkup_en, 175 pmu_sim_wkup_en, 176 pmu_timer_wkup_en, 177 pmu_usbdev_wkup_en, 178 pmu_sft_wkup_en, 179 pmu_wdt_mcu_wkup_en, 180 pmu_timeout_wkup_en, 181 }; 182 183 enum pmu_bus_idle_st { 184 pmu_idle_ack_cluster_l = 0, 185 pmu_idle_ack_cluster_b, 186 pmu_idle_ack_gpu, 187 pmu_idle_ack_core, 188 pmu_idle_ack_bus, 189 pmu_idle_ack_dma, 190 pmu_idle_ack_peri, 191 pmu_idle_ack_video, 192 pmu_idle_ack_vio, 193 pmu_idle_ack_cci = 10, 194 pmu_idle_ack_msch, 195 pmu_idle_ack_alive, 196 pmu_idle_ack_pmu, 197 pmu_idle_ack_cxcs, 198 pmu_idle_ack_cci400, 199 pmu_inactive_cluster_l, 200 pmu_inactive_cluster_b, 201 pmu_idle_gpu, 202 pmu_idle_core, 203 pmu_idle_bus, 204 pmu_idle_dma, 205 pmu_idle_peri, 206 pmu_idle_video, 207 pmu_idle_vio, 208 pmu_idle_cci = 26, 209 pmu_idle_msch, 210 pmu_idle_alive, 211 pmu_idle_pmu, 212 pmu_active_cxcs, 213 pmu_active_cci, 214 }; 215 216 #define PM_PWRDM_CPUSB_MSK (0xf << 5) 217 218 #define CKECK_WFE_MSK 0x1 219 #define CKECK_WFI_MSK 0x10 220 #define CKECK_WFEI_MSK 0x11 221 222 #define PD_CTR_LOOP 500 223 #define CHK_CPU_LOOP 500 224 225 #define MAX_WAIT_CONUT 1000 226 227 #endif /* __PMU_H__ */ 228