1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PMU_H__ 32 #define __PMU_H__ 33 34 /* Allocate sp reginon in pmusram */ 35 #define PSRAM_SP_SIZE 0x80 36 #define PSRAM_SP_BOTTOM (PSRAM_SP_TOP - PSRAM_SP_SIZE) 37 38 /***************************************************************************** 39 * pmu con,reg 40 *****************************************************************************/ 41 #define PMU_WKUP_CFG0 0x0 42 #define PMU_WKUP_CFG1 0x4 43 #define PMU_WKUP_CFG2 0x8 44 #define PMU_TIMEOUT_CNT 0x7c 45 #define PMU_PWRDN_CON 0xc 46 #define PMU_PWRDN_ST 0x10 47 #define PMU_CORE_PWR_ST 0x38 48 49 #define PMU_PWRMD_CORE 0x14 50 #define PMU_PWRMD_COM 0x18 51 #define PMU_SFT_CON 0x1c 52 #define PMU_BUS_IDE_REQ 0x3c 53 #define PMU_BUS_IDE_ST 0x40 54 #define PMU_OSC_CNT 0x48 55 #define PMU_PLLLOCK_CNT 0x4c 56 #define PMU_PLLRST_CNT 0x50 57 #define PMU_STABLE_CNT 0x54 58 #define PMU_DDRIO_PWR_CNT 0x58 59 #define PMU_WKUPRST_CNT 0x5c 60 61 enum pmu_powermode_core { 62 pmu_mdcr_global_int_dis = 0, 63 pmu_mdcr_core_src_gt, 64 pmu_mdcr_clr_cci, 65 pmu_mdcr_cpu0_pd, 66 pmu_mdcr_clr_clst_l = 4, 67 pmu_mdcr_clr_core, 68 pmu_mdcr_scu_l_pd, 69 pmu_mdcr_core_pd, 70 pmu_mdcr_l2_idle = 8, 71 pmu_mdcr_l2_flush 72 }; 73 74 /* 75 * the shift of bits for cores status 76 */ 77 enum pmu_core_pwrst_shift { 78 clstl_cpu_wfe = 2, 79 clstl_cpu_wfi = 6, 80 clstb_cpu_wfe = 12, 81 clstb_cpu_wfi = 16 82 }; 83 84 enum pmu_pdid { 85 PD_CPUL0 = 0, 86 PD_CPUL1, 87 PD_CPUL2, 88 PD_CPUL3, 89 PD_SCUL, 90 PD_CPUB0 = 5, 91 PD_CPUB1, 92 PD_CPUB2, 93 PD_CPUB3, 94 PD_SCUB = 9, 95 PD_PERI = 13, 96 PD_VIDEO, 97 PD_VIO, 98 PD_GPU0, 99 PD_GPU1, 100 PD_END 101 }; 102 103 enum pmu_bus_ide { 104 bus_ide_req_clst_l = 0, 105 bus_ide_req_clst_b, 106 bus_ide_req_gpu, 107 bus_ide_req_core, 108 bus_ide_req_bus = 4, 109 bus_ide_req_dma, 110 bus_ide_req_peri, 111 bus_ide_req_video, 112 bus_ide_req_vio = 8, 113 bus_ide_req_res0, 114 bus_ide_req_cxcs, 115 bus_ide_req_alive, 116 bus_ide_req_pmu = 12, 117 bus_ide_req_msch, 118 bus_ide_req_cci, 119 bus_ide_req_cci400 = 15, 120 bus_ide_req_end 121 }; 122 123 enum pmu_powermode_common { 124 pmu_mode_en = 0, 125 pmu_mode_res0, 126 pmu_mode_bus_pd, 127 pmu_mode_wkup_rst, 128 pmu_mode_pll_pd = 4, 129 pmu_mode_pwr_off, 130 pmu_mode_pmu_use_if, 131 pmu_mode_pmu_alive_use_if, 132 pmu_mode_osc_dis = 8, 133 pmu_mode_input_clamp, 134 pmu_mode_sref_enter, 135 pmu_mode_ddrc_gt, 136 pmu_mode_ddrio_ret = 12, 137 pmu_mode_ddrio_ret_deq, 138 pmu_mode_clr_pmu, 139 pmu_mode_clr_alive, 140 pmu_mode_clr_bus = 16, 141 pmu_mode_clr_dma, 142 pmu_mode_clr_msch, 143 pmu_mode_clr_peri, 144 pmu_mode_clr_video = 20, 145 pmu_mode_clr_vio, 146 pmu_mode_clr_gpu, 147 pmu_mode_clr_mcu, 148 pmu_mode_clr_cxcs = 24, 149 pmu_mode_clr_cci400, 150 pmu_mode_res1, 151 pmu_mode_res2, 152 pmu_mode_res3 = 28, 153 pmu_mode_mclst 154 }; 155 156 enum pmu_core_power_st { 157 clst_l_cpu_wfe = 2, 158 clst_l_cpu_wfi = 6, 159 clst_b_l2_flsh_done = 10, 160 clst_b_l2_wfi = 11, 161 clst_b_cpu_wfe = 12, 162 clst_b_cpu_wfi = 16, 163 mcu_sleeping = 20, 164 }; 165 166 enum pmu_sft_con { 167 pmu_sft_acinactm_clst_b = 5, 168 pmu_sft_l2flsh_clst_b, 169 pmu_sft_glbl_int_dis_b = 9, 170 pmu_sft_ddrio_ret_cfg = 11, 171 }; 172 173 enum pmu_wkup_cfg2 { 174 pmu_cluster_l_wkup_en = 0, 175 pmu_cluster_b_wkup_en, 176 pmu_gpio_wkup_en, 177 pmu_sdio_wkup_en, 178 pmu_sdmmc_wkup_en, 179 pmu_sim_wkup_en, 180 pmu_timer_wkup_en, 181 pmu_usbdev_wkup_en, 182 pmu_sft_wkup_en, 183 pmu_wdt_mcu_wkup_en, 184 pmu_timeout_wkup_en, 185 }; 186 187 enum pmu_bus_idle_st { 188 pmu_idle_ack_cluster_l = 0, 189 pmu_idle_ack_cluster_b, 190 pmu_idle_ack_gpu, 191 pmu_idle_ack_core, 192 pmu_idle_ack_bus, 193 pmu_idle_ack_dma, 194 pmu_idle_ack_peri, 195 pmu_idle_ack_video, 196 pmu_idle_ack_vio, 197 pmu_idle_ack_cci = 10, 198 pmu_idle_ack_msch, 199 pmu_idle_ack_alive, 200 pmu_idle_ack_pmu, 201 pmu_idle_ack_cxcs, 202 pmu_idle_ack_cci400, 203 pmu_inactive_cluster_l, 204 pmu_inactive_cluster_b, 205 pmu_idle_gpu, 206 pmu_idle_core, 207 pmu_idle_bus, 208 pmu_idle_dma, 209 pmu_idle_peri, 210 pmu_idle_video, 211 pmu_idle_vio, 212 pmu_idle_cci = 26, 213 pmu_idle_msch, 214 pmu_idle_alive, 215 pmu_idle_pmu, 216 pmu_active_cxcs, 217 pmu_active_cci, 218 }; 219 220 #define PM_PWRDM_CPUSB_MSK (0xf << 5) 221 222 #define CKECK_WFE_MSK 0x1 223 #define CKECK_WFI_MSK 0x10 224 #define CKECK_WFEI_MSK 0x11 225 226 #define PD_CTR_LOOP 500 227 #define CHK_CPU_LOOP 500 228 229 #define MAX_WAIT_CONUT 1000 230 231 #endif /* __PMU_H__ */ 232