1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <common_def.h> 12 #include <rk3328_def.h> 13 14 /******************************************************************************* 15 * Platform binary types for linking 16 ******************************************************************************/ 17 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 18 #define PLATFORM_LINKER_ARCH aarch64 19 20 /******************************************************************************* 21 * Generic platform constants 22 ******************************************************************************/ 23 24 /* Size of cacheable stacks */ 25 #if defined(IMAGE_BL1) 26 #define PLATFORM_STACK_SIZE 0x440 27 #elif defined(IMAGE_BL2) 28 #define PLATFORM_STACK_SIZE 0x400 29 #elif defined(IMAGE_BL31) 30 #define PLATFORM_STACK_SIZE 0x800 31 #elif defined(IMAGE_BL32) 32 #define PLATFORM_STACK_SIZE 0x440 33 #endif 34 35 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 36 37 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 38 #define PLATFORM_SYSTEM_COUNT 1 39 #define PLATFORM_CLUSTER_COUNT 1 40 #define PLATFORM_CLUSTER0_CORE_COUNT 4 41 #define PLATFORM_CLUSTER1_CORE_COUNT 0 42 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 43 PLATFORM_CLUSTER0_CORE_COUNT) 44 45 #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 46 PLATFORM_CLUSTER_COUNT + \ 47 PLATFORM_CORE_COUNT) 48 49 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 50 51 #define PLAT_RK_CLST_TO_CPUID_SHIFT 6 52 53 /* 54 * This macro defines the deepest retention state possible. A higher state 55 * id will represent an invalid or a power down state. 56 */ 57 #define PLAT_MAX_RET_STATE U(1) 58 59 /* 60 * This macro defines the deepest power down states possible. Any state ID 61 * higher than this is invalid. 62 */ 63 #define PLAT_MAX_OFF_STATE U(2) 64 65 /******************************************************************************* 66 * Platform memory map related constants 67 ******************************************************************************/ 68 /* TF txet, ro, rw, Size: 512KB */ 69 #define TZRAM_BASE (0x0) 70 #define TZRAM_SIZE (0x80000) 71 72 /******************************************************************************* 73 * BL31 specific defines. 74 ******************************************************************************/ 75 /* 76 * Put BL3-1 at the top of the Trusted RAM 77 */ 78 #define BL31_BASE (TZRAM_BASE + 0x10000) 79 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 80 81 /******************************************************************************* 82 * Platform specific page table and MMU setup constants 83 ******************************************************************************/ 84 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 85 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 86 #define MAX_XLAT_TABLES 9 87 #define MAX_MMAP_REGIONS 33 88 89 /******************************************************************************* 90 * Declarations and constants to access the mailboxes safely. Each mailbox is 91 * aligned on the biggest cache line size in the platform. This is known only 92 * to the platform as it might have a combination of integrated and external 93 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 94 * line at any cache level. They could belong to different cpus/clusters & 95 * get written while being protected by different locks causing corruption of 96 * a valid mailbox address. 97 ******************************************************************************/ 98 #define CACHE_WRITEBACK_SHIFT 6 99 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 100 101 /* 102 * Define GICD and GICC and GICR base 103 */ 104 #define PLAT_RK_GICD_BASE RK3328_GICD_BASE 105 #define PLAT_RK_GICC_BASE RK3328_GICC_BASE 106 107 #define PLAT_RK_UART_BASE RK3328_UART2_BASE 108 #define PLAT_RK_UART_CLOCK RK3328_UART_CLOCK 109 #define PLAT_RK_UART_BAUDRATE RK3328_BAUDRATE 110 111 #define PLAT_RK_PRIMARY_CPU 0x0 112 113 #define PSRAM_DO_DDR_RESUME 0 114 #define PSRAM_CHECK_WAKEUP_CPU 0 115 116 #endif /* PLATFORM_DEF_H */ 117