xref: /rk3399_ARM-atf/plat/rockchip/rk3328/include/plat.ld.S (revision 0e14a7fbeb3014e719302c9b7f6a24c4030dfaf0) 
1/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6#ifndef __ROCKCHIP_PLAT_LD_S__
7#define __ROCKCHIP_PLAT_LD_S__
8
9MEMORY {
10    SRAM (rwx): ORIGIN = SRAM_LDS_BASE, LENGTH = SRAM_LDS_SIZE
11}
12
13SECTIONS
14{
15	. = SRAM_LDS_BASE;
16	ASSERT(. == ALIGN(4096),
17		"SRAM_BASE address is not aligned on a page boundary.")
18
19	/*
20	 * The SRAM space allocation for RK3328
21	 * ----------------
22	 * | sram text
23	 * ----------------
24	 * | sram data
25	 * ----------------
26	 */
27	.text_sram : ALIGN(4096) {
28		__bl31_sram_text_start = .;
29		*(.sram.text)
30		*(.sram.rodata)
31		. = ALIGN(4096);
32		__bl31_sram_text_end = .;
33	} >SRAM
34
35	.data_sram : ALIGN(4096) {
36		__bl31_sram_data_start = .;
37		*(.sram.data)
38		. = ALIGN(4096);
39		__bl31_sram_data_end = .;
40	} >SRAM
41	__sram_incbin_start = .;
42	__sram_incbin_end = .;
43}
44
45#endif /* __ROCKCHIP_PLAT_LD_S__ */
46