xref: /rk3399_ARM-atf/plat/rockchip/rk3328/include/plat.ld.S (revision 9d068f66b15e644df4961b74b965323c20f21f14)
10d5ec955Stony.xie/*
2bc5c3007SLin Huang * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
30d5ec955Stony.xie *
4c3e70be1Sdp-arm * SPDX-License-Identifier: BSD-3-Clause
50d5ec955Stony.xie */
6*c3cf06f1SAntonio Nino Diaz#ifndef ROCKCHIP_PLAT_LD_S
7*c3cf06f1SAntonio Nino Diaz#define ROCKCHIP_PLAT_LD_S
80d5ec955Stony.xie
90d5ec955Stony.xieMEMORY {
10bc5c3007SLin Huang    PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE
110d5ec955Stony.xie}
120d5ec955Stony.xie
130d5ec955Stony.xieSECTIONS
140d5ec955Stony.xie{
15bc5c3007SLin Huang	. = PMUSRAM_BASE;
160d5ec955Stony.xie
170d5ec955Stony.xie	/*
18bc5c3007SLin Huang	 * pmu_cpuson_entrypoint request address
19bc5c3007SLin Huang	 * align 64K when resume, so put it in the
20bc5c3007SLin Huang	 * start of pmusram
210d5ec955Stony.xie	 */
22bc5c3007SLin Huang	.text_pmusram : {
23bc5c3007SLin Huang		ASSERT(. == ALIGN(64 * 1024),
24bc5c3007SLin Huang			".pmusram.entry request 64K aligned.");
25bc5c3007SLin Huang		*(.pmusram.entry)
26bc5c3007SLin Huang		__bl31_pmusram_text_start = .;
27bc5c3007SLin Huang		*(.pmusram.text)
28bc5c3007SLin Huang		*(.pmusram.rodata)
29bc5c3007SLin Huang		__bl31_pmusram_text_end = .;
30bc5c3007SLin Huang		__bl31_pmusram_data_start = .;
31bc5c3007SLin Huang		*(.pmusram.data)
32bc5c3007SLin Huang		__bl31_pmusram_data_end = .;
330d5ec955Stony.xie
34bc5c3007SLin Huang	} >PMUSRAM
350d5ec955Stony.xie}
360d5ec955Stony.xie
37*c3cf06f1SAntonio Nino Diaz#endif /* ROCKCHIP_PLAT_LD_S */
38