1 /* 2 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef RK3288_DEF_H 8 #define RK3288_DEF_H 9 10 /* Special value used to verify platform parameters from BL2 to BL31 */ 11 #define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 12 13 #define SIZE_K(n) ((n) * 1024) 14 #define SIZE_M(n) ((n) * 1024 * 1024) 15 16 #define SRAM_TEXT_LIMIT (4 * 1024) 17 #define SRAM_DATA_LIMIT (4 * 1024) 18 19 #define DDR_PCTL0_BASE 0xff610000 20 #define DDR_PCTL0_SIZE SIZE_K(64) 21 22 #define DDR_PHY0_BASE 0xff620000 23 #define DDR_PHY0_SIZE SIZE_K(64) 24 25 #define DDR_PCTL1_BASE 0xff630000 26 #define DDR_PCTL1_SIZE SIZE_K(64) 27 28 #define DDR_PHY1_BASE 0xff640000 29 #define DDR_PHY1_SIZE SIZE_K(64) 30 31 #define UART_DBG_BASE 0xff690000 32 #define UART_DBG_SIZE SIZE_K(64) 33 34 /* 96k instead of 64k? */ 35 #define SRAM_BASE 0xff700000 36 #define SRAM_SIZE SIZE_K(64) 37 38 #define PMUSRAM_BASE 0xff720000 39 #define PMUSRAM_SIZE SIZE_K(4) 40 #define PMUSRAM_RSIZE SIZE_K(4) 41 42 #define PMU_BASE 0xff730000 43 #define PMU_SIZE SIZE_K(64) 44 45 #define SGRF_BASE 0xff740000 46 #define SGRF_SIZE SIZE_K(64) 47 48 #define CRU_BASE 0xff760000 49 #define CRU_SIZE SIZE_K(64) 50 51 #define GRF_BASE 0xff770000 52 #define GRF_SIZE SIZE_K(64) 53 54 /* timer 6+7 can be set as secure in SGRF */ 55 #define STIME_BASE 0xff810000 56 #define STIME_SIZE SIZE_K(64) 57 58 #define SERVICE_BUS_BASE 0xffac0000 59 #define SERVICE_BUS_SIZE SIZE_K(64) 60 61 #define TZPC_BASE 0xffb00000 62 #define TZPC_SIZE SIZE_K(64) 63 64 #define GIC400_BASE 0xffc00000 65 #define GIC400_SIZE SIZE_K(64) 66 67 #define CORE_AXI_BUS_BASE 0xffd00000 68 #define CORE_AXI_BUS_SIZE SIZE_M(1) 69 70 #define COLD_BOOT_BASE 0xffff0000 71 /************************************************************************** 72 * UART related constants 73 **************************************************************************/ 74 #define RK3288_UART2_BASE UART_DBG_BASE 75 #define RK3288_BAUDRATE 115200 76 #define RK3288_UART_CLOCK 24000000 77 78 /****************************************************************************** 79 * System counter frequency related constants 80 ******************************************************************************/ 81 #define SYS_COUNTER_FREQ_IN_TICKS 24000000 82 83 /****************************************************************************** 84 * GIC-400 & interrupt handling related constants 85 ******************************************************************************/ 86 87 /* Base rk_platform compatible GIC memory map */ 88 #define RK3288_GICD_BASE (GIC400_BASE + 0x1000) 89 #define RK3288_GICC_BASE (GIC400_BASE + 0x2000) 90 #define RK3288_GICR_BASE 0 /* no GICR in GIC-400 */ 91 92 /****************************************************************************** 93 * sgi, ppi 94 ******************************************************************************/ 95 #define RK_IRQ_SEC_PHY_TIMER 29 96 97 /* what are these, and are they present on rk3288? */ 98 #define RK_IRQ_SEC_SGI_0 8 99 #define RK_IRQ_SEC_SGI_1 9 100 #define RK_IRQ_SEC_SGI_2 10 101 #define RK_IRQ_SEC_SGI_3 11 102 #define RK_IRQ_SEC_SGI_4 12 103 #define RK_IRQ_SEC_SGI_5 13 104 #define RK_IRQ_SEC_SGI_6 14 105 #define RK_IRQ_SEC_SGI_7 15 106 107 /* 108 * Define a list of Group 0 interrupts. 109 */ 110 #define PLAT_RK_GICV2_G0_IRQS \ 111 INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ 112 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), \ 113 INTR_PROP_DESC(RK_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ 114 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL) 115 116 #endif /* RK3288_DEF_H */ 117