1*780e3f24SHeiko Stuebner /* 2*780e3f24SHeiko Stuebner * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 3*780e3f24SHeiko Stuebner * 4*780e3f24SHeiko Stuebner * SPDX-License-Identifier: BSD-3-Clause 5*780e3f24SHeiko Stuebner */ 6*780e3f24SHeiko Stuebner 7*780e3f24SHeiko Stuebner #ifndef PLATFORM_DEF_H 8*780e3f24SHeiko Stuebner #define PLATFORM_DEF_H 9*780e3f24SHeiko Stuebner 10*780e3f24SHeiko Stuebner #include <arch.h> 11*780e3f24SHeiko Stuebner #include <lib/utils_def.h> 12*780e3f24SHeiko Stuebner #include <plat/common/common_def.h> 13*780e3f24SHeiko Stuebner 14*780e3f24SHeiko Stuebner #include <bl32_param.h> 15*780e3f24SHeiko Stuebner #include <rk3288_def.h> 16*780e3f24SHeiko Stuebner 17*780e3f24SHeiko Stuebner /******************************************************************************* 18*780e3f24SHeiko Stuebner * Platform binary types for linking 19*780e3f24SHeiko Stuebner ******************************************************************************/ 20*780e3f24SHeiko Stuebner #define PLATFORM_LINKER_FORMAT "elf32-littlearm" 21*780e3f24SHeiko Stuebner #define PLATFORM_LINKER_ARCH arm 22*780e3f24SHeiko Stuebner 23*780e3f24SHeiko Stuebner /******************************************************************************* 24*780e3f24SHeiko Stuebner * Generic platform constants 25*780e3f24SHeiko Stuebner ******************************************************************************/ 26*780e3f24SHeiko Stuebner 27*780e3f24SHeiko Stuebner /* Size of cacheable stacks */ 28*780e3f24SHeiko Stuebner #if defined(IMAGE_BL1) 29*780e3f24SHeiko Stuebner #define PLATFORM_STACK_SIZE 0x440 30*780e3f24SHeiko Stuebner #elif defined(IMAGE_BL2) 31*780e3f24SHeiko Stuebner #define PLATFORM_STACK_SIZE 0x400 32*780e3f24SHeiko Stuebner #elif defined(IMAGE_BL32) 33*780e3f24SHeiko Stuebner #define PLATFORM_STACK_SIZE 0x800 34*780e3f24SHeiko Stuebner #endif 35*780e3f24SHeiko Stuebner 36*780e3f24SHeiko Stuebner #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 37*780e3f24SHeiko Stuebner 38*780e3f24SHeiko Stuebner #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 39*780e3f24SHeiko Stuebner #define PLATFORM_SYSTEM_COUNT 1 40*780e3f24SHeiko Stuebner #define PLATFORM_CLUSTER_COUNT 1 41*780e3f24SHeiko Stuebner #define PLATFORM_CLUSTER0_CORE_COUNT 4 42*780e3f24SHeiko Stuebner #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 43*780e3f24SHeiko Stuebner #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 44*780e3f24SHeiko Stuebner #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 45*780e3f24SHeiko Stuebner PLATFORM_CLUSTER_COUNT + \ 46*780e3f24SHeiko Stuebner PLATFORM_CORE_COUNT) 47*780e3f24SHeiko Stuebner 48*780e3f24SHeiko Stuebner #define PLAT_RK_CLST_TO_CPUID_SHIFT 6 49*780e3f24SHeiko Stuebner 50*780e3f24SHeiko Stuebner #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 51*780e3f24SHeiko Stuebner 52*780e3f24SHeiko Stuebner /* 53*780e3f24SHeiko Stuebner * This macro defines the deepest retention state possible. A higher state 54*780e3f24SHeiko Stuebner * id will represent an invalid or a power down state. 55*780e3f24SHeiko Stuebner */ 56*780e3f24SHeiko Stuebner #define PLAT_MAX_RET_STATE U(1) 57*780e3f24SHeiko Stuebner 58*780e3f24SHeiko Stuebner /* 59*780e3f24SHeiko Stuebner * This macro defines the deepest power down states possible. Any state ID 60*780e3f24SHeiko Stuebner * higher than this is invalid. 61*780e3f24SHeiko Stuebner */ 62*780e3f24SHeiko Stuebner #define PLAT_MAX_OFF_STATE U(2) 63*780e3f24SHeiko Stuebner 64*780e3f24SHeiko Stuebner /******************************************************************************* 65*780e3f24SHeiko Stuebner * Platform specific page table and MMU setup constants 66*780e3f24SHeiko Stuebner ******************************************************************************/ 67*780e3f24SHeiko Stuebner #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 68*780e3f24SHeiko Stuebner #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 69*780e3f24SHeiko Stuebner #define MAX_XLAT_TABLES 8 70*780e3f24SHeiko Stuebner #define MAX_MMAP_REGIONS 18 71*780e3f24SHeiko Stuebner 72*780e3f24SHeiko Stuebner /******************************************************************************* 73*780e3f24SHeiko Stuebner * Declarations and constants to access the mailboxes safely. Each mailbox is 74*780e3f24SHeiko Stuebner * aligned on the biggest cache line size in the platform. This is known only 75*780e3f24SHeiko Stuebner * to the platform as it might have a combination of integrated and external 76*780e3f24SHeiko Stuebner * caches. Such alignment ensures that two maiboxes do not sit on the same cache 77*780e3f24SHeiko Stuebner * line at any cache level. They could belong to different cpus/clusters & 78*780e3f24SHeiko Stuebner * get written while being protected by different locks causing corruption of 79*780e3f24SHeiko Stuebner * a valid mailbox address. 80*780e3f24SHeiko Stuebner ******************************************************************************/ 81*780e3f24SHeiko Stuebner #define CACHE_WRITEBACK_SHIFT 6 82*780e3f24SHeiko Stuebner #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 83*780e3f24SHeiko Stuebner 84*780e3f24SHeiko Stuebner /* 85*780e3f24SHeiko Stuebner * Define GICD and GICC and GICR base 86*780e3f24SHeiko Stuebner */ 87*780e3f24SHeiko Stuebner #define PLAT_RK_GICD_BASE RK3288_GICD_BASE 88*780e3f24SHeiko Stuebner #define PLAT_RK_GICC_BASE RK3288_GICC_BASE 89*780e3f24SHeiko Stuebner 90*780e3f24SHeiko Stuebner #define PLAT_RK_UART_BASE RK3288_UART2_BASE 91*780e3f24SHeiko Stuebner #define PLAT_RK_UART_CLOCK RK3288_UART_CLOCK 92*780e3f24SHeiko Stuebner #define PLAT_RK_UART_BAUDRATE RK3288_BAUDRATE 93*780e3f24SHeiko Stuebner 94*780e3f24SHeiko Stuebner /* ClusterId is always 0x5 on rk3288, filter it */ 95*780e3f24SHeiko Stuebner #define PLAT_RK_MPIDR_CLUSTER_MASK 0 96*780e3f24SHeiko Stuebner #define PLAT_RK_PRIMARY_CPU 0x0 97*780e3f24SHeiko Stuebner 98*780e3f24SHeiko Stuebner #define PSRAM_DO_DDR_RESUME 0 99*780e3f24SHeiko Stuebner #define PSRAM_CHECK_WAKEUP_CPU 0 100*780e3f24SHeiko Stuebner 101*780e3f24SHeiko Stuebner #endif /* PLATFORM_DEF_H */ 102