1010d6ae3SXiaoDong Huang /* 2010d6ae3SXiaoDong Huang * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3010d6ae3SXiaoDong Huang * 4010d6ae3SXiaoDong Huang * SPDX-License-Identifier: BSD-3-Clause 5010d6ae3SXiaoDong Huang */ 6010d6ae3SXiaoDong Huang 7010d6ae3SXiaoDong Huang #ifndef __PLATFORM_DEF_H__ 8010d6ae3SXiaoDong Huang #define __PLATFORM_DEF_H__ 9010d6ae3SXiaoDong Huang 10010d6ae3SXiaoDong Huang #include <arch.h> 11010d6ae3SXiaoDong Huang #include <common_def.h> 12010d6ae3SXiaoDong Huang #include <px30_def.h> 13010d6ae3SXiaoDong Huang 14010d6ae3SXiaoDong Huang #define DEBUG_XLAT_TABLE 0 15010d6ae3SXiaoDong Huang 16010d6ae3SXiaoDong Huang /******************************************************************************* 17010d6ae3SXiaoDong Huang * Platform binary types for linking 18010d6ae3SXiaoDong Huang ******************************************************************************/ 19010d6ae3SXiaoDong Huang #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 20010d6ae3SXiaoDong Huang #define PLATFORM_LINKER_ARCH aarch64 21010d6ae3SXiaoDong Huang 22010d6ae3SXiaoDong Huang /******************************************************************************* 23010d6ae3SXiaoDong Huang * Generic platform constants 24010d6ae3SXiaoDong Huang ******************************************************************************/ 25010d6ae3SXiaoDong Huang 26010d6ae3SXiaoDong Huang /* Size of cacheable stacks */ 27010d6ae3SXiaoDong Huang #if DEBUG_XLAT_TABLE 28010d6ae3SXiaoDong Huang #define PLATFORM_STACK_SIZE 0x800 29010d6ae3SXiaoDong Huang #elif IMAGE_BL1 30010d6ae3SXiaoDong Huang #define PLATFORM_STACK_SIZE 0x440 31010d6ae3SXiaoDong Huang #elif IMAGE_BL2 32010d6ae3SXiaoDong Huang #define PLATFORM_STACK_SIZE 0x400 33010d6ae3SXiaoDong Huang #elif IMAGE_BL31 34010d6ae3SXiaoDong Huang #define PLATFORM_STACK_SIZE 0x800 35010d6ae3SXiaoDong Huang #elif IMAGE_BL32 36010d6ae3SXiaoDong Huang #define PLATFORM_STACK_SIZE 0x440 37010d6ae3SXiaoDong Huang #endif 38010d6ae3SXiaoDong Huang 39010d6ae3SXiaoDong Huang #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 40010d6ae3SXiaoDong Huang 41010d6ae3SXiaoDong Huang #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 42010d6ae3SXiaoDong Huang #define PLATFORM_SYSTEM_COUNT 1 43010d6ae3SXiaoDong Huang #define PLATFORM_CLUSTER_COUNT 1 44010d6ae3SXiaoDong Huang #define PLATFORM_CLUSTER0_CORE_COUNT 4 45010d6ae3SXiaoDong Huang #define PLATFORM_CLUSTER1_CORE_COUNT 0 46010d6ae3SXiaoDong Huang #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 47010d6ae3SXiaoDong Huang PLATFORM_CLUSTER0_CORE_COUNT) 48010d6ae3SXiaoDong Huang 49010d6ae3SXiaoDong Huang #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 50010d6ae3SXiaoDong Huang PLATFORM_CLUSTER_COUNT + \ 51010d6ae3SXiaoDong Huang PLATFORM_CORE_COUNT) 52010d6ae3SXiaoDong Huang 53010d6ae3SXiaoDong Huang #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 54010d6ae3SXiaoDong Huang 55010d6ae3SXiaoDong Huang #define PLAT_RK_CLST_TO_CPUID_SHIFT 8 56010d6ae3SXiaoDong Huang 57010d6ae3SXiaoDong Huang /* 58010d6ae3SXiaoDong Huang * This macro defines the deepest retention state possible. A higher state 59010d6ae3SXiaoDong Huang * id will represent an invalid or a power down state. 60010d6ae3SXiaoDong Huang */ 61010d6ae3SXiaoDong Huang #define PLAT_MAX_RET_STATE 1 62010d6ae3SXiaoDong Huang 63010d6ae3SXiaoDong Huang /* 64010d6ae3SXiaoDong Huang * This macro defines the deepest power down states possible. Any state ID 65010d6ae3SXiaoDong Huang * higher than this is invalid. 66010d6ae3SXiaoDong Huang */ 67010d6ae3SXiaoDong Huang #define PLAT_MAX_OFF_STATE 2 68010d6ae3SXiaoDong Huang 69010d6ae3SXiaoDong Huang /******************************************************************************* 70010d6ae3SXiaoDong Huang * Platform memory map related constants 71010d6ae3SXiaoDong Huang ******************************************************************************/ 72*c6ee020eSHeiko Stuebner /* TF text, ro, rw, Size: 1MB */ 73010d6ae3SXiaoDong Huang #define TZRAM_BASE (0x0) 74*c6ee020eSHeiko Stuebner #define TZRAM_SIZE (0x100000) 75010d6ae3SXiaoDong Huang 76010d6ae3SXiaoDong Huang /******************************************************************************* 77010d6ae3SXiaoDong Huang * BL31 specific defines. 78010d6ae3SXiaoDong Huang ******************************************************************************/ 79010d6ae3SXiaoDong Huang /* 80010d6ae3SXiaoDong Huang * Put BL3-1 at the top of the Trusted RAM 81010d6ae3SXiaoDong Huang */ 820aad563cSKever Yang #define BL31_BASE (TZRAM_BASE + 0x40000) 83010d6ae3SXiaoDong Huang #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 84010d6ae3SXiaoDong Huang 85010d6ae3SXiaoDong Huang /******************************************************************************* 86010d6ae3SXiaoDong Huang * Platform specific page table and MMU setup constants 87010d6ae3SXiaoDong Huang ******************************************************************************/ 88010d6ae3SXiaoDong Huang #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 89010d6ae3SXiaoDong Huang #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 90010d6ae3SXiaoDong Huang #define ADDR_SPACE_SIZE (1ull << 32) 91010d6ae3SXiaoDong Huang #define MAX_XLAT_TABLES 8 92010d6ae3SXiaoDong Huang #define MAX_MMAP_REGIONS 27 93010d6ae3SXiaoDong Huang 94010d6ae3SXiaoDong Huang /******************************************************************************* 95010d6ae3SXiaoDong Huang * Declarations and constants to access the mailboxes safely. Each mailbox is 96010d6ae3SXiaoDong Huang * aligned on the biggest cache line size in the platform. This is known only 97010d6ae3SXiaoDong Huang * to the platform as it might have a combination of integrated and external 98010d6ae3SXiaoDong Huang * caches. Such alignment ensures that two maiboxes do not sit on the same cache 99010d6ae3SXiaoDong Huang * line at any cache level. They could belong to different cpus/clusters & 100010d6ae3SXiaoDong Huang * get written while being protected by different locks causing corruption of 101010d6ae3SXiaoDong Huang * a valid mailbox address. 102010d6ae3SXiaoDong Huang ******************************************************************************/ 103010d6ae3SXiaoDong Huang #define CACHE_WRITEBACK_SHIFT 6 104010d6ae3SXiaoDong Huang #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 105010d6ae3SXiaoDong Huang 106010d6ae3SXiaoDong Huang /* 107010d6ae3SXiaoDong Huang * Define GICD and GICC and GICR base 108010d6ae3SXiaoDong Huang */ 109010d6ae3SXiaoDong Huang #define PLAT_RK_GICD_BASE PX30_GICD_BASE 110010d6ae3SXiaoDong Huang #define PLAT_RK_GICC_BASE PX30_GICC_BASE 111010d6ae3SXiaoDong Huang 112010d6ae3SXiaoDong Huang #define PLAT_RK_UART_BASE PX30_UART_BASE 113010d6ae3SXiaoDong Huang #define PLAT_RK_UART_CLOCK PX30_UART_CLOCK 114010d6ae3SXiaoDong Huang #define PLAT_RK_UART_BAUDRATE PX30_BAUDRATE 115010d6ae3SXiaoDong Huang 116010d6ae3SXiaoDong Huang #define PLAT_RK_PRIMARY_CPU 0x0 117010d6ae3SXiaoDong Huang 118010d6ae3SXiaoDong Huang #endif /* __PLATFORM_DEF_H__ */ 119