1*010d6ae3SXiaoDong Huang /* 2*010d6ae3SXiaoDong Huang * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3*010d6ae3SXiaoDong Huang * 4*010d6ae3SXiaoDong Huang * SPDX-License-Identifier: BSD-3-Clause 5*010d6ae3SXiaoDong Huang */ 6*010d6ae3SXiaoDong Huang 7*010d6ae3SXiaoDong Huang #ifndef __PLATFORM_DEF_H__ 8*010d6ae3SXiaoDong Huang #define __PLATFORM_DEF_H__ 9*010d6ae3SXiaoDong Huang 10*010d6ae3SXiaoDong Huang #include <arch.h> 11*010d6ae3SXiaoDong Huang #include <common_def.h> 12*010d6ae3SXiaoDong Huang #include <px30_def.h> 13*010d6ae3SXiaoDong Huang 14*010d6ae3SXiaoDong Huang #define DEBUG_XLAT_TABLE 0 15*010d6ae3SXiaoDong Huang 16*010d6ae3SXiaoDong Huang /******************************************************************************* 17*010d6ae3SXiaoDong Huang * Platform binary types for linking 18*010d6ae3SXiaoDong Huang ******************************************************************************/ 19*010d6ae3SXiaoDong Huang #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 20*010d6ae3SXiaoDong Huang #define PLATFORM_LINKER_ARCH aarch64 21*010d6ae3SXiaoDong Huang 22*010d6ae3SXiaoDong Huang /******************************************************************************* 23*010d6ae3SXiaoDong Huang * Generic platform constants 24*010d6ae3SXiaoDong Huang ******************************************************************************/ 25*010d6ae3SXiaoDong Huang 26*010d6ae3SXiaoDong Huang /* Size of cacheable stacks */ 27*010d6ae3SXiaoDong Huang #if DEBUG_XLAT_TABLE 28*010d6ae3SXiaoDong Huang #define PLATFORM_STACK_SIZE 0x800 29*010d6ae3SXiaoDong Huang #elif IMAGE_BL1 30*010d6ae3SXiaoDong Huang #define PLATFORM_STACK_SIZE 0x440 31*010d6ae3SXiaoDong Huang #elif IMAGE_BL2 32*010d6ae3SXiaoDong Huang #define PLATFORM_STACK_SIZE 0x400 33*010d6ae3SXiaoDong Huang #elif IMAGE_BL31 34*010d6ae3SXiaoDong Huang #define PLATFORM_STACK_SIZE 0x800 35*010d6ae3SXiaoDong Huang #elif IMAGE_BL32 36*010d6ae3SXiaoDong Huang #define PLATFORM_STACK_SIZE 0x440 37*010d6ae3SXiaoDong Huang #endif 38*010d6ae3SXiaoDong Huang 39*010d6ae3SXiaoDong Huang #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 40*010d6ae3SXiaoDong Huang 41*010d6ae3SXiaoDong Huang #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 42*010d6ae3SXiaoDong Huang #define PLATFORM_SYSTEM_COUNT 1 43*010d6ae3SXiaoDong Huang #define PLATFORM_CLUSTER_COUNT 1 44*010d6ae3SXiaoDong Huang #define PLATFORM_CLUSTER0_CORE_COUNT 4 45*010d6ae3SXiaoDong Huang #define PLATFORM_CLUSTER1_CORE_COUNT 0 46*010d6ae3SXiaoDong Huang #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 47*010d6ae3SXiaoDong Huang PLATFORM_CLUSTER0_CORE_COUNT) 48*010d6ae3SXiaoDong Huang 49*010d6ae3SXiaoDong Huang #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 50*010d6ae3SXiaoDong Huang PLATFORM_CLUSTER_COUNT + \ 51*010d6ae3SXiaoDong Huang PLATFORM_CORE_COUNT) 52*010d6ae3SXiaoDong Huang 53*010d6ae3SXiaoDong Huang #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 54*010d6ae3SXiaoDong Huang 55*010d6ae3SXiaoDong Huang #define PLAT_RK_CLST_TO_CPUID_SHIFT 8 56*010d6ae3SXiaoDong Huang 57*010d6ae3SXiaoDong Huang /* 58*010d6ae3SXiaoDong Huang * This macro defines the deepest retention state possible. A higher state 59*010d6ae3SXiaoDong Huang * id will represent an invalid or a power down state. 60*010d6ae3SXiaoDong Huang */ 61*010d6ae3SXiaoDong Huang #define PLAT_MAX_RET_STATE 1 62*010d6ae3SXiaoDong Huang 63*010d6ae3SXiaoDong Huang /* 64*010d6ae3SXiaoDong Huang * This macro defines the deepest power down states possible. Any state ID 65*010d6ae3SXiaoDong Huang * higher than this is invalid. 66*010d6ae3SXiaoDong Huang */ 67*010d6ae3SXiaoDong Huang #define PLAT_MAX_OFF_STATE 2 68*010d6ae3SXiaoDong Huang 69*010d6ae3SXiaoDong Huang /******************************************************************************* 70*010d6ae3SXiaoDong Huang * Platform memory map related constants 71*010d6ae3SXiaoDong Huang ******************************************************************************/ 72*010d6ae3SXiaoDong Huang /* TF txet, ro, rw, Size: 512KB */ 73*010d6ae3SXiaoDong Huang #define TZRAM_BASE (0x0) 74*010d6ae3SXiaoDong Huang #define TZRAM_SIZE (0x80000) 75*010d6ae3SXiaoDong Huang 76*010d6ae3SXiaoDong Huang /******************************************************************************* 77*010d6ae3SXiaoDong Huang * BL31 specific defines. 78*010d6ae3SXiaoDong Huang ******************************************************************************/ 79*010d6ae3SXiaoDong Huang /* 80*010d6ae3SXiaoDong Huang * Put BL3-1 at the top of the Trusted RAM 81*010d6ae3SXiaoDong Huang */ 82*010d6ae3SXiaoDong Huang #define BL31_BASE (TZRAM_BASE + 0x10000) 83*010d6ae3SXiaoDong Huang #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 84*010d6ae3SXiaoDong Huang 85*010d6ae3SXiaoDong Huang /******************************************************************************* 86*010d6ae3SXiaoDong Huang * Platform specific page table and MMU setup constants 87*010d6ae3SXiaoDong Huang ******************************************************************************/ 88*010d6ae3SXiaoDong Huang #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 89*010d6ae3SXiaoDong Huang #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 90*010d6ae3SXiaoDong Huang #define ADDR_SPACE_SIZE (1ull << 32) 91*010d6ae3SXiaoDong Huang #define MAX_XLAT_TABLES 8 92*010d6ae3SXiaoDong Huang #define MAX_MMAP_REGIONS 27 93*010d6ae3SXiaoDong Huang 94*010d6ae3SXiaoDong Huang /******************************************************************************* 95*010d6ae3SXiaoDong Huang * Declarations and constants to access the mailboxes safely. Each mailbox is 96*010d6ae3SXiaoDong Huang * aligned on the biggest cache line size in the platform. This is known only 97*010d6ae3SXiaoDong Huang * to the platform as it might have a combination of integrated and external 98*010d6ae3SXiaoDong Huang * caches. Such alignment ensures that two maiboxes do not sit on the same cache 99*010d6ae3SXiaoDong Huang * line at any cache level. They could belong to different cpus/clusters & 100*010d6ae3SXiaoDong Huang * get written while being protected by different locks causing corruption of 101*010d6ae3SXiaoDong Huang * a valid mailbox address. 102*010d6ae3SXiaoDong Huang ******************************************************************************/ 103*010d6ae3SXiaoDong Huang #define CACHE_WRITEBACK_SHIFT 6 104*010d6ae3SXiaoDong Huang #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 105*010d6ae3SXiaoDong Huang 106*010d6ae3SXiaoDong Huang /* 107*010d6ae3SXiaoDong Huang * Define GICD and GICC and GICR base 108*010d6ae3SXiaoDong Huang */ 109*010d6ae3SXiaoDong Huang #define PLAT_RK_GICD_BASE PX30_GICD_BASE 110*010d6ae3SXiaoDong Huang #define PLAT_RK_GICC_BASE PX30_GICC_BASE 111*010d6ae3SXiaoDong Huang 112*010d6ae3SXiaoDong Huang #define PLAT_RK_UART_BASE PX30_UART_BASE 113*010d6ae3SXiaoDong Huang #define PLAT_RK_UART_CLOCK PX30_UART_CLOCK 114*010d6ae3SXiaoDong Huang #define PLAT_RK_UART_BAUDRATE PX30_BAUDRATE 115*010d6ae3SXiaoDong Huang 116*010d6ae3SXiaoDong Huang #define PLAT_RK_PRIMARY_CPU 0x0 117*010d6ae3SXiaoDong Huang 118*010d6ae3SXiaoDong Huang #endif /* __PLATFORM_DEF_H__ */ 119