1*010d6ae3SXiaoDong Huang/* 2*010d6ae3SXiaoDong Huang * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3*010d6ae3SXiaoDong Huang * 4*010d6ae3SXiaoDong Huang * SPDX-License-Identifier: BSD-3-Clause 5*010d6ae3SXiaoDong Huang */ 6*010d6ae3SXiaoDong Huang 7*010d6ae3SXiaoDong Huang#ifndef __ROCKCHIP_PLAT_LD_S__ 8*010d6ae3SXiaoDong Huang#define __ROCKCHIP_PLAT_LD_S__ 9*010d6ae3SXiaoDong Huang 10*010d6ae3SXiaoDong HuangMEMORY { 11*010d6ae3SXiaoDong Huang PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE 12*010d6ae3SXiaoDong Huang} 13*010d6ae3SXiaoDong Huang 14*010d6ae3SXiaoDong HuangSECTIONS 15*010d6ae3SXiaoDong Huang{ 16*010d6ae3SXiaoDong Huang . = PMUSRAM_BASE; 17*010d6ae3SXiaoDong Huang 18*010d6ae3SXiaoDong Huang /* 19*010d6ae3SXiaoDong Huang * pmu_cpuson_entrypoint request address 20*010d6ae3SXiaoDong Huang * align 64K when resume, so put it in the 21*010d6ae3SXiaoDong Huang * start of pmusram 22*010d6ae3SXiaoDong Huang */ 23*010d6ae3SXiaoDong Huang .pmusram : { 24*010d6ae3SXiaoDong Huang ASSERT(. == ALIGN(64 * 1024), 25*010d6ae3SXiaoDong Huang ".pmusram.entry request 64K aligned."); 26*010d6ae3SXiaoDong Huang KEEP(*(.pmusram.entry)) 27*010d6ae3SXiaoDong Huang 28*010d6ae3SXiaoDong Huang __bl31_pmusram_text_start = .; 29*010d6ae3SXiaoDong Huang *(.pmusram.text) 30*010d6ae3SXiaoDong Huang *(.pmusram.rodata) 31*010d6ae3SXiaoDong Huang __bl31_pmusram_text_end = .; 32*010d6ae3SXiaoDong Huang __bl31_pmusram_data_start = .; 33*010d6ae3SXiaoDong Huang *(.pmusram.data) 34*010d6ae3SXiaoDong Huang __bl31_pmusram_data_end = .; 35*010d6ae3SXiaoDong Huang } >PMUSRAM 36*010d6ae3SXiaoDong Huang} 37*010d6ae3SXiaoDong Huang 38*010d6ae3SXiaoDong Huang#endif /* __ROCKCHIP_PLAT_LD_S__ */ 39