1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <platform_def.h> 8 9 #include <arch_helpers.h> 10 #include <common/debug.h> 11 #include <drivers/console.h> 12 #include <drivers/delay_timer.h> 13 #include <lib/mmio.h> 14 15 #include <platform_def.h> 16 #include <pmu.h> 17 #include <px30_def.h> 18 #include <secure.h> 19 #include <soc.h> 20 #include <rockchip_sip_svc.h> 21 22 /* Aggregate of all devices in the first GB */ 23 #define PX30_DEV_RNG0_BASE 0xff000000 24 #define PX30_DEV_RNG0_SIZE 0x00ff0000 25 26 const mmap_region_t plat_rk_mmap[] = { 27 MAP_REGION_FLAT(PX30_DEV_RNG0_BASE, PX30_DEV_RNG0_SIZE, 28 MT_DEVICE | MT_RW | MT_SECURE), 29 MAP_REGION_FLAT(SHARE_MEM_BASE, SHARE_MEM_SIZE, 30 MT_DEVICE | MT_RW | MT_SECURE), 31 MAP_REGION_FLAT(DDR_PARAM_BASE, DDR_PARAM_SIZE, 32 MT_DEVICE | MT_RW | MT_SECURE), 33 { 0 } 34 }; 35 36 /* The RockChip power domain tree descriptor */ 37 const unsigned char rockchip_power_domain_tree_desc[] = { 38 /* No of root nodes */ 39 PLATFORM_SYSTEM_COUNT, 40 /* No of children for the root node */ 41 PLATFORM_CLUSTER_COUNT, 42 /* No of children for the first cluster node */ 43 PLATFORM_CLUSTER0_CORE_COUNT, 44 }; 45 46 void clk_gate_con_save(uint32_t *clkgt_save) 47 { 48 uint32_t i, j; 49 50 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) 51 clkgt_save[i] = 52 mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(i)); 53 j = i; 54 for (i = 0; i < CRU_PMU_CLKGATE_CON_CNT; i++, j++) 55 clkgt_save[j] = 56 mmio_read_32(PMUCRU_BASE + CRU_PMU_CLKGATES_CON(i)); 57 } 58 59 void clk_gate_con_restore(uint32_t *clkgt_save) 60 { 61 uint32_t i, j; 62 63 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) 64 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), 65 WITH_16BITS_WMSK(clkgt_save[i])); 66 67 j = i; 68 for (i = 0; i < CRU_PMU_CLKGATE_CON_CNT; i++, j++) 69 mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATES_CON(i), 70 WITH_16BITS_WMSK(clkgt_save[j])); 71 } 72 73 void clk_gate_con_disable(void) 74 { 75 uint32_t i; 76 77 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) 78 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), 79 0xffff0000); 80 81 for (i = 0; i < CRU_PMU_CLKGATE_CON_CNT; i++) 82 mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATES_CON(i), 83 0xffff0000); 84 } 85 86 static void soc_reset_config_all(void) 87 { 88 uint32_t tmp; 89 90 /* tsadc and wdt can trigger a first rst */ 91 tmp = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON); 92 tmp |= CRU_GLB_RST_TSADC_FST | CRU_GLB_RST_WDT_FST; 93 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, tmp); 94 return; 95 tmp = mmio_read_32(PMUGRF_BASE + PMUGRF_SOC_CON(3)); 96 tmp &= ~(PMUGRF_FAILSAFE_SHTDN_TSADC | PMUGRF_FAILSAFE_SHTDN_WDT); 97 mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(3), tmp); 98 99 /* wdt pin rst eable */ 100 mmio_write_32(GRF_BASE + GRF_SOC_CON(2), 101 BIT_WITH_WMSK(GRF_SOC_CON2_NSWDT_RST_EN)); 102 } 103 104 void px30_soc_reset_config(void) 105 { 106 uint32_t tmp; 107 108 /* enable soc ip rst hold time cfg */ 109 tmp = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON); 110 tmp |= BIT(CRU_GLB_RST_TSADC_EXT) | BIT(CRU_GLB_RST_WDT_EXT); 111 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, tmp); 112 /* soc ip rst hold time, 24m */ 113 tmp = mmio_read_32(CRU_BASE + CRU_GLB_CNT_TH); 114 tmp &= ~CRU_GLB_CNT_RST_MSK; 115 tmp |= (CRU_GLB_CNT_RST_1MS / 2); 116 mmio_write_32(CRU_BASE + CRU_GLB_CNT_TH, tmp); 117 118 mmio_write_32(PMUSGRF_BASE + PMUSGRF_SOC_CON(0), 119 BIT_WITH_WMSK(PMUSGRF_RSTOUT_FST) | 120 BIT_WITH_WMSK(PMUSGRF_RSTOUT_TSADC) | 121 BIT_WITH_WMSK(PMUSGRF_RSTOUT_WDT)); 122 123 /* rst_out pulse time */ 124 mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(2), 125 PMUGRF_SOC_CON2_MAX_341US | PMUGRF_SOC_CON2_US_WMSK); 126 127 soc_reset_config_all(); 128 } 129 130 void plat_rockchip_soc_init(void) 131 { 132 secure_timer_init(); 133 sgrf_init(); 134 } 135