1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <ddr_parameter.h> 9 #include <plat_private.h> 10 #include <secure.h> 11 #include <px30_def.h> 12 13 /** 14 * There are 8 regions for DDR security control 15 * @rgn - the DDR regions 0 ~ 7 which are can be configured. 16 * @st - start address to set as secure 17 * @sz - length of area to set as secure 18 * The internal unit is megabytes, so memory areas need to be aligned 19 * to megabyte borders. 20 */ 21 static void secure_ddr_region(uint32_t rgn, 22 uintptr_t st, size_t sz) 23 { 24 uintptr_t ed = st + sz; 25 uintptr_t st_mb, ed_mb; 26 uint32_t val; 27 28 assert(rgn <= 7); 29 assert(st < ed); 30 31 /* check aligned 1MB */ 32 assert(st % SIZE_M(1) == 0); 33 assert(ed % SIZE_M(1) == 0); 34 35 st_mb = st / SIZE_M(1); 36 ed_mb = ed / SIZE_M(1); 37 38 /* map top and base */ 39 mmio_write_32(FIREWALL_DDR_BASE + 40 FIREWALL_DDR_FW_DDR_RGN(rgn), 41 RG_MAP_SECURE(ed_mb, st_mb)); 42 43 /* enable secure */ 44 val = mmio_read_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_CON_REG); 45 val |= BIT(rgn); 46 mmio_write_32(FIREWALL_DDR_BASE + 47 FIREWALL_DDR_FW_DDR_CON_REG, val); 48 } 49 50 void secure_timer_init(void) 51 { 52 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, 53 TIMER_DIS); 54 55 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT0, 0xffffffff); 56 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT1, 0xffffffff); 57 58 /* auto reload & enable the timer */ 59 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, 60 TIMER_EN | TIMER_FMODE); 61 } 62 63 void sgrf_init(void) 64 { 65 #ifdef PLAT_RK_SECURE_DDR_MINILOADER 66 uint32_t i; 67 struct param_ddr_usage usg; 68 69 /* general secure regions */ 70 usg = ddr_region_usage_parse(DDR_PARAM_BASE, 71 PLAT_MAX_DDR_CAPACITY_MB); 72 73 /* region-0 for TF-A, region-1 for optional OP-TEE */ 74 assert(usg.s_nr < 7); 75 76 for (i = 0; i < usg.s_nr; i++) 77 secure_ddr_region(7 - i, usg.s_top[i], usg.s_base[i]); 78 #endif 79 80 /* secure the trustzone ram */ 81 secure_ddr_region(0, TZRAM_BASE, TZRAM_SIZE); 82 83 /* set all slave ip into no-secure, except stimer */ 84 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_SLV_S_ALL_NS); 85 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SLV_S_ALL_NS); 86 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SLV_S_ALL_NS); 87 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SLV_S_ALL_NS); 88 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(8), 0x00030000); 89 90 /* set master crypto to no-secure, dcf to secure */ 91 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), 0x000f0003); 92 93 /* set DMAC into no-secure */ 94 mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(0), DMA_IRQ_BOOT_NS); 95 mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(1), DMA_PERI_CH_NS_15_0); 96 mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(2), DMA_PERI_CH_NS_19_16); 97 mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(3), DMA_MANAGER_BOOT_NS); 98 99 /* soft reset dma before use */ 100 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_REQ); 101 udelay(5); 102 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_RLS); 103 } 104