1d2483afaSHeiko Stuebner /* 2d2483afaSHeiko Stuebner * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3d2483afaSHeiko Stuebner * 4d2483afaSHeiko Stuebner * SPDX-License-Identifier: BSD-3-Clause 5d2483afaSHeiko Stuebner */ 6d2483afaSHeiko Stuebner 7*f55ef85eSHeiko Stuebner #include <assert.h> 8d2483afaSHeiko Stuebner #include <ddr_parameter.h> 9*f55ef85eSHeiko Stuebner #include <plat_private.h> 10d2483afaSHeiko Stuebner #include <secure.h> 11d2483afaSHeiko Stuebner #include <px30_def.h> 12d2483afaSHeiko Stuebner 13*f55ef85eSHeiko Stuebner /** 14*f55ef85eSHeiko Stuebner * There are 8 regions for DDR security control 15*f55ef85eSHeiko Stuebner * @rgn - the DDR regions 0 ~ 7 which are can be configured. 16*f55ef85eSHeiko Stuebner * @st - start address to set as secure 17*f55ef85eSHeiko Stuebner * @sz - length of area to set as secure 18*f55ef85eSHeiko Stuebner * The internal unit is megabytes, so memory areas need to be aligned 19*f55ef85eSHeiko Stuebner * to megabyte borders. 20*f55ef85eSHeiko Stuebner */ 21*f55ef85eSHeiko Stuebner static void secure_ddr_region(uint32_t rgn, 22*f55ef85eSHeiko Stuebner uintptr_t st, size_t sz) 23*f55ef85eSHeiko Stuebner { 24*f55ef85eSHeiko Stuebner uintptr_t ed = st + sz; 25*f55ef85eSHeiko Stuebner uintptr_t st_mb, ed_mb; 26*f55ef85eSHeiko Stuebner uint32_t val; 27*f55ef85eSHeiko Stuebner 28*f55ef85eSHeiko Stuebner assert(rgn <= 7); 29*f55ef85eSHeiko Stuebner assert(st < ed); 30*f55ef85eSHeiko Stuebner 31*f55ef85eSHeiko Stuebner /* check aligned 1MB */ 32*f55ef85eSHeiko Stuebner assert(st % SIZE_M(1) == 0); 33*f55ef85eSHeiko Stuebner assert(ed % SIZE_M(1) == 0); 34*f55ef85eSHeiko Stuebner 35*f55ef85eSHeiko Stuebner st_mb = st / SIZE_M(1); 36*f55ef85eSHeiko Stuebner ed_mb = ed / SIZE_M(1); 37*f55ef85eSHeiko Stuebner 38*f55ef85eSHeiko Stuebner /* map top and base */ 39*f55ef85eSHeiko Stuebner mmio_write_32(FIREWALL_DDR_BASE + 40*f55ef85eSHeiko Stuebner FIREWALL_DDR_FW_DDR_RGN(rgn), 41*f55ef85eSHeiko Stuebner RG_MAP_SECURE(ed_mb, st_mb)); 42*f55ef85eSHeiko Stuebner 43*f55ef85eSHeiko Stuebner /* enable secure */ 44*f55ef85eSHeiko Stuebner val = mmio_read_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_CON_REG); 45*f55ef85eSHeiko Stuebner val |= BIT(rgn); 46*f55ef85eSHeiko Stuebner mmio_write_32(FIREWALL_DDR_BASE + 47*f55ef85eSHeiko Stuebner FIREWALL_DDR_FW_DDR_CON_REG, val); 48*f55ef85eSHeiko Stuebner } 49*f55ef85eSHeiko Stuebner 50d2483afaSHeiko Stuebner void secure_timer_init(void) 51d2483afaSHeiko Stuebner { 52d2483afaSHeiko Stuebner mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, 53d2483afaSHeiko Stuebner TIMER_DIS); 54d2483afaSHeiko Stuebner 55d2483afaSHeiko Stuebner mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT0, 0xffffffff); 56d2483afaSHeiko Stuebner mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT1, 0xffffffff); 57d2483afaSHeiko Stuebner 58d2483afaSHeiko Stuebner /* auto reload & enable the timer */ 59d2483afaSHeiko Stuebner mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, 60d2483afaSHeiko Stuebner TIMER_EN | TIMER_FMODE); 61d2483afaSHeiko Stuebner } 62d2483afaSHeiko Stuebner 63d2483afaSHeiko Stuebner void sgrf_init(void) 64d2483afaSHeiko Stuebner { 65*f55ef85eSHeiko Stuebner uint32_t i; 66d2483afaSHeiko Stuebner struct param_ddr_usage usg; 67d2483afaSHeiko Stuebner 68d2483afaSHeiko Stuebner /* general secure regions */ 69d2483afaSHeiko Stuebner usg = ddr_region_usage_parse(DDR_PARAM_BASE, 70d2483afaSHeiko Stuebner PLAT_MAX_DDR_CAPACITY_MB); 71d2483afaSHeiko Stuebner 72*f55ef85eSHeiko Stuebner /* region-0 for TF-A, region-1 for optional OP-TEE */ 73*f55ef85eSHeiko Stuebner assert(usg.s_nr < 7); 74*f55ef85eSHeiko Stuebner 75*f55ef85eSHeiko Stuebner for (i = 0; i < usg.s_nr; i++) 76*f55ef85eSHeiko Stuebner secure_ddr_region(7 - i, usg.s_top[i], usg.s_base[i]); 77*f55ef85eSHeiko Stuebner 78*f55ef85eSHeiko Stuebner /* secure the trustzone ram */ 79*f55ef85eSHeiko Stuebner secure_ddr_region(0, TZRAM_BASE, TZRAM_SIZE); 80d2483afaSHeiko Stuebner 81d2483afaSHeiko Stuebner /* set all slave ip into no-secure, except stimer */ 82d2483afaSHeiko Stuebner mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_SLV_S_ALL_NS); 83d2483afaSHeiko Stuebner mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SLV_S_ALL_NS); 84d2483afaSHeiko Stuebner mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SLV_S_ALL_NS); 85d2483afaSHeiko Stuebner mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SLV_S_ALL_NS); 86d2483afaSHeiko Stuebner mmio_write_32(SGRF_BASE + SGRF_SOC_CON(8), 0x00030000); 87d2483afaSHeiko Stuebner 88d2483afaSHeiko Stuebner /* set master crypto to no-secure, dcf to secure */ 89d2483afaSHeiko Stuebner mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), 0x000f0003); 90d2483afaSHeiko Stuebner 91d2483afaSHeiko Stuebner /* set DMAC into no-secure */ 92d2483afaSHeiko Stuebner mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(0), DMA_IRQ_BOOT_NS); 93d2483afaSHeiko Stuebner mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(1), DMA_PERI_CH_NS_15_0); 94d2483afaSHeiko Stuebner mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(2), DMA_PERI_CH_NS_19_16); 95d2483afaSHeiko Stuebner mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(3), DMA_MANAGER_BOOT_NS); 96d2483afaSHeiko Stuebner 97d2483afaSHeiko Stuebner /* soft reset dma before use */ 98d2483afaSHeiko Stuebner mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_REQ); 99d2483afaSHeiko Stuebner udelay(5); 100d2483afaSHeiko Stuebner mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_RLS); 101d2483afaSHeiko Stuebner } 102