1*d2483afaSHeiko Stuebner /* 2*d2483afaSHeiko Stuebner * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3*d2483afaSHeiko Stuebner * 4*d2483afaSHeiko Stuebner * SPDX-License-Identifier: BSD-3-Clause 5*d2483afaSHeiko Stuebner */ 6*d2483afaSHeiko Stuebner 7*d2483afaSHeiko Stuebner #include <ddr_parameter.h> 8*d2483afaSHeiko Stuebner #include <secure.h> 9*d2483afaSHeiko Stuebner #include <px30_def.h> 10*d2483afaSHeiko Stuebner 11*d2483afaSHeiko Stuebner void secure_timer_init(void) 12*d2483afaSHeiko Stuebner { 13*d2483afaSHeiko Stuebner mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, 14*d2483afaSHeiko Stuebner TIMER_DIS); 15*d2483afaSHeiko Stuebner 16*d2483afaSHeiko Stuebner mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT0, 0xffffffff); 17*d2483afaSHeiko Stuebner mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT1, 0xffffffff); 18*d2483afaSHeiko Stuebner 19*d2483afaSHeiko Stuebner /* auto reload & enable the timer */ 20*d2483afaSHeiko Stuebner mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, 21*d2483afaSHeiko Stuebner TIMER_EN | TIMER_FMODE); 22*d2483afaSHeiko Stuebner } 23*d2483afaSHeiko Stuebner 24*d2483afaSHeiko Stuebner void sgrf_init(void) 25*d2483afaSHeiko Stuebner { 26*d2483afaSHeiko Stuebner uint32_t i, val; 27*d2483afaSHeiko Stuebner struct param_ddr_usage usg; 28*d2483afaSHeiko Stuebner 29*d2483afaSHeiko Stuebner /* general secure regions */ 30*d2483afaSHeiko Stuebner usg = ddr_region_usage_parse(DDR_PARAM_BASE, 31*d2483afaSHeiko Stuebner PLAT_MAX_DDR_CAPACITY_MB); 32*d2483afaSHeiko Stuebner for (i = 0; i < usg.s_nr; i++) { 33*d2483afaSHeiko Stuebner /* enable secure */ 34*d2483afaSHeiko Stuebner val = mmio_read_32(FIREWALL_DDR_BASE + 35*d2483afaSHeiko Stuebner FIREWALL_DDR_FW_DDR_CON_REG); 36*d2483afaSHeiko Stuebner val |= BIT(7 - i); 37*d2483afaSHeiko Stuebner mmio_write_32(FIREWALL_DDR_BASE + 38*d2483afaSHeiko Stuebner FIREWALL_DDR_FW_DDR_CON_REG, val); 39*d2483afaSHeiko Stuebner /* map top and base */ 40*d2483afaSHeiko Stuebner mmio_write_32(FIREWALL_DDR_BASE + 41*d2483afaSHeiko Stuebner FIREWALL_DDR_FW_DDR_RGN(7 - i), 42*d2483afaSHeiko Stuebner RG_MAP_SECURE(usg.s_top[i], usg.s_base[i])); 43*d2483afaSHeiko Stuebner } 44*d2483afaSHeiko Stuebner 45*d2483afaSHeiko Stuebner /* set ddr rgn0_top and rga0_top as 0 */ 46*d2483afaSHeiko Stuebner mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_RGN(0), 0x0); 47*d2483afaSHeiko Stuebner 48*d2483afaSHeiko Stuebner /* set all slave ip into no-secure, except stimer */ 49*d2483afaSHeiko Stuebner mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_SLV_S_ALL_NS); 50*d2483afaSHeiko Stuebner mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SLV_S_ALL_NS); 51*d2483afaSHeiko Stuebner mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SLV_S_ALL_NS); 52*d2483afaSHeiko Stuebner mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SLV_S_ALL_NS); 53*d2483afaSHeiko Stuebner mmio_write_32(SGRF_BASE + SGRF_SOC_CON(8), 0x00030000); 54*d2483afaSHeiko Stuebner 55*d2483afaSHeiko Stuebner /* set master crypto to no-secure, dcf to secure */ 56*d2483afaSHeiko Stuebner mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), 0x000f0003); 57*d2483afaSHeiko Stuebner 58*d2483afaSHeiko Stuebner /* set DMAC into no-secure */ 59*d2483afaSHeiko Stuebner mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(0), DMA_IRQ_BOOT_NS); 60*d2483afaSHeiko Stuebner mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(1), DMA_PERI_CH_NS_15_0); 61*d2483afaSHeiko Stuebner mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(2), DMA_PERI_CH_NS_19_16); 62*d2483afaSHeiko Stuebner mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(3), DMA_MANAGER_BOOT_NS); 63*d2483afaSHeiko Stuebner 64*d2483afaSHeiko Stuebner /* soft reset dma before use */ 65*d2483afaSHeiko Stuebner mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_REQ); 66*d2483afaSHeiko Stuebner udelay(5); 67*d2483afaSHeiko Stuebner mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_RLS); 68*d2483afaSHeiko Stuebner } 69