1 /* 2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <drivers/console.h> 15 #include <drivers/generic_delay_timer.h> 16 #include <drivers/ti/uart/uart_16550.h> 17 #include <lib/coreboot.h> 18 #include <lib/mmio.h> 19 #include <plat_private.h> 20 #include <plat/common/platform.h> 21 22 static entry_point_info_t bl33_ep_info; 23 24 /******************************************************************************* 25 * Return a pointer to the 'entry_point_info' structure of the next image for 26 * the security state specified. BL33 corresponds to the non-secure image type. 27 * A NULL pointer is returned if the image does not exist. 28 ******************************************************************************/ 29 entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) 30 { 31 entry_point_info_t *next_image_info; 32 33 next_image_info = &bl33_ep_info; 34 35 if (next_image_info->pc == 0U) { 36 return NULL; 37 } 38 39 return next_image_info; 40 } 41 42 #pragma weak params_early_setup 43 void params_early_setup(void *plat_param_from_bl2) 44 { 45 } 46 47 unsigned int plat_is_my_cpu_primary(void); 48 49 /******************************************************************************* 50 * Perform any BL32 specific platform actions. 51 ******************************************************************************/ 52 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, 53 u_register_t arg2, u_register_t arg3) 54 { 55 static console_16550_t console; 56 struct rockchip_bl31_params *arg_from_bl2 = (struct rockchip_bl31_params *) arg0; 57 void *plat_params_from_bl2 = (void *) arg1; 58 59 params_early_setup(plat_params_from_bl2); 60 61 #if COREBOOT 62 if (coreboot_serial.type) 63 console_16550_register(coreboot_serial.baseaddr, 64 coreboot_serial.input_hertz, 65 coreboot_serial.baud, 66 &console); 67 #else 68 console_16550_register(rockchip_get_uart_base(), PLAT_RK_UART_CLOCK, 69 PLAT_RK_UART_BAUDRATE, &console); 70 #endif 71 VERBOSE("sp_min_setup\n"); 72 73 /* Passing a NULL context is a critical programming error */ 74 assert(arg_from_bl2); 75 76 assert(arg_from_bl2->h.type == PARAM_BL31); 77 assert(arg_from_bl2->h.version >= VERSION_1); 78 79 bl33_ep_info = *arg_from_bl2->bl33_ep_info; 80 } 81 82 /******************************************************************************* 83 * Perform any sp_min platform setup code 84 ******************************************************************************/ 85 void sp_min_platform_setup(void) 86 { 87 generic_delay_timer_init(); 88 plat_rockchip_soc_init(); 89 90 /* Initialize the gic cpu and distributor interfaces */ 91 plat_rockchip_gic_driver_init(); 92 plat_rockchip_gic_init(); 93 plat_rockchip_pmu_init(); 94 } 95 96 /******************************************************************************* 97 * Perform the very early platform specific architectural setup here. At the 98 * moment this is only intializes the mmu in a quick and dirty way. 99 ******************************************************************************/ 100 void sp_min_plat_arch_setup(void) 101 { 102 plat_cci_init(); 103 plat_cci_enable(); 104 105 plat_configure_mmu_svc_mon(BL_CODE_BASE, 106 BL_COHERENT_RAM_END - BL_CODE_BASE, 107 BL_CODE_BASE, 108 BL_CODE_END, 109 BL_COHERENT_RAM_BASE, 110 BL_COHERENT_RAM_END); 111 } 112 113 void sp_min_plat_fiq_handler(uint32_t id) 114 { 115 VERBOSE("[sp_min] interrupt #%d\n", id); 116 } 117