1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <bl_common.h> 32 #include <gicv3.h> 33 #include <platform.h> 34 #include <platform_def.h> 35 36 /****************************************************************************** 37 * The following functions are defined as weak to allow a platform to override 38 * the way the GICv3 driver is initialised and used. 39 *****************************************************************************/ 40 #pragma weak plat_rockchip_gic_driver_init 41 #pragma weak plat_rockchip_gic_init 42 #pragma weak plat_rockchip_gic_cpuif_enable 43 #pragma weak plat_rockchip_gic_cpuif_disable 44 #pragma weak plat_rockchip_gic_pcpu_init 45 46 /* The GICv3 driver only needs to be initialized in EL3 */ 47 uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; 48 49 /* Array of Group1 secure interrupts to be configured by the gic driver */ 50 const unsigned int g1s_interrupt_array[] = { 51 PLAT_RK_G1S_IRQS 52 }; 53 54 /* Array of Group0 interrupts to be configured by the gic driver */ 55 const unsigned int g0_interrupt_array[] = { 56 PLAT_RK_G0_IRQS 57 }; 58 59 static unsigned int plat_rockchip_mpidr_to_core_pos(unsigned long mpidr) 60 { 61 return (unsigned int)plat_core_pos_by_mpidr(mpidr); 62 } 63 64 const gicv3_driver_data_t rockchip_gic_data = { 65 .gicd_base = PLAT_RK_GICD_BASE, 66 .gicr_base = PLAT_RK_GICR_BASE, 67 .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), 68 .g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array), 69 .g0_interrupt_array = g0_interrupt_array, 70 .g1s_interrupt_array = g1s_interrupt_array, 71 .rdistif_num = PLATFORM_CORE_COUNT, 72 .rdistif_base_addrs = rdistif_base_addrs, 73 .mpidr_to_core_pos = plat_rockchip_mpidr_to_core_pos, 74 }; 75 76 void plat_rockchip_gic_driver_init(void) 77 { 78 /* 79 * The GICv3 driver is initialized in EL3 and does not need 80 * to be initialized again in SEL1. This is because the S-EL1 81 * can use GIC system registers to manage interrupts and does 82 * not need GIC interface base addresses to be configured. 83 */ 84 #if IMAGE_BL31 85 gicv3_driver_init(&rockchip_gic_data); 86 #endif 87 } 88 89 /****************************************************************************** 90 * RockChip common helper to initialize the GIC. Only invoked 91 * by BL31 92 *****************************************************************************/ 93 void plat_rockchip_gic_init(void) 94 { 95 gicv3_distif_init(); 96 gicv3_rdistif_init(plat_my_core_pos()); 97 gicv3_cpuif_enable(plat_my_core_pos()); 98 } 99 100 /****************************************************************************** 101 * RockChip common helper to enable the GIC CPU interface 102 *****************************************************************************/ 103 void plat_rockchip_gic_cpuif_enable(void) 104 { 105 gicv3_cpuif_enable(plat_my_core_pos()); 106 } 107 108 /****************************************************************************** 109 * RockChip common helper to disable the GIC CPU interface 110 *****************************************************************************/ 111 void plat_rockchip_gic_cpuif_disable(void) 112 { 113 gicv3_cpuif_disable(plat_my_core_pos()); 114 } 115 116 /****************************************************************************** 117 * RockChip common helper to initialize the per-cpu redistributor interface 118 * in GICv3 119 *****************************************************************************/ 120 void plat_rockchip_gic_pcpu_init(void) 121 { 122 gicv3_rdistif_init(plat_my_core_pos()); 123 } 124