1 /* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <drivers/console.h> 15 #include <drivers/delay_timer.h> 16 #include <lib/psci/psci.h> 17 18 #include <plat_private.h> 19 20 /* Macros to read the rk power domain state */ 21 #define RK_CORE_PWR_STATE(state) \ 22 ((state)->pwr_domain_state[MPIDR_AFFLVL0]) 23 #define RK_CLUSTER_PWR_STATE(state) \ 24 ((state)->pwr_domain_state[MPIDR_AFFLVL1]) 25 #define RK_SYSTEM_PWR_STATE(state) \ 26 ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) 27 28 static uintptr_t rockchip_sec_entrypoint; 29 30 #pragma weak rockchip_soc_cores_pwr_dm_on 31 #pragma weak rockchip_soc_hlvl_pwr_dm_off 32 #pragma weak rockchip_soc_cores_pwr_dm_off 33 #pragma weak rockchip_soc_sys_pwr_dm_suspend 34 #pragma weak rockchip_soc_cores_pwr_dm_suspend 35 #pragma weak rockchip_soc_hlvl_pwr_dm_suspend 36 #pragma weak rockchip_soc_hlvl_pwr_dm_on_finish 37 #pragma weak rockchip_soc_cores_pwr_dm_on_finish 38 #pragma weak rockchip_soc_sys_pwr_dm_resume 39 #pragma weak rockchip_soc_hlvl_pwr_dm_resume 40 #pragma weak rockchip_soc_cores_pwr_dm_resume 41 #pragma weak rockchip_soc_soft_reset 42 #pragma weak rockchip_soc_system_off 43 #pragma weak rockchip_soc_sys_pd_pwr_dn_wfi 44 #pragma weak rockchip_soc_cores_pd_pwr_dn_wfi 45 46 int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint) 47 { 48 return PSCI_E_NOT_SUPPORTED; 49 } 50 51 int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl, 52 plat_local_state_t lvl_state) 53 { 54 return PSCI_E_NOT_SUPPORTED; 55 } 56 57 int rockchip_soc_cores_pwr_dm_off(void) 58 { 59 return PSCI_E_NOT_SUPPORTED; 60 } 61 62 int rockchip_soc_sys_pwr_dm_suspend(void) 63 { 64 return PSCI_E_NOT_SUPPORTED; 65 } 66 67 int rockchip_soc_cores_pwr_dm_suspend(void) 68 { 69 return PSCI_E_NOT_SUPPORTED; 70 } 71 72 int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl, 73 plat_local_state_t lvl_state) 74 { 75 return PSCI_E_NOT_SUPPORTED; 76 } 77 78 int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl, 79 plat_local_state_t lvl_state) 80 { 81 return PSCI_E_NOT_SUPPORTED; 82 } 83 84 int rockchip_soc_cores_pwr_dm_on_finish(void) 85 { 86 return PSCI_E_NOT_SUPPORTED; 87 } 88 89 int rockchip_soc_sys_pwr_dm_resume(void) 90 { 91 return PSCI_E_NOT_SUPPORTED; 92 } 93 94 int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl, 95 plat_local_state_t lvl_state) 96 { 97 return PSCI_E_NOT_SUPPORTED; 98 } 99 100 int rockchip_soc_cores_pwr_dm_resume(void) 101 { 102 return PSCI_E_NOT_SUPPORTED; 103 } 104 105 void __dead2 rockchip_soc_soft_reset(void) 106 { 107 while (1) 108 ; 109 } 110 111 void __dead2 rockchip_soc_system_off(void) 112 { 113 while (1) 114 ; 115 } 116 117 void __dead2 rockchip_soc_cores_pd_pwr_dn_wfi( 118 const psci_power_state_t *target_state) 119 { 120 psci_power_down_wfi(); 121 /* should never reach here */ 122 panic(); 123 } 124 125 void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void) 126 { 127 psci_power_down_wfi(); 128 /* should never reach here */ 129 panic(); 130 } 131 132 /******************************************************************************* 133 * Rockchip standard platform handler called to check the validity of the power 134 * state parameter. 135 ******************************************************************************/ 136 int rockchip_validate_power_state(unsigned int power_state, 137 psci_power_state_t *req_state) 138 { 139 int pstate = psci_get_pstate_type(power_state); 140 int pwr_lvl = psci_get_pstate_pwrlvl(power_state); 141 int i; 142 143 assert(req_state); 144 145 if (pwr_lvl > PLAT_MAX_PWR_LVL) 146 return PSCI_E_INVALID_PARAMS; 147 148 /* Sanity check the requested state */ 149 if (pstate == PSTATE_TYPE_STANDBY) { 150 /* 151 * It's probably to enter standby only on power level 0 152 * ignore any other power level. 153 */ 154 if (pwr_lvl != MPIDR_AFFLVL0) 155 return PSCI_E_INVALID_PARAMS; 156 157 req_state->pwr_domain_state[MPIDR_AFFLVL0] = 158 PLAT_MAX_RET_STATE; 159 } else { 160 for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++) 161 req_state->pwr_domain_state[i] = 162 PLAT_MAX_OFF_STATE; 163 164 for (i = (pwr_lvl + 1); i <= PLAT_MAX_PWR_LVL; i++) 165 req_state->pwr_domain_state[i] = 166 PLAT_MAX_RET_STATE; 167 } 168 169 /* We expect the 'state id' to be zero */ 170 if (psci_get_pstate_id(power_state)) 171 return PSCI_E_INVALID_PARAMS; 172 173 return PSCI_E_SUCCESS; 174 } 175 176 void rockchip_get_sys_suspend_power_state(psci_power_state_t *req_state) 177 { 178 int i; 179 180 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) 181 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 182 } 183 184 /******************************************************************************* 185 * RockChip handler called when a CPU is about to enter standby. 186 ******************************************************************************/ 187 void rockchip_cpu_standby(plat_local_state_t cpu_state) 188 { 189 u_register_t scr; 190 191 assert(cpu_state == PLAT_MAX_RET_STATE); 192 193 scr = read_scr_el3(); 194 /* Enable PhysicalIRQ bit for NS world to wake the CPU */ 195 write_scr_el3(scr | SCR_IRQ_BIT); 196 isb(); 197 dsb(); 198 wfi(); 199 200 /* 201 * Restore SCR to the original value, synchronisation of scr_el3 is 202 * done by eret while el3_exit to save some execution cycles. 203 */ 204 write_scr_el3(scr); 205 } 206 207 /******************************************************************************* 208 * RockChip handler called when a power domain is about to be turned on. The 209 * mpidr determines the CPU to be turned on. 210 ******************************************************************************/ 211 int rockchip_pwr_domain_on(u_register_t mpidr) 212 { 213 return rockchip_soc_cores_pwr_dm_on(mpidr, rockchip_sec_entrypoint); 214 } 215 216 /******************************************************************************* 217 * RockChip handler called when a power domain is about to be turned off. The 218 * target_state encodes the power state that each level should transition to. 219 ******************************************************************************/ 220 void rockchip_pwr_domain_off(const psci_power_state_t *target_state) 221 { 222 uint32_t lvl; 223 plat_local_state_t lvl_state; 224 int ret; 225 226 assert(RK_CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE); 227 228 plat_rockchip_gic_cpuif_disable(); 229 230 if (RK_CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) 231 plat_cci_disable(); 232 233 rockchip_soc_cores_pwr_dm_off(); 234 235 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { 236 lvl_state = target_state->pwr_domain_state[lvl]; 237 ret = rockchip_soc_hlvl_pwr_dm_off(lvl, lvl_state); 238 if (ret == PSCI_E_NOT_SUPPORTED) 239 break; 240 } 241 } 242 243 /******************************************************************************* 244 * RockChip handler called when a power domain is about to be suspended. The 245 * target_state encodes the power state that each level should transition to. 246 ******************************************************************************/ 247 void rockchip_pwr_domain_suspend(const psci_power_state_t *target_state) 248 { 249 uint32_t lvl; 250 plat_local_state_t lvl_state; 251 int ret; 252 253 if (RK_CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) 254 return; 255 256 /* Prevent interrupts from spuriously waking up this cpu */ 257 plat_rockchip_gic_cpuif_disable(); 258 259 if (RK_SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) 260 rockchip_soc_sys_pwr_dm_suspend(); 261 else 262 rockchip_soc_cores_pwr_dm_suspend(); 263 264 /* Perform the common cluster specific operations */ 265 if (RK_CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) 266 plat_cci_disable(); 267 268 if (RK_SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) 269 return; 270 271 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { 272 lvl_state = target_state->pwr_domain_state[lvl]; 273 ret = rockchip_soc_hlvl_pwr_dm_suspend(lvl, lvl_state); 274 if (ret == PSCI_E_NOT_SUPPORTED) 275 break; 276 } 277 } 278 279 /******************************************************************************* 280 * RockChip handler called when a power domain has just been powered on after 281 * being turned off earlier. The target_state encodes the low power state that 282 * each level has woken up from. 283 ******************************************************************************/ 284 void rockchip_pwr_domain_on_finish(const psci_power_state_t *target_state) 285 { 286 uint32_t lvl; 287 plat_local_state_t lvl_state; 288 int ret; 289 290 assert(RK_CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE); 291 292 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { 293 lvl_state = target_state->pwr_domain_state[lvl]; 294 ret = rockchip_soc_hlvl_pwr_dm_on_finish(lvl, lvl_state); 295 if (ret == PSCI_E_NOT_SUPPORTED) 296 break; 297 } 298 299 rockchip_soc_cores_pwr_dm_on_finish(); 300 301 /* Perform the common cluster specific operations */ 302 if (RK_CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { 303 /* Enable coherency if this cluster was off */ 304 plat_cci_enable(); 305 } 306 307 /* Enable the gic cpu interface */ 308 plat_rockchip_gic_pcpu_init(); 309 310 /* Program the gic per-cpu distributor or re-distributor interface */ 311 plat_rockchip_gic_cpuif_enable(); 312 } 313 314 /******************************************************************************* 315 * RockChip handler called when a power domain has just been powered on after 316 * having been suspended earlier. The target_state encodes the low power state 317 * that each level has woken up from. 318 * TODO: At the moment we reuse the on finisher and reinitialize the secure 319 * context. Need to implement a separate suspend finisher. 320 ******************************************************************************/ 321 void rockchip_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 322 { 323 uint32_t lvl; 324 plat_local_state_t lvl_state; 325 int ret; 326 327 /* Nothing to be done on waking up from retention from CPU level */ 328 if (RK_CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) 329 return; 330 331 if (RK_SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { 332 rockchip_soc_sys_pwr_dm_resume(); 333 goto comm_finish; 334 } 335 336 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { 337 lvl_state = target_state->pwr_domain_state[lvl]; 338 ret = rockchip_soc_hlvl_pwr_dm_resume(lvl, lvl_state); 339 if (ret == PSCI_E_NOT_SUPPORTED) 340 break; 341 } 342 343 rockchip_soc_cores_pwr_dm_resume(); 344 345 /* 346 * Program the gic per-cpu distributor or re-distributor interface. 347 * For sys power domain operation, resuming of the gic needs to operate 348 * in rockchip_soc_sys_pwr_dm_resume(), according to the sys power mode 349 * implements. 350 */ 351 plat_rockchip_gic_cpuif_enable(); 352 353 comm_finish: 354 /* Perform the common cluster specific operations */ 355 if (RK_CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { 356 /* Enable coherency if this cluster was off */ 357 plat_cci_enable(); 358 } 359 } 360 361 /******************************************************************************* 362 * RockChip handlers to reboot the system 363 ******************************************************************************/ 364 static void __dead2 rockchip_system_reset(void) 365 { 366 rockchip_soc_soft_reset(); 367 } 368 369 /******************************************************************************* 370 * RockChip handlers to power off the system 371 ******************************************************************************/ 372 static void __dead2 rockchip_system_poweroff(void) 373 { 374 rockchip_soc_system_off(); 375 } 376 377 static void __dead2 rockchip_pd_pwr_down_wfi( 378 const psci_power_state_t *target_state) 379 { 380 if (RK_SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) 381 rockchip_soc_sys_pd_pwr_dn_wfi(); 382 else 383 rockchip_soc_cores_pd_pwr_dn_wfi(target_state); 384 } 385 386 /******************************************************************************* 387 * Export the platform handlers via plat_rockchip_psci_pm_ops. The rockchip 388 * standard 389 * platform layer will take care of registering the handlers with PSCI. 390 ******************************************************************************/ 391 const plat_psci_ops_t plat_rockchip_psci_pm_ops = { 392 .cpu_standby = rockchip_cpu_standby, 393 .pwr_domain_on = rockchip_pwr_domain_on, 394 .pwr_domain_off = rockchip_pwr_domain_off, 395 .pwr_domain_suspend = rockchip_pwr_domain_suspend, 396 .pwr_domain_on_finish = rockchip_pwr_domain_on_finish, 397 .pwr_domain_suspend_finish = rockchip_pwr_domain_suspend_finish, 398 .pwr_domain_pwr_down = rockchip_pd_pwr_down_wfi, 399 .system_reset = rockchip_system_reset, 400 .system_off = rockchip_system_poweroff, 401 .validate_power_state = rockchip_validate_power_state, 402 .get_sys_suspend_power_state = rockchip_get_sys_suspend_power_state 403 }; 404 405 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 406 const plat_psci_ops_t **psci_ops) 407 { 408 *psci_ops = &plat_rockchip_psci_pm_ops; 409 rockchip_sec_entrypoint = sec_entrypoint; 410 return 0; 411 } 412 413 uintptr_t plat_get_sec_entrypoint(void) 414 { 415 assert(rockchip_sec_entrypoint); 416 return rockchip_sec_entrypoint; 417 } 418