1/* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30#ifndef __ROCKCHIP_PLAT_MACROS_S__ 31#define __ROCKCHIP_PLAT_MACROS_S__ 32 33#include <cci.h> 34#include <gic_common.h> 35#include <gicv2.h> 36#include <gicv3.h> 37#include <platform_def.h> 38 39.section .rodata.gic_reg_name, "aS" 40/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */ 41gicc_regs: 42 .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" 43 44/* Applicable only to GICv3 with SRE enabled */ 45icc_regs: 46 .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", "" 47 48/* Registers common to both GICv2 and GICv3 */ 49gicd_pend_reg: 50 .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \ 51 " Offset:\t\t\tvalue\n" 52newline: 53 .asciz "\n" 54spacer: 55 .asciz ":\t\t0x" 56 57 /* --------------------------------------------- 58 * The below utility macro prints out relevant GIC 59 * registers whenever an unhandled exception is 60 * taken in BL31 on ARM standard platforms. 61 * Expects: GICD base in x16, GICC base in x17 62 * Clobbers: x0 - x10, sp 63 * --------------------------------------------- 64 */ 65 .macro plat_print_gic_regs 66 67 mov_imm x16, PLAT_RK_GICD_BASE 68 mov_imm x17, PLAT_RK_GICC_BASE 69 70 /* Check for GICv3 system register access */ 71 mrs x7, id_aa64pfr0_el1 72 ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH 73 cmp x7, #1 74 b.ne print_gicv2 75 76 /* Check for SRE enable */ 77 mrs x8, ICC_SRE_EL3 78 tst x8, #ICC_SRE_SRE_BIT 79 b.eq print_gicv2 80 81 /* Load the icc reg list to x6 */ 82 adr x6, icc_regs 83 /* Load the icc regs to gp regs used by str_in_crash_buf_print */ 84 mrs x8, ICC_HPPIR0_EL1 85 mrs x9, ICC_HPPIR1_EL1 86 mrs x10, ICC_CTLR_EL3 87 /* Store to the crash buf and print to console */ 88 bl str_in_crash_buf_print 89 b print_gic_common 90 91print_gicv2: 92 /* Load the gicc reg list to x6 */ 93 adr x6, gicc_regs 94 /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ 95 ldr w8, [x17, #GICC_HPPIR] 96 ldr w9, [x17, #GICC_AHPPIR] 97 ldr w10, [x17, #GICC_CTLR] 98 /* Store to the crash buf and print to console */ 99 bl str_in_crash_buf_print 100 101print_gic_common: 102 /* Print the GICD_ISPENDR regs */ 103 add x7, x16, #GICD_ISPENDR 104 adr x4, gicd_pend_reg 105 bl asm_print_str 106gicd_ispendr_loop: 107 sub x4, x7, x16 108 cmp x4, #0x280 109 b.eq exit_print_gic_regs 110 bl asm_print_hex 111 112 adr x4, spacer 113 bl asm_print_str 114 115 ldr x4, [x7], #8 116 bl asm_print_hex 117 118 adr x4, newline 119 bl asm_print_str 120 b gicd_ispendr_loop 121exit_print_gic_regs: 122 .endm 123 124.section .rodata.cci_reg_name, "aS" 125cci_iface_regs: 126 .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" 127 128 /* ------------------------------------------------ 129 * The below macro prints out relevant interconnect 130 * registers whenever an unhandled exception is 131 * taken in BL3-1. 132 * Clobbers: x0 - x9, sp 133 * ------------------------------------------------ 134 */ 135 .macro plat_print_interconnect_regs 136#if PLATFORM_CLUSTER_COUNT > 1 137 adr x6, cci_iface_regs 138 /* Store in x7 the base address of the first interface */ 139 mov_imm x7, (PLAT_RK_CCI_BASE + SLAVE_IFACE_OFFSET( \ 140 PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX)) 141 ldr w8, [x7, #SNOOP_CTRL_REG] 142 /* Store in x7 the base address of the second interface */ 143 mov_imm x7, (PLAT_RK_CCI_BASE + SLAVE_IFACE_OFFSET( \ 144 PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX)) 145 ldr w9, [x7, #SNOOP_CTRL_REG] 146 /* Store to the crash buf and print to console */ 147 bl str_in_crash_buf_print 148#endif 149 .endm 150 151#endif /* __ROCKCHIP_PLAT_MACROS_S__ */ 152