1/* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30#ifndef __ROCKCHIP_PLAT_MACROS_S__ 31#define __ROCKCHIP_PLAT_MACROS_S__ 32 33#include <cci.h> 34#include <gic_common.h> 35#include <gicv2.h> 36#include <gicv3.h> 37#include <platform_def.h> 38 39.section .rodata.gic_reg_name, "aS" 40/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */ 41gicc_regs: 42 .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" 43 44/* Applicable only to GICv3 with SRE enabled */ 45icc_regs: 46 .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", "" 47 48/* Registers common to both GICv2 and GICv3 */ 49gicd_pend_reg: 50 .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \ 51 " Offset:\t\t\tvalue\n" 52newline: 53 .asciz "\n" 54spacer: 55 .asciz ":\t\t0x" 56 57.section .rodata.cci_reg_name, "aS" 58cci_iface_regs: 59 .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" 60 61 /* --------------------------------------------- 62 * The below utility macro prints out relevant GIC 63 * and CCI registers whenever an unhandled 64 * exception is taken in BL31. 65 * Expects: GICD base in x16, GICC base in x17 66 * Clobbers: x0 - x10, sp 67 * --------------------------------------------- 68 */ 69 .macro plat_crash_print_regs 70 71 mov_imm x16, PLAT_RK_GICD_BASE 72 mov_imm x17, PLAT_RK_GICC_BASE 73 74 /* Check for GICv3 system register access */ 75 mrs x7, id_aa64pfr0_el1 76 ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH 77 cmp x7, #1 78 b.ne print_gicv2 79 80 /* Check for SRE enable */ 81 mrs x8, ICC_SRE_EL3 82 tst x8, #ICC_SRE_SRE_BIT 83 b.eq print_gicv2 84 85 /* Load the icc reg list to x6 */ 86 adr x6, icc_regs 87 /* Load the icc regs to gp regs used by str_in_crash_buf_print */ 88 mrs x8, ICC_HPPIR0_EL1 89 mrs x9, ICC_HPPIR1_EL1 90 mrs x10, ICC_CTLR_EL3 91 /* Store to the crash buf and print to console */ 92 bl str_in_crash_buf_print 93 b print_gic_common 94 95print_gicv2: 96 /* Load the gicc reg list to x6 */ 97 adr x6, gicc_regs 98 /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ 99 ldr w8, [x17, #GICC_HPPIR] 100 ldr w9, [x17, #GICC_AHPPIR] 101 ldr w10, [x17, #GICC_CTLR] 102 /* Store to the crash buf and print to console */ 103 bl str_in_crash_buf_print 104 105print_gic_common: 106 /* Print the GICD_ISPENDR regs */ 107 add x7, x16, #GICD_ISPENDR 108 adr x4, gicd_pend_reg 109 bl asm_print_str 110gicd_ispendr_loop: 111 sub x4, x7, x16 112 cmp x4, #0x280 113 b.eq exit_print_gic_regs 114 bl asm_print_hex 115 116 adr x4, spacer 117 bl asm_print_str 118 119 ldr x4, [x7], #8 120 bl asm_print_hex 121 122 adr x4, newline 123 bl asm_print_str 124 b gicd_ispendr_loop 125exit_print_gic_regs: 126 127#if PLATFORM_CLUSTER_COUNT > 1 128 adr x6, cci_iface_regs 129 /* Store in x7 the base address of the first interface */ 130 mov_imm x7, (PLAT_RK_CCI_BASE + SLAVE_IFACE_OFFSET( \ 131 PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX)) 132 ldr w8, [x7, #SNOOP_CTRL_REG] 133 /* Store in x7 the base address of the second interface */ 134 mov_imm x7, (PLAT_RK_CCI_BASE + SLAVE_IFACE_OFFSET( \ 135 PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX)) 136 ldr w9, [x7, #SNOOP_CTRL_REG] 137 /* Store to the crash buf and print to console */ 138 bl str_in_crash_buf_print 139#endif 140 .endm 141 142#endif /* __ROCKCHIP_PLAT_MACROS_S__ */ 143