16fba6e04STony Xie/* 26fba6e04STony Xie * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 36fba6e04STony Xie * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 56fba6e04STony Xie */ 6*c3cf06f1SAntonio Nino Diaz#ifndef ROCKCHIP_PLAT_MACROS_S 7*c3cf06f1SAntonio Nino Diaz#define ROCKCHIP_PLAT_MACROS_S 86fba6e04STony Xie 96fba6e04STony Xie#include <cci.h> 106fba6e04STony Xie#include <gic_common.h> 116fba6e04STony Xie#include <gicv2.h> 126fba6e04STony Xie#include <gicv3.h> 136fba6e04STony Xie#include <platform_def.h> 146fba6e04STony Xie 156fba6e04STony Xie.section .rodata.gic_reg_name, "aS" 166fba6e04STony Xie/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */ 176fba6e04STony Xiegicc_regs: 186fba6e04STony Xie .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" 196fba6e04STony Xie 206fba6e04STony Xie/* Applicable only to GICv3 with SRE enabled */ 216fba6e04STony Xieicc_regs: 226fba6e04STony Xie .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", "" 236fba6e04STony Xie 246fba6e04STony Xie/* Registers common to both GICv2 and GICv3 */ 256fba6e04STony Xiegicd_pend_reg: 266fba6e04STony Xie .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \ 276fba6e04STony Xie " Offset:\t\t\tvalue\n" 286fba6e04STony Xienewline: 296fba6e04STony Xie .asciz "\n" 306fba6e04STony Xiespacer: 316fba6e04STony Xie .asciz ":\t\t0x" 326fba6e04STony Xie 339ff67fa6SGerald Lejeune.section .rodata.cci_reg_name, "aS" 349ff67fa6SGerald Lejeunecci_iface_regs: 359ff67fa6SGerald Lejeune .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" 369ff67fa6SGerald Lejeune 376fba6e04STony Xie /* --------------------------------------------- 386fba6e04STony Xie * The below utility macro prints out relevant GIC 399ff67fa6SGerald Lejeune * and CCI registers whenever an unhandled 409ff67fa6SGerald Lejeune * exception is taken in BL31. 41890abc33SJulius Werner * Expects: GICD base in x26, GICC base in x27 426fba6e04STony Xie * Clobbers: x0 - x10, sp 436fba6e04STony Xie * --------------------------------------------- 446fba6e04STony Xie */ 459ff67fa6SGerald Lejeune .macro plat_crash_print_regs 466fba6e04STony Xie 47890abc33SJulius Werner mov_imm x26, PLAT_RK_GICD_BASE 48890abc33SJulius Werner mov_imm x27, PLAT_RK_GICC_BASE 496fba6e04STony Xie 506fba6e04STony Xie /* Check for GICv3 system register access */ 516fba6e04STony Xie mrs x7, id_aa64pfr0_el1 526fba6e04STony Xie ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH 536fba6e04STony Xie cmp x7, #1 546fba6e04STony Xie b.ne print_gicv2 556fba6e04STony Xie 566fba6e04STony Xie /* Check for SRE enable */ 576fba6e04STony Xie mrs x8, ICC_SRE_EL3 586fba6e04STony Xie tst x8, #ICC_SRE_SRE_BIT 596fba6e04STony Xie b.eq print_gicv2 606fba6e04STony Xie 616fba6e04STony Xie /* Load the icc reg list to x6 */ 626fba6e04STony Xie adr x6, icc_regs 636fba6e04STony Xie /* Load the icc regs to gp regs used by str_in_crash_buf_print */ 646fba6e04STony Xie mrs x8, ICC_HPPIR0_EL1 656fba6e04STony Xie mrs x9, ICC_HPPIR1_EL1 666fba6e04STony Xie mrs x10, ICC_CTLR_EL3 676fba6e04STony Xie /* Store to the crash buf and print to console */ 686fba6e04STony Xie bl str_in_crash_buf_print 696fba6e04STony Xie b print_gic_common 706fba6e04STony Xie 716fba6e04STony Xieprint_gicv2: 726fba6e04STony Xie /* Load the gicc reg list to x6 */ 736fba6e04STony Xie adr x6, gicc_regs 746fba6e04STony Xie /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ 75890abc33SJulius Werner ldr w8, [x27, #GICC_HPPIR] 76890abc33SJulius Werner ldr w9, [x27, #GICC_AHPPIR] 77890abc33SJulius Werner ldr w10, [x27, #GICC_CTLR] 786fba6e04STony Xie /* Store to the crash buf and print to console */ 796fba6e04STony Xie bl str_in_crash_buf_print 806fba6e04STony Xie 816fba6e04STony Xieprint_gic_common: 826fba6e04STony Xie /* Print the GICD_ISPENDR regs */ 83890abc33SJulius Werner add x7, x26, #GICD_ISPENDR 846fba6e04STony Xie adr x4, gicd_pend_reg 856fba6e04STony Xie bl asm_print_str 866fba6e04STony Xiegicd_ispendr_loop: 87890abc33SJulius Werner sub x4, x7, x26 886fba6e04STony Xie cmp x4, #0x280 896fba6e04STony Xie b.eq exit_print_gic_regs 906fba6e04STony Xie bl asm_print_hex 916fba6e04STony Xie 926fba6e04STony Xie adr x4, spacer 936fba6e04STony Xie bl asm_print_str 946fba6e04STony Xie 956fba6e04STony Xie ldr x4, [x7], #8 966fba6e04STony Xie bl asm_print_hex 976fba6e04STony Xie 986fba6e04STony Xie adr x4, newline 996fba6e04STony Xie bl asm_print_str 1006fba6e04STony Xie b gicd_ispendr_loop 1016fba6e04STony Xieexit_print_gic_regs: 1026fba6e04STony Xie 1036fba6e04STony Xie#if PLATFORM_CLUSTER_COUNT > 1 1046fba6e04STony Xie adr x6, cci_iface_regs 1056fba6e04STony Xie /* Store in x7 the base address of the first interface */ 1066fba6e04STony Xie mov_imm x7, (PLAT_RK_CCI_BASE + SLAVE_IFACE_OFFSET( \ 1076fba6e04STony Xie PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX)) 1086fba6e04STony Xie ldr w8, [x7, #SNOOP_CTRL_REG] 1096fba6e04STony Xie /* Store in x7 the base address of the second interface */ 1106fba6e04STony Xie mov_imm x7, (PLAT_RK_CCI_BASE + SLAVE_IFACE_OFFSET( \ 1116fba6e04STony Xie PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX)) 1126fba6e04STony Xie ldr w9, [x7, #SNOOP_CTRL_REG] 1136fba6e04STony Xie /* Store to the crash buf and print to console */ 1146fba6e04STony Xie bl str_in_crash_buf_print 1156fba6e04STony Xie#endif 1166fba6e04STony Xie .endm 1176fba6e04STony Xie 118*c3cf06f1SAntonio Nino Diaz#endif /* ROCKCHIP_PLAT_MACROS_S */ 119