1*6fba6e04STony Xie/* 2*6fba6e04STony Xie * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3*6fba6e04STony Xie * 4*6fba6e04STony Xie * Redistribution and use in source and binary forms, with or without 5*6fba6e04STony Xie * modification, are permitted provided that the following conditions are met: 6*6fba6e04STony Xie * 7*6fba6e04STony Xie * Redistributions of source code must retain the above copyright notice, this 8*6fba6e04STony Xie * list of conditions and the following disclaimer. 9*6fba6e04STony Xie * 10*6fba6e04STony Xie * Redistributions in binary form must reproduce the above copyright notice, 11*6fba6e04STony Xie * this list of conditions and the following disclaimer in the documentation 12*6fba6e04STony Xie * and/or other materials provided with the distribution. 13*6fba6e04STony Xie * 14*6fba6e04STony Xie * Neither the name of ARM nor the names of its contributors may be used 15*6fba6e04STony Xie * to endorse or promote products derived from this software without specific 16*6fba6e04STony Xie * prior written permission. 17*6fba6e04STony Xie * 18*6fba6e04STony Xie * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*6fba6e04STony Xie * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*6fba6e04STony Xie * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*6fba6e04STony Xie * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*6fba6e04STony Xie * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*6fba6e04STony Xie * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*6fba6e04STony Xie * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*6fba6e04STony Xie * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*6fba6e04STony Xie * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*6fba6e04STony Xie * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*6fba6e04STony Xie * POSSIBILITY OF SUCH DAMAGE. 29*6fba6e04STony Xie */ 30*6fba6e04STony Xie#ifndef __ROCKCHIP_PLAT_MACROS_S__ 31*6fba6e04STony Xie#define __ROCKCHIP_PLAT_MACROS_S__ 32*6fba6e04STony Xie 33*6fba6e04STony Xie#include <cci.h> 34*6fba6e04STony Xie#include <gic_common.h> 35*6fba6e04STony Xie#include <gicv2.h> 36*6fba6e04STony Xie#include <gicv3.h> 37*6fba6e04STony Xie#include <platform_def.h> 38*6fba6e04STony Xie 39*6fba6e04STony Xie.section .rodata.gic_reg_name, "aS" 40*6fba6e04STony Xie/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */ 41*6fba6e04STony Xiegicc_regs: 42*6fba6e04STony Xie .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" 43*6fba6e04STony Xie 44*6fba6e04STony Xie/* Applicable only to GICv3 with SRE enabled */ 45*6fba6e04STony Xieicc_regs: 46*6fba6e04STony Xie .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", "" 47*6fba6e04STony Xie 48*6fba6e04STony Xie/* Registers common to both GICv2 and GICv3 */ 49*6fba6e04STony Xiegicd_pend_reg: 50*6fba6e04STony Xie .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \ 51*6fba6e04STony Xie " Offset:\t\t\tvalue\n" 52*6fba6e04STony Xienewline: 53*6fba6e04STony Xie .asciz "\n" 54*6fba6e04STony Xiespacer: 55*6fba6e04STony Xie .asciz ":\t\t0x" 56*6fba6e04STony Xie 57*6fba6e04STony Xie /* --------------------------------------------- 58*6fba6e04STony Xie * The below utility macro prints out relevant GIC 59*6fba6e04STony Xie * registers whenever an unhandled exception is 60*6fba6e04STony Xie * taken in BL31 on ARM standard platforms. 61*6fba6e04STony Xie * Expects: GICD base in x16, GICC base in x17 62*6fba6e04STony Xie * Clobbers: x0 - x10, sp 63*6fba6e04STony Xie * --------------------------------------------- 64*6fba6e04STony Xie */ 65*6fba6e04STony Xie .macro plat_print_gic_regs 66*6fba6e04STony Xie 67*6fba6e04STony Xie mov_imm x16, PLAT_RK_GICD_BASE 68*6fba6e04STony Xie mov_imm x17, PLAT_RK_GICC_BASE 69*6fba6e04STony Xie 70*6fba6e04STony Xie /* Check for GICv3 system register access */ 71*6fba6e04STony Xie mrs x7, id_aa64pfr0_el1 72*6fba6e04STony Xie ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH 73*6fba6e04STony Xie cmp x7, #1 74*6fba6e04STony Xie b.ne print_gicv2 75*6fba6e04STony Xie 76*6fba6e04STony Xie /* Check for SRE enable */ 77*6fba6e04STony Xie mrs x8, ICC_SRE_EL3 78*6fba6e04STony Xie tst x8, #ICC_SRE_SRE_BIT 79*6fba6e04STony Xie b.eq print_gicv2 80*6fba6e04STony Xie 81*6fba6e04STony Xie /* Load the icc reg list to x6 */ 82*6fba6e04STony Xie adr x6, icc_regs 83*6fba6e04STony Xie /* Load the icc regs to gp regs used by str_in_crash_buf_print */ 84*6fba6e04STony Xie mrs x8, ICC_HPPIR0_EL1 85*6fba6e04STony Xie mrs x9, ICC_HPPIR1_EL1 86*6fba6e04STony Xie mrs x10, ICC_CTLR_EL3 87*6fba6e04STony Xie /* Store to the crash buf and print to console */ 88*6fba6e04STony Xie bl str_in_crash_buf_print 89*6fba6e04STony Xie b print_gic_common 90*6fba6e04STony Xie 91*6fba6e04STony Xieprint_gicv2: 92*6fba6e04STony Xie /* Load the gicc reg list to x6 */ 93*6fba6e04STony Xie adr x6, gicc_regs 94*6fba6e04STony Xie /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ 95*6fba6e04STony Xie ldr w8, [x17, #GICC_HPPIR] 96*6fba6e04STony Xie ldr w9, [x17, #GICC_AHPPIR] 97*6fba6e04STony Xie ldr w10, [x17, #GICC_CTLR] 98*6fba6e04STony Xie /* Store to the crash buf and print to console */ 99*6fba6e04STony Xie bl str_in_crash_buf_print 100*6fba6e04STony Xie 101*6fba6e04STony Xieprint_gic_common: 102*6fba6e04STony Xie /* Print the GICD_ISPENDR regs */ 103*6fba6e04STony Xie add x7, x16, #GICD_ISPENDR 104*6fba6e04STony Xie adr x4, gicd_pend_reg 105*6fba6e04STony Xie bl asm_print_str 106*6fba6e04STony Xiegicd_ispendr_loop: 107*6fba6e04STony Xie sub x4, x7, x16 108*6fba6e04STony Xie cmp x4, #0x280 109*6fba6e04STony Xie b.eq exit_print_gic_regs 110*6fba6e04STony Xie bl asm_print_hex 111*6fba6e04STony Xie 112*6fba6e04STony Xie adr x4, spacer 113*6fba6e04STony Xie bl asm_print_str 114*6fba6e04STony Xie 115*6fba6e04STony Xie ldr x4, [x7], #8 116*6fba6e04STony Xie bl asm_print_hex 117*6fba6e04STony Xie 118*6fba6e04STony Xie adr x4, newline 119*6fba6e04STony Xie bl asm_print_str 120*6fba6e04STony Xie b gicd_ispendr_loop 121*6fba6e04STony Xieexit_print_gic_regs: 122*6fba6e04STony Xie .endm 123*6fba6e04STony Xie 124*6fba6e04STony Xie.section .rodata.cci_reg_name, "aS" 125*6fba6e04STony Xiecci_iface_regs: 126*6fba6e04STony Xie .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" 127*6fba6e04STony Xie 128*6fba6e04STony Xie /* ------------------------------------------------ 129*6fba6e04STony Xie * The below macro prints out relevant interconnect 130*6fba6e04STony Xie * registers whenever an unhandled exception is 131*6fba6e04STony Xie * taken in BL3-1. 132*6fba6e04STony Xie * Clobbers: x0 - x9, sp 133*6fba6e04STony Xie * ------------------------------------------------ 134*6fba6e04STony Xie */ 135*6fba6e04STony Xie .macro plat_print_interconnect_regs 136*6fba6e04STony Xie#if PLATFORM_CLUSTER_COUNT > 1 137*6fba6e04STony Xie adr x6, cci_iface_regs 138*6fba6e04STony Xie /* Store in x7 the base address of the first interface */ 139*6fba6e04STony Xie mov_imm x7, (PLAT_RK_CCI_BASE + SLAVE_IFACE_OFFSET( \ 140*6fba6e04STony Xie PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX)) 141*6fba6e04STony Xie ldr w8, [x7, #SNOOP_CTRL_REG] 142*6fba6e04STony Xie /* Store in x7 the base address of the second interface */ 143*6fba6e04STony Xie mov_imm x7, (PLAT_RK_CCI_BASE + SLAVE_IFACE_OFFSET( \ 144*6fba6e04STony Xie PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX)) 145*6fba6e04STony Xie ldr w9, [x7, #SNOOP_CTRL_REG] 146*6fba6e04STony Xie /* Store to the crash buf and print to console */ 147*6fba6e04STony Xie bl str_in_crash_buf_print 148*6fba6e04STony Xie#endif 149*6fba6e04STony Xie .endm 150*6fba6e04STony Xie 151*6fba6e04STony Xie#endif /* __ROCKCHIP_PLAT_MACROS_S__ */ 152