1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 18 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #ifndef __PMU_COM_H__ 28 #define __PMU_COM_H__ 29 30 /* 31 * Use this macro to instantiate lock before it is used in below 32 * rockchip_pd_lock_xxx() macros 33 */ 34 DECLARE_BAKERY_LOCK(rockchip_pd_lock); 35 36 /* 37 * These are wrapper macros to the powe domain Bakery Lock API. 38 */ 39 #define rockchip_pd_lock_init() bakery_lock_init(&rockchip_pd_lock) 40 #define rockchip_pd_lock_get() bakery_lock_get(&rockchip_pd_lock) 41 #define rockchip_pd_lock_rls() bakery_lock_release(&rockchip_pd_lock) 42 43 /***************************************************************************** 44 * power domain on or off 45 *****************************************************************************/ 46 enum pmu_pd_state { 47 pmu_pd_on = 0, 48 pmu_pd_off = 1 49 }; 50 51 #pragma weak plat_ic_get_pending_interrupt_id 52 #pragma weak pmu_power_domain_ctr 53 #pragma weak check_cpu_wfie 54 55 static inline uint32_t pmu_power_domain_st(uint32_t pd) 56 { 57 uint32_t pwrdn_st = mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & BIT(pd); 58 59 if (pwrdn_st) 60 return pmu_pd_off; 61 else 62 return pmu_pd_on; 63 } 64 65 static int pmu_power_domain_ctr(uint32_t pd, uint32_t pd_state) 66 { 67 uint32_t val; 68 uint32_t loop = 0; 69 int ret = 0; 70 71 rockchip_pd_lock_get(); 72 73 val = mmio_read_32(PMU_BASE + PMU_PWRDN_CON); 74 if (pd_state == pmu_pd_off) 75 val |= BIT(pd); 76 else 77 val &= ~BIT(pd); 78 79 mmio_write_32(PMU_BASE + PMU_PWRDN_CON, val); 80 dsb(); 81 82 while ((pmu_power_domain_st(pd) != pd_state) && (loop < PD_CTR_LOOP)) { 83 udelay(1); 84 loop++; 85 } 86 87 if (pmu_power_domain_st(pd) != pd_state) { 88 WARN("%s: %d, %d, error!\n", __func__, pd, pd_state); 89 ret = -EINVAL; 90 } 91 92 rockchip_pd_lock_rls(); 93 94 return ret; 95 } 96 97 static int check_cpu_wfie(uint32_t cpu_id, uint32_t wfie_msk) 98 { 99 uint32_t cluster_id, loop = 0; 100 101 if (cpu_id >= PLATFORM_CLUSTER0_CORE_COUNT) { 102 cluster_id = 1; 103 cpu_id -= PLATFORM_CLUSTER0_CORE_COUNT; 104 } else { 105 cluster_id = 0; 106 } 107 108 if (cluster_id) 109 wfie_msk <<= (clstb_cpu_wfe + cpu_id); 110 else 111 wfie_msk <<= (clstl_cpu_wfe + cpu_id); 112 113 while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) & wfie_msk) && 114 (loop < CHK_CPU_LOOP)) { 115 udelay(1); 116 loop++; 117 } 118 119 if ((mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) & wfie_msk) == 0) { 120 WARN("%s: %d, %d, %d, error!\n", __func__, 121 cluster_id, cpu_id, wfie_msk); 122 return -EINVAL; 123 } 124 125 return 0; 126 } 127 128 #endif /* __PMU_COM_H__ */ 129