1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PMU_COM_H__ 32 #define __PMU_COM_H__ 33 34 /* 35 * Use this macro to instantiate lock before it is used in below 36 * rockchip_pd_lock_xxx() macros 37 */ 38 DECLARE_BAKERY_LOCK(rockchip_pd_lock); 39 40 /* 41 * These are wrapper macros to the powe domain Bakery Lock API. 42 */ 43 #define rockchip_pd_lock_init() bakery_lock_init(&rockchip_pd_lock) 44 #define rockchip_pd_lock_get() bakery_lock_get(&rockchip_pd_lock) 45 #define rockchip_pd_lock_rls() bakery_lock_release(&rockchip_pd_lock) 46 47 /***************************************************************************** 48 * power domain on or off 49 *****************************************************************************/ 50 enum pmu_pd_state { 51 pmu_pd_on = 0, 52 pmu_pd_off = 1 53 }; 54 55 #pragma weak plat_ic_get_pending_interrupt_id 56 #pragma weak pmu_power_domain_ctr 57 #pragma weak check_cpu_wfie 58 59 static inline uint32_t pmu_power_domain_st(uint32_t pd) 60 { 61 uint32_t pwrdn_st = mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & BIT(pd); 62 63 if (pwrdn_st) 64 return pmu_pd_off; 65 else 66 return pmu_pd_on; 67 } 68 69 static int pmu_power_domain_ctr(uint32_t pd, uint32_t pd_state) 70 { 71 uint32_t val; 72 uint32_t loop = 0; 73 int ret = 0; 74 75 rockchip_pd_lock_get(); 76 77 val = mmio_read_32(PMU_BASE + PMU_PWRDN_CON); 78 if (pd_state == pmu_pd_off) 79 val |= BIT(pd); 80 else 81 val &= ~BIT(pd); 82 83 mmio_write_32(PMU_BASE + PMU_PWRDN_CON, val); 84 dsb(); 85 86 while ((pmu_power_domain_st(pd) != pd_state) && (loop < PD_CTR_LOOP)) { 87 udelay(1); 88 loop++; 89 } 90 91 if (pmu_power_domain_st(pd) != pd_state) { 92 WARN("%s: %d, %d, error!\n", __func__, pd, pd_state); 93 ret = -EINVAL; 94 } 95 96 rockchip_pd_lock_rls(); 97 98 return ret; 99 } 100 101 static int check_cpu_wfie(uint32_t cpu_id, uint32_t wfie_msk) 102 { 103 uint32_t cluster_id, loop = 0; 104 105 if (cpu_id >= PLATFORM_CLUSTER0_CORE_COUNT) { 106 cluster_id = 1; 107 cpu_id -= PLATFORM_CLUSTER0_CORE_COUNT; 108 } else { 109 cluster_id = 0; 110 } 111 112 if (cluster_id) 113 wfie_msk <<= (clstb_cpu_wfe + cpu_id); 114 else 115 wfie_msk <<= (clstl_cpu_wfe + cpu_id); 116 117 while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) & wfie_msk) && 118 (loop < CHK_CPU_LOOP)) { 119 udelay(1); 120 loop++; 121 } 122 123 if ((mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) & wfie_msk) == 0) { 124 WARN("%s: %d, %d, %d, error!\n", __func__, 125 cluster_id, cpu_id, wfie_msk); 126 return -EINVAL; 127 } 128 129 return 0; 130 } 131 132 #endif /* __PMU_COM_H__ */ 133